Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version      : Vivado v.2023.1 (lin64) Build 3865809 Sun May  7 15:04:56 MDT 2023
| Date              : Fri May 30 17:26:48 2025
| Host              : linux-139028 running 64-bit Debian GNU/Linux 12 (bookworm)
| Command           : report_timing_summary -max_paths 10 -report_unconstrained -file d_1_wrapper_timing_summary_routed.rpt -pb d_1_wrapper_timing_summary_routed.pb -rpx d_1_wrapper_timing_summary_routed.rpx -warn_on_violation
| Design            : d_1_wrapper
| Device            : xczu28dr-ffvg1517
| Speed File        : -2  PRODUCTION 1.30 05-03-2022
| Design State      : Routed
| Temperature Grade : E
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

Rule       Severity  Description                                                                                            Violations  
---------  --------  -----------------------------------------------------------------------------------------------------  ----------  
LUTAR-1    Warning   LUT drives async reset alert                                                                           24          
TIMING-9   Warning   Unknown CDC Logic                                                                                      1           
TIMING-10  Warning   Missing property on synchronizer                                                                       1           
TIMING-18  Warning   Missing input or output delay                                                                          8           
TIMING-24  Warning   Overridden Max delay datapath only                                                                     12          
TIMING-47  Warning   False path, asynchronous clock group or max delay datapath only constraint between synchronous clocks  2           
CLKC-40    Advisory  Substitute PLLE4 for MMCME4 check                                                                      1           
CLKC-56    Advisory  MMCME4 with global clock driver has no LOC                                                             2           
XDCB-6     Advisory  Timing constraint pointing to hierarchical pins                                                        1           

Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (2)
6. checking no_output_delay (9)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (2)
------------------------------
 There are 2 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (9)
-------------------------------
 There are 9 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.019        0.000                      0               791336        0.007        0.000                      0               790634        0.000        0.000                       0                273637  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock                                                                                                Waveform(ns)           Period(ns)      Frequency(MHz)
-----                                                                                                ------------           ----------      --------------
RFADC0_CLK                                                                                           {0.000 1.953}          3.906           256.016         
  clk_out1_d_1_clk_adc0_x2_0                                                                         {0.000 0.976}          1.953           512.033         
RFADC0_CLK_dummy                                                                                     {0.000 1.953}          3.906           256.016         
RFADC1_CLK                                                                                           {0.000 5.000}          10.000          100.000         
RFADC1_CLK_dummy                                                                                     {0.000 5.000}          10.000          100.000         
RFADC1_FABCLK0                                                                                       {0.000 5.000}          10.000          100.000         
RFADC1_FABCLK1                                                                                       {0.000 5.000}          10.000          100.000         
RFADC1_FABCLK2                                                                                       {0.000 5.000}          10.000          100.000         
RFADC1_FABCLK3                                                                                       {0.000 5.000}          10.000          100.000         
RFADC2_CLK                                                                                           {0.000 1.953}          3.906           256.016         
RFADC2_CLK_dummy                                                                                     {0.000 1.953}          3.906           256.016         
RFADC3_CLK                                                                                           {0.000 5.000}          10.000          100.000         
RFADC3_CLK_dummy                                                                                     {0.000 5.000}          10.000          100.000         
RFADC3_FABCLK0                                                                                       {0.000 5.000}          10.000          100.000         
RFADC3_FABCLK1                                                                                       {0.000 5.000}          10.000          100.000         
RFADC3_FABCLK2                                                                                       {0.000 5.000}          10.000          100.000         
RFADC3_FABCLK3                                                                                       {0.000 5.000}          10.000          100.000         
RFDAC0_CLK                                                                                           {0.000 1.302}          2.604           384.025         
RFDAC1_CLK                                                                                           {0.000 1.302}          2.604           384.025         
clk_pl_0                                                                                             {0.000 5.000}          10.000          100.000         
  clk_out1_d_1_clk_core_0                                                                            {0.000 2.500}          5.000           200.000         
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {0.000 25.000}         50.000          20.000          
sys_clk_ddr4_clk_p                                                                                   {0.000 1.667}          3.334           299.940         
  mmcm_clkout0                                                                                       {0.000 1.500}          3.001           333.267         
    pll_clk[0]                                                                                       {0.000 0.188}          0.375           2666.133        
      pll_clk[0]_DIV                                                                                 {0.000 1.500}          3.001           333.267         
    pll_clk[1]                                                                                       {0.000 0.188}          0.375           2666.133        
      pll_clk[1]_DIV                                                                                 {0.000 1.500}          3.001           333.267         
    pll_clk[2]                                                                                       {0.000 0.188}          0.375           2666.133        
      pll_clk[2]_DIV                                                                                 {0.000 1.500}          3.001           333.267         
  mmcm_clkout5                                                                                       {0.000 6.001}          12.002          83.317          
  mmcm_clkout6                                                                                       {0.000 3.001}          6.001           166.633         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                                                                                                    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                                                                                                    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
RFADC0_CLK                                                                                                 3.148        0.000                      0                   46        0.035        0.000                      0                   46        0.586        0.000                       0                    37  
  clk_out1_d_1_clk_adc0_x2_0                                                                               0.019        0.000                      0               257625        0.007        0.000                      0               257625        0.030        0.000                       0                 83059  
RFDAC0_CLK                                                                                                 0.034        0.000                      0               228636        0.010        0.000                      0               228636        0.502        0.000                       0                 86230  
clk_pl_0                                                                                                   2.061        0.000                      0               169566        0.010        0.000                      0               169566        2.000        0.000                       0                 55462  
  clk_out1_d_1_clk_core_0                                                                                  0.287        0.000                      0                14030        0.022        0.000                      0                14030        1.958        0.000                       0                  4522  
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK       11.071        0.000                      0                  992        0.032        0.000                      0                  992       24.468        0.000                       0                   479  
sys_clk_ddr4_clk_p                                                                                         1.760        0.000                      0                   23        0.054        0.000                      0                   23        0.500        0.000                       0                    19  
  mmcm_clkout0                                                                                             0.078        0.000                      0               109910        0.010        0.000                      0               109910        0.000        0.000                       0                 41407  
    pll_clk[0]                                                                                                                                                                                                                                         0.000        0.000                       0                     9  
      pll_clk[0]_DIV                                                                                                                                                                                                                                   0.300        0.000                       0                    40  
    pll_clk[1]                                                                                                                                                                                                                                         0.000        0.000                       0                     9  
      pll_clk[1]_DIV                                                                                                                                                                                                                                   0.300        0.000                       0                    40  
    pll_clk[2]                                                                                                                                                                                                                                         0.000        0.000                       0                     7  
      pll_clk[2]_DIV                                                                                                                                                                                                                                   0.300        0.000                       0                    25  
  mmcm_clkout5                                                                                             9.755        0.000                      0                  827        0.022        0.000                      0                  827        5.469        0.000                       0                   570  
  mmcm_clkout6                                                                                             0.768        0.000                      0                 5636        0.014        0.000                      0                 5152        0.972        0.000                       0                  1722  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock                                                                                           To Clock                                                                                                 WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                                                                                           --------                                                                                                 -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
mmcm_clkout5                                                                                         dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK       11.489        0.000                      0                    8                                                                        
mmcm_clkout5                                                                                         mmcm_clkout0                                                                                               2.315        0.000                      0                   28                                                                        
mmcm_clkout6                                                                                         mmcm_clkout0                                                                                               0.803        0.000                      0                  129                                                                        
mmcm_clkout0                                                                                         pll_clk[0]_DIV                                                                                             0.568        0.000                      0                  352        0.709        0.000                      0                  352  
mmcm_clkout0                                                                                         pll_clk[1]_DIV                                                                                             0.323        0.000                      0                  352        0.517        0.000                      0                  352  
mmcm_clkout0                                                                                         pll_clk[2]_DIV                                                                                             0.712        0.000                      0                  216        0.573        0.000                      0                  216  
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  mmcm_clkout5                                                                                              49.569        0.000                      0                    8                                                                        
mmcm_clkout0                                                                                         mmcm_clkout5                                                                                              11.546        0.000                      0                   10                                                                        
mmcm_clkout0                                                                                         mmcm_clkout6                                                                                               1.456        0.000                      0                   36        0.139        0.000                      0                    1  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group                                                                                           From Clock                                                                                           To Clock                                                                                                 WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                                                                                           ----------                                                                                           --------                                                                                                 -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
**async_default**                                                                                    clk_out1_d_1_clk_adc0_x2_0                                                                           clk_out1_d_1_clk_adc0_x2_0                                                                                 0.406        0.000                      0                    4        0.180        0.000                      0                    4  
**async_default**                                                                                    clk_out1_d_1_clk_core_0                                                                              clk_out1_d_1_clk_core_0                                                                                    1.308        0.000                      0                 2055        0.098        0.000                      0                 2055  
**async_default**                                                                                    clk_pl_0                                                                                             clk_pl_0                                                                                                   6.316        0.000                      0                  642        0.151        0.000                      0                  642  
**async_default**                                                                                    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK       46.379        0.000                      0                  100        0.097        0.000                      0                  100  
**async_default**                                                                                    mmcm_clkout5                                                                                         mmcm_clkout5                                                                                              10.483        0.000                      0                  105        0.098        0.000                      0                  105  


------------------------------------------------------------------------------------------------
| User Ignored Path Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group                                                                                           From Clock                                                                                           To Clock                                                                                           
----------                                                                                           ----------                                                                                           --------                                                                                           
(none)                                                                                               RFDAC0_CLK                                                                                                                                                                                                
(none)                                                                                                                                                                                                    RFADC0_CLK                                                                                           
(none)                                                                                                                                                                                                    RFDAC0_CLK                                                                                           
(none)                                                                                               RFDAC0_CLK                                                                                           RFDAC0_CLK                                                                                           
(none)                                                                                               clk_out1_d_1_clk_adc0_x2_0                                                                           RFDAC0_CLK                                                                                           
(none)                                                                                               clk_out1_d_1_clk_core_0                                                                              RFDAC0_CLK                                                                                           
(none)                                                                                               clk_pl_0                                                                                             RFDAC0_CLK                                                                                           
(none)                                                                                                                                                                                                    clk_out1_d_1_clk_adc0_x2_0                                                                           
(none)                                                                                               RFDAC0_CLK                                                                                           clk_out1_d_1_clk_adc0_x2_0                                                                           
(none)                                                                                               clk_pl_0                                                                                             clk_out1_d_1_clk_adc0_x2_0                                                                           
(none)                                                                                               mmcm_clkout0                                                                                         clk_out1_d_1_clk_adc0_x2_0                                                                           
(none)                                                                                                                                                                                                    clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                               RFDAC0_CLK                                                                                           clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                               clk_pl_0                                                                                             clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                                                                                                                                    clk_pl_0                                                                                             
(none)                                                                                               RFADC0_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFADC1_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFADC2_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFADC3_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFDAC0_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFDAC1_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               clk_out1_d_1_clk_adc0_x2_0                                                                           clk_pl_0                                                                                             
(none)                                                                                               clk_out1_d_1_clk_core_0                                                                              clk_pl_0                                                                                             
(none)                                                                                               clk_pl_0                                                                                             clk_pl_0                                                                                             
(none)                                                                                               mmcm_clkout5                                                                                         dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  
(none)                                                                                               RFDAC0_CLK                                                                                           mmcm_clkout0                                                                                         
(none)                                                                                               clk_out1_d_1_clk_adc0_x2_0                                                                           mmcm_clkout0                                                                                         
(none)                                                                                               clk_pl_0                                                                                             mmcm_clkout0                                                                                         
(none)                                                                                               mmcm_clkout0                                                                                         mmcm_clkout0                                                                                         
(none)                                                                                               mmcm_clkout5                                                                                         mmcm_clkout0                                                                                         
(none)                                                                                               mmcm_clkout6                                                                                         mmcm_clkout0                                                                                         
(none)                                                                                               sys_clk_ddr4_clk_p                                                                                   mmcm_clkout0                                                                                         
(none)                                                                                               dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  mmcm_clkout5                                                                                         
(none)                                                                                               mmcm_clkout0                                                                                         mmcm_clkout5                                                                                         
(none)                                                                                               mmcm_clkout0                                                                                         mmcm_clkout6                                                                                         
(none)                                                                                               mmcm_clkout6                                                                                         mmcm_clkout6                                                                                         
(none)                                                                                               sys_clk_ddr4_clk_p                                                                                   mmcm_clkout6                                                                                         
(none)                                                                                               clk_pl_0                                                                                             sys_clk_ddr4_clk_p                                                                                   


------------------------------------------------------------------------------------------------
| Unconstrained Path Table
| ------------------------
------------------------------------------------------------------------------------------------

Path Group                                                                                           From Clock                                                                                           To Clock                                                                                           
----------                                                                                           ----------                                                                                           --------                                                                                           
(none)                                                                                               clk_pl_0                                                                                                                                                                                                  
(none)                                                                                               mmcm_clkout0                                                                                                                                                                                              
(none)                                                                                                                                                                                                    clk_out1_d_1_clk_adc0_x2_0                                                                           
(none)                                                                                                                                                                                                    clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                                                                                                                                    clk_pl_0                                                                                             
(none)                                                                                                                                                                                                    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  
(none)                                                                                                                                                                                                    sys_clk_ddr4_clk_p                                                                                   


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  RFADC0_CLK
  To Clock:  RFADC0_CLK

Setup :            0  Failing Endpoints,  Worst Slack        3.148ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.035ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.586ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             3.148ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
                            (rising edge-triggered cell SRL16E clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.691ns  (logic 0.508ns (73.517%)  route 0.183ns (26.483%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.057ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.134ns = ( 6.040 - 3.906 ) 
    Source Clock Delay      (SCD):    2.515ns
    Clock Pessimism Removal (CPR):    0.325ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.988ns (routing 1.119ns, distribution 0.869ns)
  Clock Net Delay (Destination): 1.748ns (routing 1.020ns, distribution 0.728ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.988     2.515    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X75Y103        SRL16E                                       r  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y103        SRL16E (Prop_H6LUT_SLICEM_CLK_Q)
                                                      0.392     2.907 r  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/Q
                         net (fo=1, routed)           0.157     3.064    d_1_i/rst_adc0/U0/EXT_LPF/Q
    SLICE_X75Y104        LUT3 (Prop_B5LUT_SLICEM_I2_O)
                                                      0.116     3.180 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.026     3.206    d_1_i/rst_adc0/U0/EXT_LPF/lpf_int0__0
    SLICE_X75Y104        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.748     6.040    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X75Y104        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
                         clock pessimism              0.325     6.364    
                         clock uncertainty           -0.035     6.329    
    SLICE_X75Y104        FDRE (Setup_BFF2_SLICEM_C_D)
                                                      0.025     6.354    d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg
  -------------------------------------------------------------------
                         required time                          6.354    
                         arrival time                          -3.206    
  -------------------------------------------------------------------
                         slack                                  3.148    

Slack (MET) :             3.196ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.502ns  (logic 0.076ns (15.138%)  route 0.426ns (84.862%))
  Logic Levels:           0  
  Clock Path Skew:        -0.099ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.118ns = ( 6.024 - 3.906 ) 
    Source Clock Delay      (SCD):    2.492ns
    Clock Pessimism Removal (CPR):    0.275ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.965ns (routing 1.119ns, distribution 0.846ns)
  Clock Net Delay (Destination): 1.732ns (routing 1.020ns, distribution 0.712ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.965     2.492    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X75Y101        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y101        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.568 f  d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/Q
                         net (fo=6, routed)           0.426     2.994    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/seq_clr
    SLICE_X74Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.732     6.024    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X74Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
                         clock pessimism              0.275     6.299    
                         clock uncertainty           -0.035     6.264    
    SLICE_X74Y102        FDRE (Setup_DFF_SLICEL_C_R)
                                                     -0.074     6.190    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]
  -------------------------------------------------------------------
                         required time                          6.190    
                         arrival time                          -2.994    
  -------------------------------------------------------------------
                         slack                                  3.196    

Slack (MET) :             3.196ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.502ns  (logic 0.076ns (15.138%)  route 0.426ns (84.862%))
  Logic Levels:           0  
  Clock Path Skew:        -0.099ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.118ns = ( 6.024 - 3.906 ) 
    Source Clock Delay      (SCD):    2.492ns
    Clock Pessimism Removal (CPR):    0.275ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.965ns (routing 1.119ns, distribution 0.846ns)
  Clock Net Delay (Destination): 1.732ns (routing 1.020ns, distribution 0.712ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.965     2.492    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X75Y101        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y101        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.568 f  d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/Q
                         net (fo=6, routed)           0.426     2.994    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/seq_clr
    SLICE_X74Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.732     6.024    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X74Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/C
                         clock pessimism              0.275     6.299    
                         clock uncertainty           -0.035     6.264    
    SLICE_X74Y102        FDRE (Setup_DFF2_SLICEL_C_R)
                                                     -0.074     6.190    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]
  -------------------------------------------------------------------
                         required time                          6.190    
                         arrival time                          -2.994    
  -------------------------------------------------------------------
                         slack                                  3.196    

Slack (MET) :             3.227ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/lpf_asr_reg/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.660ns  (logic 0.237ns (35.909%)  route 0.423ns (64.091%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.009ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.134ns = ( 6.040 - 3.906 ) 
    Source Clock Delay      (SCD):    2.496ns
    Clock Pessimism Removal (CPR):    0.354ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.969ns (routing 1.119ns, distribution 0.850ns)
  Clock Net Delay (Destination): 1.748ns (routing 1.020ns, distribution 0.728ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.969     2.496    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/slowest_sync_clk
    SLICE_X75Y104        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y104        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     2.574 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/Q
                         net (fo=2, routed)           0.396     2.970    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/scndry_out
    SLICE_X75Y104        LUT5 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.159     3.129 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/lpf_asr_i_1/O
                         net (fo=1, routed)           0.027     3.156    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX_n_0
    SLICE_X75Y104        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_asr_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.748     6.040    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X75Y104        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_asr_reg/C
                         clock pessimism              0.354     6.393    
                         clock uncertainty           -0.035     6.358    
    SLICE_X75Y104        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     6.383    d_1_i/rst_adc0/U0/EXT_LPF/lpf_asr_reg
  -------------------------------------------------------------------
                         required time                          6.383    
                         arrival time                          -3.156    
  -------------------------------------------------------------------
                         slack                                  3.227    

Slack (MET) :             3.251ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/Core_reg/S
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.506ns  (logic 0.080ns (15.815%)  route 0.426ns (84.185%))
  Logic Levels:           0  
  Clock Path Skew:        -0.040ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.132ns = ( 6.038 - 3.906 ) 
    Source Clock Delay      (SCD):    2.496ns
    Clock Pessimism Removal (CPR):    0.325ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.969ns (routing 1.119ns, distribution 0.850ns)
  Clock Net Delay (Destination): 1.746ns (routing 1.020ns, distribution 0.726ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.969     2.496    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X75Y104        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y104        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     2.576 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/Q
                         net (fo=4, routed)           0.426     3.002    d_1_i/rst_adc0/U0/SEQ/lpf_int
    SLICE_X75Y101        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/Core_reg/S
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.746     6.038    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X75Y101        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/Core_reg/C
                         clock pessimism              0.325     6.362    
                         clock uncertainty           -0.035     6.327    
    SLICE_X75Y101        FDSE (Setup_DFF_SLICEM_C_S)
                                                     -0.074     6.253    d_1_i/rst_adc0/U0/SEQ/Core_reg
  -------------------------------------------------------------------
                         required time                          6.253    
                         arrival time                          -3.002    
  -------------------------------------------------------------------
                         slack                                  3.251    

Slack (MET) :             3.251ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/from_sys_reg/S
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.506ns  (logic 0.080ns (15.815%)  route 0.426ns (84.185%))
  Logic Levels:           0  
  Clock Path Skew:        -0.040ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.132ns = ( 6.038 - 3.906 ) 
    Source Clock Delay      (SCD):    2.496ns
    Clock Pessimism Removal (CPR):    0.325ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.969ns (routing 1.119ns, distribution 0.850ns)
  Clock Net Delay (Destination): 1.746ns (routing 1.020ns, distribution 0.726ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.969     2.496    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X75Y104        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y104        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     2.576 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/Q
                         net (fo=4, routed)           0.426     3.002    d_1_i/rst_adc0/U0/SEQ/lpf_int
    SLICE_X75Y101        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/S
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.746     6.038    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X75Y101        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/C
                         clock pessimism              0.325     6.362    
                         clock uncertainty           -0.035     6.327    
    SLICE_X75Y101        FDSE (Setup_DFF2_SLICEM_C_S)
                                                     -0.074     6.253    d_1_i/rst_adc0/U0/SEQ/from_sys_reg
  -------------------------------------------------------------------
                         required time                          6.253    
                         arrival time                          -3.002    
  -------------------------------------------------------------------
                         slack                                  3.251    

Slack (MET) :             3.253ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/R
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.503ns  (logic 0.080ns (15.909%)  route 0.423ns (84.091%))
  Logic Levels:           0  
  Clock Path Skew:        -0.041ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.131ns = ( 6.037 - 3.906 ) 
    Source Clock Delay      (SCD):    2.496ns
    Clock Pessimism Removal (CPR):    0.325ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.969ns (routing 1.119ns, distribution 0.850ns)
  Clock Net Delay (Destination): 1.745ns (routing 1.020ns, distribution 0.725ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.969     2.496    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X75Y104        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y104        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     2.576 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/Q
                         net (fo=4, routed)           0.423     2.999    d_1_i/rst_adc0/U0/SEQ/lpf_int
    SLICE_X75Y101        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/R
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.745     6.037    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X75Y101        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/C
                         clock pessimism              0.325     6.361    
                         clock uncertainty           -0.035     6.326    
    SLICE_X75Y101        FDRE (Setup_EFF_SLICEM_C_R)
                                                     -0.074     6.252    d_1_i/rst_adc0/U0/SEQ/seq_clr_reg
  -------------------------------------------------------------------
                         required time                          6.252    
                         arrival time                          -2.999    
  -------------------------------------------------------------------
                         slack                                  3.253    

Slack (MET) :             3.255ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/from_sys_reg/C
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/CE
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.456ns  (logic 0.080ns (17.553%)  route 0.376ns (82.447%))
  Logic Levels:           0  
  Clock Path Skew:        -0.100ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.118ns = ( 6.024 - 3.906 ) 
    Source Clock Delay      (SCD):    2.493ns
    Clock Pessimism Removal (CPR):    0.275ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.966ns (routing 1.119ns, distribution 0.847ns)
  Clock Net Delay (Destination): 1.732ns (routing 1.020ns, distribution 0.712ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.966     2.493    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X75Y101        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y101        FDSE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     2.573 r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/Q
                         net (fo=10, routed)          0.376     2.949    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/seq_cnt_en
    SLICE_X74Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.732     6.024    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X74Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
                         clock pessimism              0.275     6.299    
                         clock uncertainty           -0.035     6.264    
    SLICE_X74Y102        FDRE (Setup_DFF_SLICEL_C_CE)
                                                     -0.060     6.204    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]
  -------------------------------------------------------------------
                         required time                          6.204    
                         arrival time                          -2.949    
  -------------------------------------------------------------------
                         slack                                  3.255    

Slack (MET) :             3.255ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/from_sys_reg/C
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/CE
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.457ns  (logic 0.080ns (17.514%)  route 0.377ns (82.486%))
  Logic Levels:           0  
  Clock Path Skew:        -0.100ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.118ns = ( 6.024 - 3.906 ) 
    Source Clock Delay      (SCD):    2.493ns
    Clock Pessimism Removal (CPR):    0.275ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.966ns (routing 1.119ns, distribution 0.847ns)
  Clock Net Delay (Destination): 1.732ns (routing 1.020ns, distribution 0.712ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.966     2.493    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X75Y101        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y101        FDSE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     2.573 r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/Q
                         net (fo=10, routed)          0.377     2.950    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/seq_cnt_en
    SLICE_X74Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.732     6.024    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X74Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/C
                         clock pessimism              0.275     6.299    
                         clock uncertainty           -0.035     6.264    
    SLICE_X74Y102        FDRE (Setup_DFF2_SLICEL_C_CE)
                                                     -0.059     6.205    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]
  -------------------------------------------------------------------
                         required time                          6.205    
                         arrival time                          -2.950    
  -------------------------------------------------------------------
                         slack                                  3.255    

Slack (MET) :             3.286ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.547ns  (logic 0.202ns (36.898%)  route 0.345ns (63.102%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.062ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.132ns = ( 6.038 - 3.906 ) 
    Source Clock Delay      (SCD):    2.469ns
    Clock Pessimism Removal (CPR):    0.275ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.942ns (routing 1.119ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.746ns (routing 1.020ns, distribution 0.726ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.942     2.469    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X74Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y102        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.548 f  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/Q
                         net (fo=6, routed)           0.278     2.826    d_1_i/rst_adc0/U0/SEQ/seq_cnt[1]
    SLICE_X75Y102        LUT4 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.123     2.949 r  d_1_i/rst_adc0/U0/SEQ/pr_dec0/O
                         net (fo=1, routed)           0.067     3.016    d_1_i/rst_adc0/U0/SEQ/pr_dec0__0
    SLICE_X75Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.746     6.038    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X75Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/C
                         clock pessimism              0.275     6.313    
                         clock uncertainty           -0.035     6.278    
    SLICE_X75Y102        FDRE (Setup_FFF_SLICEM_C_D)
                                                      0.025     6.303    d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]
  -------------------------------------------------------------------
                         required time                          6.303    
                         arrival time                          -3.016    
  -------------------------------------------------------------------
                         slack                                  3.286    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.035ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.099ns (50.140%)  route 0.098ns (49.859%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.101ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.494ns
    Source Clock Delay      (SCD):    2.118ns
    Clock Pessimism Removal (CPR):    0.275ns
  Clock Net Delay (Source):      1.732ns (routing 1.020ns, distribution 0.712ns)
  Clock Net Delay (Destination): 1.967ns (routing 1.119ns, distribution 0.848ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.732     2.118    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X74Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y102        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     2.179 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/Q
                         net (fo=5, routed)           0.085     2.264    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/Q[2]
    SLICE_X75Y102        LUT5 (Prop_D5LUT_SLICEM_I0_O)
                                                      0.038     2.302 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int[4]_i_1/O
                         net (fo=1, routed)           0.013     2.315    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int0[4]
    SLICE_X75Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.967     2.494    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X75Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]/C
                         clock pessimism             -0.275     2.219    
    SLICE_X75Y102        FDRE (Hold_DFF2_SLICEM_C_D)
                                                      0.061     2.280    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]
  -------------------------------------------------------------------
                         required time                         -2.280    
                         arrival time                           2.315    
  -------------------------------------------------------------------
                         slack                                  0.035    

Slack (MET) :             0.043ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.203ns  (logic 0.083ns (40.797%)  route 0.120ns (59.203%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.100ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.493ns
    Source Clock Delay      (SCD):    2.118ns
    Clock Pessimism Removal (CPR):    0.275ns
  Clock Net Delay (Source):      1.732ns (routing 1.020ns, distribution 0.712ns)
  Clock Net Delay (Destination): 1.966ns (routing 1.119ns, distribution 0.847ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.732     2.118    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X74Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y102        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     2.179 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/Q
                         net (fo=5, routed)           0.085     2.264    d_1_i/rst_adc0/U0/SEQ/seq_cnt[2]
    SLICE_X75Y102        LUT4 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.022     2.286 r  d_1_i/rst_adc0/U0/SEQ/pr_dec0/O
                         net (fo=1, routed)           0.035     2.321    d_1_i/rst_adc0/U0/SEQ/pr_dec0__0
    SLICE_X75Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.966     2.493    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X75Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/C
                         clock pessimism             -0.275     2.218    
    SLICE_X75Y102        FDRE (Hold_FFF_SLICEM_C_D)
                                                      0.060     2.278    d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.278    
                         arrival time                           2.321    
  -------------------------------------------------------------------
                         slack                                  0.043    

Slack (MET) :             0.044ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.097ns  (logic 0.061ns (62.876%)  route 0.036ns (37.124%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.565ns
    Source Clock Delay      (SCD):    1.339ns
    Clock Pessimism Removal (CPR):    0.221ns
  Clock Net Delay (Source):      1.076ns (routing 0.604ns, distribution 0.472ns)
  Clock Net Delay (Destination): 1.213ns (routing 0.670ns, distribution 0.543ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.076     1.339    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X75Y104        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y104        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.378 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg/Q
                         net (fo=2, routed)           0.028     1.406    d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr
    SLICE_X75Y104        LUT3 (Prop_B5LUT_SLICEM_I0_O)
                                                      0.022     1.428 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.008     1.436    d_1_i/rst_adc0/U0/EXT_LPF/lpf_int0__0
    SLICE_X75Y104        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.213     1.565    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X75Y104        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
                         clock pessimism             -0.221     1.345    
    SLICE_X75Y104        FDRE (Hold_BFF2_SLICEM_C_D)
                                                      0.047     1.392    d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg
  -------------------------------------------------------------------
                         required time                         -1.392    
                         arrival time                           1.436    
  -------------------------------------------------------------------
                         slack                                  0.044    

Slack (MET) :             0.047ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.113ns  (logic 0.039ns (34.508%)  route 0.074ns (65.492%))
  Logic Levels:           0  
  Clock Path Skew:        0.019ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.564ns
    Source Clock Delay      (SCD):    1.339ns
    Clock Pessimism Removal (CPR):    0.207ns
  Clock Net Delay (Source):      1.076ns (routing 0.604ns, distribution 0.472ns)
  Clock Net Delay (Destination): 1.212ns (routing 0.670ns, distribution 0.542ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.076     1.339    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X75Y105        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y105        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.039     1.378 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/Q
                         net (fo=2, routed)           0.074     1.452    d_1_i/rst_adc0/U0/EXT_LPF/p_3_in6_in
    SLICE_X75Y104        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.212     1.564    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X75Y104        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]/C
                         clock pessimism             -0.207     1.358    
    SLICE_X75Y104        FDRE (Hold_FFF2_SLICEM_C_D)
                                                      0.047     1.405    d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.405    
                         arrival time                           1.452    
  -------------------------------------------------------------------
                         slack                                  0.047    

Slack (MET) :             0.048ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.100ns  (logic 0.052ns (52.079%)  route 0.048ns (47.921%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.564ns
    Source Clock Delay      (SCD):    1.338ns
    Clock Pessimism Removal (CPR):    0.221ns
  Clock Net Delay (Source):      1.075ns (routing 0.604ns, distribution 0.471ns)
  Clock Net Delay (Destination): 1.212ns (routing 0.670ns, distribution 0.542ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.075     1.338    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X75Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y102        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     1.376 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/Q
                         net (fo=3, routed)           0.027     1.402    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/Q[5]
    SLICE_X75Y102        LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.014     1.416 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int[5]_i_2/O
                         net (fo=1, routed)           0.021     1.437    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int0[5]
    SLICE_X75Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.212     1.564    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X75Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/C
                         clock pessimism             -0.221     1.344    
    SLICE_X75Y102        FDRE (Hold_BFF_SLICEM_C_D)
                                                      0.046     1.390    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]
  -------------------------------------------------------------------
                         required time                         -1.390    
                         arrival time                           1.437    
  -------------------------------------------------------------------
                         slack                                  0.048    

Slack (MET) :             0.048ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[2].asr_lpf_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.101ns  (logic 0.038ns (37.624%)  route 0.063ns (62.376%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.564ns
    Source Clock Delay      (SCD):    1.338ns
    Clock Pessimism Removal (CPR):    0.221ns
  Clock Net Delay (Source):      1.075ns (routing 0.604ns, distribution 0.471ns)
  Clock Net Delay (Destination): 1.212ns (routing 0.670ns, distribution 0.542ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.075     1.338    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X75Y104        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y104        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.376 r  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/Q
                         net (fo=2, routed)           0.063     1.439    d_1_i/rst_adc0/U0/EXT_LPF/p_2_in
    SLICE_X75Y104        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[2].asr_lpf_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.212     1.564    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X75Y104        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[2].asr_lpf_reg[2]/C
                         clock pessimism             -0.221     1.344    
    SLICE_X75Y104        FDRE (Hold_EFF2_SLICEM_C_D)
                                                      0.047     1.391    d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[2].asr_lpf_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.391    
                         arrival time                           1.439    
  -------------------------------------------------------------------
                         slack                                  0.048    

Slack (MET) :             0.052ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.105ns  (logic 0.072ns (68.779%)  route 0.033ns (31.221%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.551ns
    Source Clock Delay      (SCD):    1.327ns
    Clock Pessimism Removal (CPR):    0.218ns
  Clock Net Delay (Source):      1.064ns (routing 0.604ns, distribution 0.460ns)
  Clock Net Delay (Destination): 1.199ns (routing 0.670ns, distribution 0.529ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.064     1.327    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X74Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y102        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.366 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/Q
                         net (fo=6, routed)           0.027     1.393    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/Q[1]
    SLICE_X74Y102        LUT3 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.033     1.426 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int[2]_i_1/O
                         net (fo=1, routed)           0.006     1.432    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int0[2]
    SLICE_X74Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.199     1.551    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X74Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/C
                         clock pessimism             -0.218     1.333    
    SLICE_X74Y102        FDRE (Hold_DFF2_SLICEL_C_D)
                                                      0.047     1.380    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.380    
                         arrival time                           1.432    
  -------------------------------------------------------------------
                         slack                                  0.052    

Slack (MET) :             0.055ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.161ns  (logic 0.063ns (39.087%)  route 0.098ns (60.913%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.564ns
    Source Clock Delay      (SCD):    1.327ns
    Clock Pessimism Removal (CPR):    0.177ns
  Clock Net Delay (Source):      1.064ns (routing 0.604ns, distribution 0.460ns)
  Clock Net Delay (Destination): 1.212ns (routing 0.670ns, distribution 0.542ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.064     1.327    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X74Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y102        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.368 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/Q
                         net (fo=5, routed)           0.072     1.440    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/Q[2]
    SLICE_X75Y102        LUT4 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.022     1.462 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int[3]_i_1/O
                         net (fo=1, routed)           0.026     1.488    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int0[3]
    SLICE_X75Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.212     1.564    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X75Y102        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/C
                         clock pessimism             -0.177     1.387    
    SLICE_X75Y102        FDRE (Hold_DFF_SLICEM_C_D)
                                                      0.046     1.433    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.433    
                         arrival time                           1.488    
  -------------------------------------------------------------------
                         slack                                  0.055    

Slack (MET) :             0.055ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[2].exr_lpf_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.116ns  (logic 0.061ns (52.730%)  route 0.055ns (47.270%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.565ns
    Source Clock Delay      (SCD):    1.338ns
    Clock Pessimism Removal (CPR):    0.213ns
  Clock Net Delay (Source):      1.075ns (routing 0.604ns, distribution 0.471ns)
  Clock Net Delay (Destination): 1.213ns (routing 0.670ns, distribution 0.543ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.075     1.338    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X75Y104        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[2].exr_lpf_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y104        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     1.377 r  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[2].exr_lpf_reg[2]/Q
                         net (fo=2, routed)           0.029     1.405    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/p_1_in4_in
    SLICE_X75Y104        LUT5 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.022     1.427 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/lpf_exr_i_1/O
                         net (fo=1, routed)           0.026     1.453    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT_n_0
    SLICE_X75Y104        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.213     1.565    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X75Y104        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg/C
                         clock pessimism             -0.213     1.352    
    SLICE_X75Y104        FDRE (Hold_DFF_SLICEM_C_D)
                                                      0.046     1.398    d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg
  -------------------------------------------------------------------
                         required time                         -1.398    
                         arrival time                           1.453    
  -------------------------------------------------------------------
                         slack                                  0.055    

Slack (MET) :             0.059ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/Core_reg/C
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/from_sys_reg/D
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.112ns  (logic 0.076ns (67.857%)  route 0.036ns (32.143%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.563ns
    Source Clock Delay      (SCD):    1.337ns
    Clock Pessimism Removal (CPR):    0.221ns
  Clock Net Delay (Source):      1.074ns (routing 0.604ns, distribution 0.470ns)
  Clock Net Delay (Destination): 1.211ns (routing 0.670ns, distribution 0.541ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.074     1.337    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X75Y101        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/Core_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y101        FDSE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.376 r  d_1_i/rst_adc0/U0/SEQ/Core_reg/Q
                         net (fo=2, routed)           0.027     1.403    d_1_i/rst_adc0/U0/SEQ/MB_out
    SLICE_X75Y101        LUT2 (Prop_D5LUT_SLICEM_I0_O)
                                                      0.037     1.440 r  d_1_i/rst_adc0/U0/SEQ/from_sys_i_1/O
                         net (fo=1, routed)           0.009     1.449    d_1_i/rst_adc0/U0/SEQ/from_sys_i_1_n_0
    SLICE_X75Y101        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.211     1.563    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X75Y101        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/C
                         clock pessimism             -0.221     1.343    
    SLICE_X75Y101        FDSE (Hold_DFF2_SLICEM_C_D)
                                                      0.047     1.390    d_1_i/rst_adc0/U0/SEQ/from_sys_reg
  -------------------------------------------------------------------
                         required time                         -1.390    
                         arrival time                           1.449    
  -------------------------------------------------------------------
                         slack                                  0.059    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         RFADC0_CLK
Waveform(ns):       { 0.000 1.953 }
Period(ns):         3.906
Sources:            { d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     HSADC/CLK_ADC      n/a            1.923         3.906       1.983      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
Min Period        n/a     BUFG_GT/I          n/a            1.290         3.906       2.616      BUFG_GT_X1Y3   d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/I
Min Period        n/a     MMCME4_ADV/CLKIN1  n/a            1.071         3.906       2.835      MMCM_X0Y1      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Min Period        n/a     SRL16E/CLK         n/a            1.064         3.906       2.842      SLICE_X75Y103  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X75Y105  d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X75Y104  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X75Y104  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[2].asr_lpf_reg[2]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X75Y104  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[3].asr_lpf_reg[3]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X75Y104  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X75Y104  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[2].exr_lpf_reg[2]/C
Max Period        n/a     MMCME4_ADV/CLKIN1  n/a            100.000       3.906       96.094     MMCM_X0Y1      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    MMCME4_ADV/CLKIN1  n/a            1.367         1.953       0.586      MMCM_X0Y1      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Fast    MMCME4_ADV/CLKIN1  n/a            1.367         1.953       0.586      MMCM_X0Y1      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    HSADC/CLK_ADC      n/a            0.800         1.953       1.153      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
Low Pulse Width   Fast    HSADC/CLK_ADC      n/a            0.800         1.953       1.153      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
Low Pulse Width   Slow    SRL16E/CLK         n/a            0.532         1.953       1.421      SLICE_X75Y103  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
Low Pulse Width   Fast    SRL16E/CLK         n/a            0.532         1.953       1.421      SLICE_X75Y103  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X75Y105  d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X75Y105  d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X75Y104  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X75Y104  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C
High Pulse Width  Slow    MMCME4_ADV/CLKIN1  n/a            1.367         1.953       0.586      MMCM_X0Y1      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Fast    MMCME4_ADV/CLKIN1  n/a            1.367         1.953       0.586      MMCM_X0Y1      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Slow    HSADC/CLK_ADC      n/a            0.800         1.953       1.153      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
High Pulse Width  Fast    HSADC/CLK_ADC      n/a            0.800         1.953       1.153      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
High Pulse Width  Slow    SRL16E/CLK         n/a            0.532         1.953       1.421      SLICE_X75Y103  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
High Pulse Width  Fast    SRL16E/CLK         n/a            0.532         1.953       1.421      SLICE_X75Y103  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X75Y105  d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X75Y105  d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X75Y104  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X75Y104  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C



---------------------------------------------------------------------------------------------------
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Setup :            0  Failing Endpoints,  Worst Slack        0.019ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.007ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.030ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.019ns  (required time - arrival time)
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FABRIC_CLK0
                            (rising edge-triggered cell HSADC clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[100]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.594ns  (logic 0.395ns (24.779%)  route 1.199ns (75.221%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.314ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.215ns = ( 7.168 - 1.953 ) 
    Source Clock Delay      (SCD):    5.256ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.621ns (routing 0.878ns, distribution 1.743ns)
  Clock Net Delay (Destination): 2.265ns (routing 0.798ns, distribution 1.467ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.621     5.180    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m0_axis_aclk
    HSADC_X0Y0           HSADC (Prop_HSADC_FABRIC_CLK_INTERNAL_FABRIC_CLK0)
                                                      0.076     5.256 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FABRIC_CLK0
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FABRIC_CLK0_DATA_ADC0[100])
                                                      0.360     5.616 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DATA_ADC0[100]
                         net (fo=2, routed)           1.151     6.767    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/s_axis_tdata[100]
    SLICE_X98Y63         LUT4 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.035     6.802 r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1[100]_i_1/O
                         net (fo=1, routed)           0.048     6.850    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/p_0_in[100]
    SLICE_X98Y63         FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[100]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     4.034    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.664 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.879    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.903 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.265     7.168    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X98Y63         FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[100]/C
                         clock pessimism             -0.273     6.895    
                         clock uncertainty           -0.051     6.844    
    SLICE_X98Y63         FDRE (Setup_AFF_SLICEL_C_D)
                                                      0.025     6.869    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[100]
  -------------------------------------------------------------------
                         required time                          6.869    
                         arrival time                          -6.850    
  -------------------------------------------------------------------
                         slack                                  0.019    

Slack (MET) :             0.022ns  (required time - arrival time)
  Source:                 d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[38]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[38]_psdsp_1/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.586ns  (logic 0.078ns (4.919%)  route 1.508ns (95.081%))
  Logic Levels:           0  
  Clock Path Skew:        -0.319ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.100ns = ( 7.053 - 1.953 ) 
    Source Clock Delay      (SCD):    5.129ns
    Clock Pessimism Removal (CPR):    -0.290ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.570ns (routing 0.878ns, distribution 1.692ns)
  Clock Net Delay (Destination): 2.150ns (routing 0.798ns, distribution 1.352ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.570     5.129    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X107Y61        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[38]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y61        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     5.207 r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[38]/Q
                         net (fo=3, routed)           1.508     6.715    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/s1_axis_tdata[38]_alias
    SLICE_X88Y178        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[38]_psdsp_1/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     4.034    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.664 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.879    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.903 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.150     7.053    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X88Y178        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[38]_psdsp_1/C
                         clock pessimism             -0.290     6.763    
                         clock uncertainty           -0.051     6.712    
    SLICE_X88Y178        FDRE (Setup_FFF2_SLICEL_C_D)
                                                      0.025     6.737    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[38]_psdsp_1
  -------------------------------------------------------------------
                         required time                          6.737    
                         arrival time                          -6.715    
  -------------------------------------------------------------------
                         slack                                  0.022    

Slack (MET) :             0.023ns  (required time - arrival time)
  Source:                 d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[108]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[108]_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.620ns  (logic 0.079ns (4.878%)  route 1.541ns (95.122%))
  Logic Levels:           0  
  Clock Path Skew:        -0.284ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.125ns = ( 7.078 - 1.953 ) 
    Source Clock Delay      (SCD):    5.102ns
    Clock Pessimism Removal (CPR):    -0.307ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.543ns (routing 0.878ns, distribution 1.665ns)
  Clock Net Delay (Destination): 2.175ns (routing 0.798ns, distribution 1.377ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.543     5.102    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X108Y73        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[108]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y73        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     5.181 r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[108]/Q
                         net (fo=3, routed)           1.541     6.722    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/s1_axis_tdata[108]_alias
    SLICE_X98Y209        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[108]_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     4.034    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.664 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.879    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.903 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.175     7.078    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X98Y209        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[108]_psdsp/C
                         clock pessimism             -0.307     6.771    
                         clock uncertainty           -0.051     6.720    
    SLICE_X98Y209        FDRE (Setup_BFF_SLICEL_C_D)
                                                      0.025     6.745    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[108]_psdsp
  -------------------------------------------------------------------
                         required time                          6.745    
                         arrival time                          -6.722    
  -------------------------------------------------------------------
                         slack                                  0.023    

Slack (MET) :             0.023ns  (required time - arrival time)
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FABRIC_CLK0
                            (rising edge-triggered cell HSADC clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[106]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.550ns  (logic 0.434ns (28.004%)  route 1.116ns (71.996%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.354ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.175ns = ( 7.128 - 1.953 ) 
    Source Clock Delay      (SCD):    5.256ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.621ns (routing 0.878ns, distribution 1.743ns)
  Clock Net Delay (Destination): 2.225ns (routing 0.798ns, distribution 1.427ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.621     5.180    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m0_axis_aclk
    HSADC_X0Y0           HSADC (Prop_HSADC_FABRIC_CLK_INTERNAL_FABRIC_CLK0)
                                                      0.076     5.256 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FABRIC_CLK0
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FABRIC_CLK0_DATA_ADC0[106])
                                                      0.384     5.640 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DATA_ADC0[106]
                         net (fo=2, routed)           1.068     6.708    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/s_axis_tdata[106]
    SLICE_X101Y64        LUT4 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.050     6.758 r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1[106]_i_1/O
                         net (fo=1, routed)           0.048     6.806    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/p_0_in[106]
    SLICE_X101Y64        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[106]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     4.034    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.664 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.879    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.903 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.225     7.128    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X101Y64        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[106]/C
                         clock pessimism             -0.273     6.855    
                         clock uncertainty           -0.051     6.803    
    SLICE_X101Y64        FDRE (Setup_AFF_SLICEL_C_D)
                                                      0.025     6.828    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[106]
  -------------------------------------------------------------------
                         required time                          6.828    
                         arrival time                          -6.806    
  -------------------------------------------------------------------
                         slack                                  0.023    

Slack (MET) :             0.024ns  (required time - arrival time)
  Source:                 d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[14]_psdsp_1/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.678ns  (logic 0.079ns (4.708%)  route 1.599ns (95.292%))
  Logic Levels:           0  
  Clock Path Skew:        -0.225ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.187ns = ( 7.140 - 1.953 ) 
    Source Clock Delay      (SCD):    5.105ns
    Clock Pessimism Removal (CPR):    -0.307ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.546ns (routing 0.878ns, distribution 1.668ns)
  Clock Net Delay (Destination): 2.237ns (routing 0.798ns, distribution 1.439ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.546     5.105    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X108Y41        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y41        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     5.184 r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[14]/Q
                         net (fo=3, routed)           1.599     6.783    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/s1_axis_tdata[14]_alias
    SLICE_X102Y181       FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[14]_psdsp_1/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     4.034    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.664 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.879    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.903 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.237     7.140    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X102Y181       FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[14]_psdsp_1/C
                         clock pessimism             -0.307     6.833    
                         clock uncertainty           -0.051     6.782    
    SLICE_X102Y181       FDRE (Setup_AFF_SLICEL_C_D)
                                                      0.025     6.807    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[14]_psdsp_1
  -------------------------------------------------------------------
                         required time                          6.807    
                         arrival time                          -6.783    
  -------------------------------------------------------------------
                         slack                                  0.024    

Slack (MET) :             0.027ns  (required time - arrival time)
  Source:                 d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[127]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[127]_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.622ns  (logic 0.079ns (4.870%)  route 1.543ns (95.130%))
  Logic Levels:           0  
  Clock Path Skew:        -0.277ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.090ns = ( 7.043 - 1.953 ) 
    Source Clock Delay      (SCD):    5.077ns
    Clock Pessimism Removal (CPR):    -0.290ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.518ns (routing 0.878ns, distribution 1.640ns)
  Clock Net Delay (Destination): 2.140ns (routing 0.798ns, distribution 1.342ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.518     5.077    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X106Y64        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[127]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y64        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     5.156 r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[127]/Q
                         net (fo=3, routed)           1.543     6.699    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/s1_axis_tdata[127]_alias
    SLICE_X86Y179        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[127]_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     4.034    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.664 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.879    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.903 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.140     7.043    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X86Y179        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[127]_psdsp/C
                         clock pessimism             -0.290     6.753    
                         clock uncertainty           -0.051     6.701    
    SLICE_X86Y179        FDRE (Setup_AFF_SLICEM_C_D)
                                                      0.025     6.726    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[127]_psdsp
  -------------------------------------------------------------------
                         required time                          6.726    
                         arrival time                          -6.699    
  -------------------------------------------------------------------
                         slack                                  0.027    

Slack (MET) :             0.027ns  (required time - arrival time)
  Source:                 d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/GEN[3].data_writer_i/fifo_i/rd_ptr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/GEN[3].bram_dp_i/RAM_reg_bram_0/DINADIN[0]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.610ns  (logic 0.242ns (15.029%)  route 1.368ns (84.971%))
  Logic Levels:           1  (RAMD32=1)
  Clock Path Skew:        0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.229ns = ( 7.182 - 1.953 ) 
    Source Clock Delay      (SCD):    4.985ns
    Clock Pessimism Removal (CPR):    -0.217ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.426ns (routing 0.878ns, distribution 1.548ns)
  Clock Net Delay (Destination): 2.279ns (routing 0.798ns, distribution 1.481ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.426     4.985    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/GEN[3].data_writer_i/fifo_i/s00_axis_aclk
    SLICE_X85Y113        FDRE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/GEN[3].data_writer_i/fifo_i/rd_ptr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y113        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     5.064 r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/GEN[3].data_writer_i/fifo_i/rd_ptr_reg[0]/Q
                         net (fo=40, routed)          0.385     5.449    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/GEN[3].data_writer_i/fifo_i/regs_reg_0_3_0_13/ADDRA0
    SLICE_X89Y115        RAMD32 (Prop_A5LUT_SLICEM_RADR0_O)
                                                      0.163     5.612 r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/GEN[3].data_writer_i/fifo_i/regs_reg_0_3_0_13/RAMA/O
                         net (fo=1, routed)           0.983     6.595    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/GEN[3].bram_dp_i/DINADIN[0]
    RAMB36_X10Y12        RAMB36E2                                     r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/GEN[3].bram_dp_i/RAM_reg_bram_0/DINADIN[0]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     4.034    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.664 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.879    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.903 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.279     7.182    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/GEN[3].bram_dp_i/s00_axis_aclk
    RAMB36_X10Y12        RAMB36E2                                     r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/GEN[3].bram_dp_i/RAM_reg_bram_0/CLKARDCLK
                         clock pessimism             -0.217     6.965    
                         clock uncertainty           -0.051     6.914    
    RAMB36_X10Y12        RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[0])
                                                     -0.291     6.623    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/GEN[3].bram_dp_i/RAM_reg_bram_0
  -------------------------------------------------------------------
                         required time                          6.623    
                         arrival time                          -6.595    
  -------------------------------------------------------------------
                         slack                                  0.027    

Slack (MET) :             0.029ns  (required time - arrival time)
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FABRIC_CLK0
                            (rising edge-triggered cell HSADC clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[34]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.571ns  (logic 0.403ns (25.648%)  route 1.168ns (74.352%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.327ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.202ns = ( 7.155 - 1.953 ) 
    Source Clock Delay      (SCD):    5.256ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.621ns (routing 0.878ns, distribution 1.743ns)
  Clock Net Delay (Destination): 2.252ns (routing 0.798ns, distribution 1.454ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.621     5.180    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m0_axis_aclk
    HSADC_X0Y0           HSADC (Prop_HSADC_FABRIC_CLK_INTERNAL_FABRIC_CLK0)
                                                      0.076     5.256 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FABRIC_CLK0
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FABRIC_CLK0_DATA_ADC0[34])
                                                      0.367     5.623 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DATA_ADC0[34]
                         net (fo=2, routed)           1.119     6.742    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/s_axis_tdata[34]
    SLICE_X106Y61        LUT4 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.036     6.778 r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1[34]_i_1/O
                         net (fo=1, routed)           0.049     6.827    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/p_0_in[34]
    SLICE_X106Y61        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[34]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     4.034    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.664 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.879    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.903 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.252     7.155    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X106Y61        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[34]/C
                         clock pessimism             -0.273     6.882    
                         clock uncertainty           -0.051     6.831    
    SLICE_X106Y61        FDRE (Setup_BFF_SLICEL_C_D)
                                                      0.025     6.856    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[34]
  -------------------------------------------------------------------
                         required time                          6.856    
                         arrival time                          -6.827    
  -------------------------------------------------------------------
                         slack                                  0.029    

Slack (MET) :             0.029ns  (required time - arrival time)
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FABRIC_CLK0
                            (rising edge-triggered cell HSADC clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[47]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.572ns  (logic 0.422ns (26.850%)  route 1.150ns (73.150%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.326ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.203ns = ( 7.156 - 1.953 ) 
    Source Clock Delay      (SCD):    5.256ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.621ns (routing 0.878ns, distribution 1.743ns)
  Clock Net Delay (Destination): 2.253ns (routing 0.798ns, distribution 1.455ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.621     5.180    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m0_axis_aclk
    HSADC_X0Y0           HSADC (Prop_HSADC_FABRIC_CLK_INTERNAL_FABRIC_CLK0)
                                                      0.076     5.256 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FABRIC_CLK0
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FABRIC_CLK0_DATA_ADC0[47])
                                                      0.385     5.641 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DATA_ADC0[47]
                         net (fo=2, routed)           1.093     6.734    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/s_axis_tdata[47]
    SLICE_X107Y60        LUT4 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.037     6.771 r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1[47]_i_1/O
                         net (fo=1, routed)           0.057     6.828    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/p_0_in[47]
    SLICE_X107Y60        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[47]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     4.034    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.664 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.879    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.903 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.253     7.156    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X107Y60        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[47]/C
                         clock pessimism             -0.273     6.883    
                         clock uncertainty           -0.051     6.832    
    SLICE_X107Y60        FDRE (Setup_GFF2_SLICEM_C_D)
                                                      0.025     6.857    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[47]
  -------------------------------------------------------------------
                         required time                          6.857    
                         arrival time                          -6.828    
  -------------------------------------------------------------------
                         slack                                  0.029    

Slack (MET) :             0.030ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_tvalid_r_reg_replica_12/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/ENARDEN
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.481ns  (logic 0.078ns (5.265%)  route 1.403ns (94.735%))
  Logic Levels:           0  
  Clock Path Skew:        -0.048ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.141ns = ( 7.094 - 1.953 ) 
    Source Clock Delay      (SCD):    4.972ns
    Clock Pessimism Removal (CPR):    -0.217ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.413ns (routing 0.878ns, distribution 1.535ns)
  Clock Net Delay (Destination): 2.191ns (routing 0.798ns, distribution 1.393ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.413     4.972    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X89Y84         FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_tvalid_r_reg_replica_12/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y84         FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     5.050 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_tvalid_r_reg_replica_12/Q
                         net (fo=121, routed)         1.403     6.454    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/dds_tvalid_r_repN_12_alias
    RAMB36_X8Y12         RAMB36E2                                     r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/ENARDEN
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     4.034    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.664 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.879    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.903 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.191     7.094    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/aclk
    RAMB36_X8Y12         RAMB36E2                                     r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/CLKARDCLK
                         clock pessimism             -0.217     6.877    
                         clock uncertainty           -0.051     6.826    
    RAMB36_X8Y12         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ENARDEN)
                                                     -0.342     6.484    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0
  -------------------------------------------------------------------
                         required time                          6.484    
                         arrival time                          -6.454    
  -------------------------------------------------------------------
                         slack                                  0.030    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.007ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[15].g_symmetric.g_data_sym_array.g_data_sym[14].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[15].g_symmetric.g_data_sym_array.g_data_sym[8].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.130ns  (logic 0.058ns (44.615%)  route 0.072ns (55.385%))
  Logic Levels:           0  
  Clock Path Skew:        0.091ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.073ns
    Source Clock Delay      (SCD):    5.152ns
    Clock Pessimism Removal (CPR):    -0.170ns
  Clock Net Delay (Source):      2.202ns (routing 0.798ns, distribution 1.404ns)
  Clock Net Delay (Destination): 2.514ns (routing 0.878ns, distribution 1.636ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.202     5.152    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[15].g_symmetric.g_data_sym_array.g_data_sym[14].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X97Y230        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[15].g_symmetric.g_data_sym_array.g_data_sym[14].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y230        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     5.210 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[15].g_symmetric.g_data_sym_array.g_data_sym[14].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.072     5.282    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[15].g_symmetric.g_data_sym_array.g_data_sym[8].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X97Y231        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[15].g_symmetric.g_data_sym_array.g_data_sym[8].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.514     5.073    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[15].g_symmetric.g_data_sym_array.g_data_sym[8].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X97Y231        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[15].g_symmetric.g_data_sym_array.g_data_sym[8].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism              0.170     5.243    
    SLICE_X97Y231        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     5.275    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[15].g_symmetric.g_data_sym_array.g_data_sym[8].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -5.275    
                         arrival time                           5.282    
  -------------------------------------------------------------------
                         slack                                  0.007    

Slack (MET) :             0.007ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[9].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.130ns  (logic 0.058ns (44.615%)  route 0.072ns (55.385%))
  Logic Levels:           0  
  Clock Path Skew:        0.091ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.072ns
    Source Clock Delay      (SCD):    5.151ns
    Clock Pessimism Removal (CPR):    -0.170ns
  Clock Net Delay (Source):      2.201ns (routing 0.798ns, distribution 1.403ns)
  Clock Net Delay (Destination): 2.513ns (routing 0.878ns, distribution 1.635ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.201     5.151    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X97Y228        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y228        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     5.209 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.072     5.281    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[9].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X97Y229        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[9].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.513     5.072    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[9].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X97Y229        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[9].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism              0.170     5.242    
    SLICE_X97Y229        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     5.274    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[9].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -5.274    
                         arrival time                           5.281    
  -------------------------------------------------------------------
                         slack                                  0.007    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[4].g_symmetric.g_data_sym_array.g_data_sym[17].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[4].g_symmetric.g_data_sym_array.g_data_sym[11].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.321ns  (logic 0.058ns (18.069%)  route 0.263ns (81.932%))
  Logic Levels:           0  
  Clock Path Skew:        0.279ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.045ns
    Source Clock Delay      (SCD):    5.077ns
    Clock Pessimism Removal (CPR):    -0.311ns
  Clock Net Delay (Source):      2.127ns (routing 0.798ns, distribution 1.329ns)
  Clock Net Delay (Destination): 2.486ns (routing 0.878ns, distribution 1.608ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.127     5.077    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[4].g_symmetric.g_data_sym_array.g_data_sym[17].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X89Y234        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[4].g_symmetric.g_data_sym_array.g_data_sym[17].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y234        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     5.135 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[4].g_symmetric.g_data_sym_array.g_data_sym[17].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.263     5.398    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[4].g_symmetric.g_data_sym_array.g_data_sym[11].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X89Y251        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[4].g_symmetric.g_data_sym_array.g_data_sym[11].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.486     5.045    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[4].g_symmetric.g_data_sym_array.g_data_sym[11].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X89Y251        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[4].g_symmetric.g_data_sym_array.g_data_sym[11].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism              0.311     5.356    
    SLICE_X89Y251        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     5.388    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[4].g_symmetric.g_data_sym_array.g_data_sym[11].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -5.388    
                         arrival time                           5.398    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[34].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[42].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.241ns  (logic 0.058ns (24.034%)  route 0.183ns (75.966%))
  Logic Levels:           0  
  Clock Path Skew:        0.169ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.020ns
    Source Clock Delay      (SCD):    5.124ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Net Delay (Source):      2.174ns (routing 0.798ns, distribution 1.376ns)
  Clock Net Delay (Destination): 2.461ns (routing 0.878ns, distribution 1.583ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.174     5.124    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[34].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X94Y61         FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[34].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y61         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     5.182 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[34].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[2]/Q
                         net (fo=2, routed)           0.183     5.365    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[42].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[2]_0
    SLICE_X95Y46         FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[42].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.461     5.020    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[42].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X95Y46         FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[42].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[2]/C
                         clock pessimism              0.273     5.293    
    SLICE_X95Y46         FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.062     5.355    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[42].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         -5.355    
                         arrival time                           5.365    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[45].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[6]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.211ns  (logic 0.058ns (27.488%)  route 0.153ns (72.512%))
  Logic Levels:           0  
  Clock Path Skew:        0.181ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.104ns
    Source Clock Delay      (SCD):    5.196ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Net Delay (Source):      2.246ns (routing 0.798ns, distribution 1.448ns)
  Clock Net Delay (Destination): 2.545ns (routing 0.878ns, distribution 1.667ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.246     5.196    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[45].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X103Y59        FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[45].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y59        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.058     5.254 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[45].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][6]/Q
                         net (fo=1, routed)           0.153     5.407    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[6]
    SLICE_X103Y64        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[6]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.545     5.104    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X103Y64        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[6]_srl6/CLK
                         clock pessimism              0.273     5.377    
    SLICE_X103Y64        SRL16E (Hold_G6LUT_SLICEM_CLK_D)
                                                      0.020     5.397    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[6]_srl6
  -------------------------------------------------------------------
                         required time                         -5.397    
                         arrival time                           5.407    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][133]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[8].g_symmetric.g_data_array.g_data[3].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.364ns  (logic 0.057ns (15.641%)  route 0.307ns (84.359%))
  Logic Levels:           0  
  Clock Path Skew:        0.294ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.059ns
    Source Clock Delay      (SCD):    5.076ns
    Clock Pessimism Removal (CPR):    -0.311ns
  Clock Net Delay (Source):      2.126ns (routing 0.798ns, distribution 1.328ns)
  Clock Net Delay (Destination): 2.500ns (routing 0.878ns, distribution 1.622ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.126     5.076    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/aclk
    SLICE_X96Y219        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][133]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y219        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     5.133 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][133]/Q
                         net (fo=2, routed)           0.307     5.440    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[8].g_symmetric.g_data_array.g_data[3].g_data_buff.i_data_buf/g_buff.i_buff/data_in[5]
    SLICE_X99Y242        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[8].g_symmetric.g_data_array.g_data[3].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.500     5.059    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[8].g_symmetric.g_data_array.g_data[3].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X99Y242        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[8].g_symmetric.g_data_array.g_data[3].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[5]/C
                         clock pessimism              0.311     5.370    
    SLICE_X99Y242        FDRE (Hold_AFF_SLICEM_C_D)
                                                      0.060     5.430    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[8].g_symmetric.g_data_array.g_data[3].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[5]
  -------------------------------------------------------------------
                         required time                         -5.430    
                         arrival time                           5.440    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_array.g_data[55].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[4]_srl2/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.137ns  (logic 0.058ns (42.336%)  route 0.079ns (57.664%))
  Logic Levels:           0  
  Clock Path Skew:        0.101ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.869ns
    Source Clock Delay      (SCD):    4.995ns
    Clock Pessimism Removal (CPR):    -0.227ns
  Clock Net Delay (Source):      2.045ns (routing 0.798ns, distribution 1.247ns)
  Clock Net Delay (Destination): 2.310ns (routing 0.878ns, distribution 1.432ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.045     4.995    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_array.g_data[55].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X76Y103        FDRE                                         r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_array.g_data[55].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y103        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     5.053 r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_array.g_data[55].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[4]/Q
                         net (fo=1, routed)           0.079     5.132    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[4]_0
    SLICE_X78Y103        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[4]_srl2/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.310     4.869    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X78Y103        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[4]_srl2/CLK
                         clock pessimism              0.227     5.096    
    SLICE_X78Y103        SRL16E (Hold_E6LUT_SLICEM_CLK_D)
                                                      0.026     5.122    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[4]_srl2
  -------------------------------------------------------------------
                         required time                         -5.122    
                         arrival time                           5.132    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_array.g_data[41].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_array.g_data[49].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[8][13]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.219ns  (logic 0.061ns (27.793%)  route 0.158ns (72.207%))
  Logic Levels:           0  
  Clock Path Skew:        0.153ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.014ns
    Source Clock Delay      (SCD):    5.085ns
    Clock Pessimism Removal (CPR):    -0.224ns
  Clock Net Delay (Source):      2.135ns (routing 0.798ns, distribution 1.337ns)
  Clock Net Delay (Destination): 2.455ns (routing 0.878ns, distribution 1.577ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.135     5.085    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_array.g_data[41].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X88Y157        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_array.g_data[41].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y157        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     5.146 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_array.g_data[41].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[13]/Q
                         net (fo=2, routed)           0.158     5.305    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_array.g_data[49].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[9][13]_0
    SLICE_X90Y155        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_array.g_data[49].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[8][13]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.455     5.014    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_array.g_data[49].i_data_casc_dly/aclk
    SLICE_X90Y155        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_array.g_data[49].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[8][13]_srl9/CLK
                         clock pessimism              0.224     5.238    
    SLICE_X90Y155        SRL16E (Hold_F5LUT_SLICEM_CLK_D)
                                                      0.056     5.294    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_array.g_data[49].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[8][13]_srl9
  -------------------------------------------------------------------
                         required time                         -5.294    
                         arrival time                           5.305    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[47].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[55].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[2][10]_srl3/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.236ns  (logic 0.059ns (24.992%)  route 0.177ns (75.008%))
  Logic Levels:           0  
  Clock Path Skew:        0.170ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.198ns
    Source Clock Delay      (SCD):    5.234ns
    Clock Pessimism Removal (CPR):    -0.206ns
  Clock Net Delay (Source):      2.284ns (routing 0.798ns, distribution 1.486ns)
  Clock Net Delay (Destination): 2.639ns (routing 0.878ns, distribution 1.761ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.284     5.234    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[47].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X111Y29        FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[47].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y29        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     5.293 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[47].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[10]/Q
                         net (fo=2, routed)           0.177     5.470    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[55].i_data_casc_dly/g_parallel.g_paths[1].data_casc[48]_191[10]
    SLICE_X112Y13        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[55].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[2][10]_srl3/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.639     5.198    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[55].i_data_casc_dly/aclk
    SLICE_X112Y13        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[55].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[2][10]_srl3/CLK
                         clock pessimism              0.206     5.404    
    SLICE_X112Y13        SRL16E (Hold_C5LUT_SLICEM_CLK_D)
                                                      0.055     5.459    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[55].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[2][10]_srl3
  -------------------------------------------------------------------
                         required time                         -5.459    
                         arrival time                           5.470    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[47].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[55].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[2][9]_srl3/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.236ns  (logic 0.060ns (25.416%)  route 0.176ns (74.584%))
  Logic Levels:           0  
  Clock Path Skew:        0.170ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.198ns
    Source Clock Delay      (SCD):    5.234ns
    Clock Pessimism Removal (CPR):    -0.206ns
  Clock Net Delay (Source):      2.284ns (routing 0.798ns, distribution 1.486ns)
  Clock Net Delay (Destination): 2.639ns (routing 0.878ns, distribution 1.761ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.284     5.234    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[47].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X111Y29        FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[47].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y29        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.060     5.294 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[47].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[9]/Q
                         net (fo=2, routed)           0.176     5.470    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[55].i_data_casc_dly/g_parallel.g_paths[1].data_casc[48]_191[9]
    SLICE_X112Y13        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[55].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[2][9]_srl3/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.639     5.198    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[55].i_data_casc_dly/aclk
    SLICE_X112Y13        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[55].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[2][9]_srl3/CLK
                         clock pessimism              0.206     5.404    
    SLICE_X112Y13        SRL16E (Hold_B5LUT_SLICEM_CLK_D)
                                                      0.055     5.459    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[55].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[2][9]_srl3
  -------------------------------------------------------------------
                         required time                         -5.459    
                         arrival time                           5.470    
  -------------------------------------------------------------------
                         slack                                  0.011    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out1_d_1_clk_adc0_x2_0
Waveform(ns):       { 0.000 0.976 }
Period(ns):         1.953
Sources:            { d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     HSADC/FABRIC_CLK    n/a            1.923         1.953       0.030      HSADC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
Min Period        n/a     HSADC/FABRIC_CLK    n/a            1.923         1.953       0.030      HSADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X2Y24  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X2Y25  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X3Y26  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X3Y27  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_11/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X3Y28  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_12/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X3Y29  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_13/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X3Y30  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_14/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X3Y31  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_15/CLKARDCLK
Low Pulse Width   Slow    HSADC/FABRIC_CLK    n/a            0.800         0.977       0.177      HSADC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
Low Pulse Width   Fast    HSADC/FABRIC_CLK    n/a            0.800         0.976       0.176      HSADC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
Low Pulse Width   Slow    HSADC/FABRIC_CLK    n/a            0.800         0.976       0.176      HSADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
Low Pulse Width   Fast    HSADC/FABRIC_CLK    n/a            0.800         0.976       0.176      HSADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.977       0.435      RAMB36_X2Y24  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X2Y24  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X2Y25  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X2Y25  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X3Y26  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.977       0.435      RAMB36_X3Y26  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
High Pulse Width  Slow    HSADC/FABRIC_CLK    n/a            0.800         0.976       0.176      HSADC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
High Pulse Width  Fast    HSADC/FABRIC_CLK    n/a            0.800         0.977       0.177      HSADC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
High Pulse Width  Slow    HSADC/FABRIC_CLK    n/a            0.800         0.977       0.177      HSADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
High Pulse Width  Fast    HSADC/FABRIC_CLK    n/a            0.800         0.976       0.176      HSADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X2Y24  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X2Y24  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.977       0.435      RAMB36_X2Y25  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X2Y25  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.977       0.435      RAMB36_X3Y26  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X3Y26  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK



---------------------------------------------------------------------------------------------------
From Clock:  RFDAC0_CLK
  To Clock:  RFDAC0_CLK

Setup :            0  Failing Endpoints,  Worst Slack        0.034ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.010ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.502ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.034ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r6_reg_r/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/mem_addr_int_r_reg[0]_replica_2/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.480ns  (logic 0.171ns (6.896%)  route 2.309ns (93.104%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.080ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.429ns = ( 6.033 - 2.604 ) 
    Source Clock Delay      (SCD):    3.794ns
    Clock Pessimism Removal (CPR):    0.285ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.121ns (routing 1.381ns, distribution 1.740ns)
  Clock Net Delay (Destination): 2.908ns (routing 1.256ns, distribution 1.652ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.121     3.794    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X101Y254       FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r6_reg_r/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y254       FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     3.875 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r6_reg_r/Q
                         net (fo=34, routed)          0.680     4.555    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r6_reg_r_n_0
    SLICE_X115Y229       LUT2 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.090     4.645 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/addr_cnt_r6_reg_gate__10/O
                         net (fo=10, routed)          1.629     6.274    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i_n_15
    SLICE_X116Y393       FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/mem_addr_int_r_reg[0]_replica_2/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.908     6.033    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X116Y393       FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/mem_addr_int_r_reg[0]_replica_2/C
                         clock pessimism              0.285     6.318    
                         clock uncertainty           -0.035     6.282    
    SLICE_X116Y393       FDRE (Setup_EFF_SLICEL_C_D)
                                                      0.025     6.307    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/mem_addr_int_r_reg[0]_replica_2
  -------------------------------------------------------------------
                         required time                          6.307    
                         arrival time                          -6.274    
  -------------------------------------------------------------------
                         slack                                  0.034    

Slack (MET) :             0.036ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[5].phase_v0_r2_reg[5][22]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.246ns  (logic 0.400ns (17.809%)  route 1.846ns (82.191%))
  Logic Levels:           3  (CARRY8=3)
  Clock Path Skew:        -0.224ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.205ns = ( 5.809 - 2.604 ) 
    Source Clock Delay      (SCD):    3.706ns
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.033ns (routing 1.381ns, distribution 1.652ns)
  Clock Net Delay (Destination): 2.684ns (routing 1.256ns, distribution 1.428ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.033     3.706    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X102Y228       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y228       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.785 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[1]/Q
                         net (fo=34, routed)          1.096     4.881    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N[5]
    SLICE_X81Y276        CARRY8 (Prop_CARRY8_SLICEL_S[0]_CO[7])
                                                      0.190     5.071 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[5]_carry/CO[7]
                         net (fo=1, routed)           0.026     5.097    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[5]_carry_n_0
    SLICE_X81Y277        CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7])
                                                      0.015     5.112 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[5]_carry__0/CO[7]
                         net (fo=1, routed)           0.026     5.138    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[5]_carry__0_n_0
    SLICE_X81Y278        CARRY8 (Prop_CARRY8_SLICEL_CI_O[5])
                                                      0.116     5.254 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[5]_carry__1/O[5]
                         net (fo=1, routed)           0.698     5.952    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[5]_84[22]
    SLICE_X79Y278        SRL16E                                       r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[5].phase_v0_r2_reg[5][22]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.684     5.809    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X79Y278        SRL16E                                       r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[5].phase_v0_r2_reg[5][22]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/CLK
                         clock pessimism              0.277     6.086    
                         clock uncertainty           -0.035     6.051    
    SLICE_X79Y278        SRL16E (Setup_E6LUT_SLICEM_CLK_D)
                                                     -0.063     5.988    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[5].phase_v0_r2_reg[5][22]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r
  -------------------------------------------------------------------
                         required time                          5.988    
                         arrival time                          -5.952    
  -------------------------------------------------------------------
                         slack                                  0.036    

Slack (MET) :             0.037ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[5].phase_v1_r1_reg[5][31]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.287ns  (logic 0.512ns (22.383%)  route 1.775ns (77.617%))
  Logic Levels:           3  (CARRY8=2 LUT2=1)
  Clock Path Skew:        -0.270ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.134ns = ( 5.738 - 2.604 ) 
    Source Clock Delay      (SCD):    3.680ns
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.007ns (routing 1.381ns, distribution 1.626ns)
  Clock Net Delay (Destination): 2.613ns (routing 1.256ns, distribution 1.357ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.007     3.680    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X95Y172        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y172        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.759 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[16]/Q
                         net (fo=16, routed)          1.710     5.470    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1[16]
    SLICE_X78Y279        LUT2 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.125     5.595 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[5]_carry__1_i_8/O
                         net (fo=1, routed)           0.013     5.608    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[5]_carry__1_i_8_n_0
    SLICE_X78Y279        CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[7])
                                                      0.192     5.800 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[5]_carry__1/CO[7]
                         net (fo=1, routed)           0.026     5.826    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[5]_carry__1_n_0
    SLICE_X78Y280        CARRY8 (Prop_CARRY8_SLICEM_CI_O[7])
                                                      0.116     5.942 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[5]_carry__2/O[7]
                         net (fo=1, routed)           0.026     5.968    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[5]_72[31]
    SLICE_X78Y280        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[5].phase_v1_r1_reg[5][31]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.613     5.738    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X78Y280        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[5].phase_v1_r1_reg[5][31]/C
                         clock pessimism              0.277     6.015    
                         clock uncertainty           -0.035     5.979    
    SLICE_X78Y280        FDRE (Setup_HFF_SLICEM_C_D)
                                                      0.025     6.004    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[5].phase_v1_r1_reg[5][31]
  -------------------------------------------------------------------
                         required time                          6.004    
                         arrival time                          -5.968    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.038ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[5].phase_v1_r1_reg[5][29]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.286ns  (logic 0.512ns (22.392%)  route 1.774ns (77.608%))
  Logic Levels:           3  (CARRY8=2 LUT2=1)
  Clock Path Skew:        -0.270ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.134ns = ( 5.738 - 2.604 ) 
    Source Clock Delay      (SCD):    3.680ns
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.007ns (routing 1.381ns, distribution 1.626ns)
  Clock Net Delay (Destination): 2.613ns (routing 1.256ns, distribution 1.357ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.007     3.680    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X95Y172        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y172        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.759 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[16]/Q
                         net (fo=16, routed)          1.710     5.470    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1[16]
    SLICE_X78Y279        LUT2 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.125     5.595 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[5]_carry__1_i_8/O
                         net (fo=1, routed)           0.013     5.608    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[5]_carry__1_i_8_n_0
    SLICE_X78Y279        CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[7])
                                                      0.192     5.800 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[5]_carry__1/CO[7]
                         net (fo=1, routed)           0.026     5.826    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[5]_carry__1_n_0
    SLICE_X78Y280        CARRY8 (Prop_CARRY8_SLICEM_CI_O[5])
                                                      0.116     5.942 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[5]_carry__2/O[5]
                         net (fo=1, routed)           0.025     5.967    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[5]_72[29]
    SLICE_X78Y280        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[5].phase_v1_r1_reg[5][29]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.613     5.738    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X78Y280        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[5].phase_v1_r1_reg[5][29]/C
                         clock pessimism              0.277     6.015    
                         clock uncertainty           -0.035     5.979    
    SLICE_X78Y280        FDRE (Setup_FFF_SLICEM_C_D)
                                                      0.025     6.004    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[5].phase_v1_r1_reg[5][29]
  -------------------------------------------------------------------
                         required time                          6.004    
                         arrival time                          -5.967    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.038ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[19]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.464ns  (logic 0.944ns (38.309%)  route 1.520ns (61.691%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.081ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.212ns = ( 5.816 - 2.604 ) 
    Source Clock Delay      (SCD):    3.574ns
    Clock Pessimism Removal (CPR):    0.281ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.901ns (routing 1.381ns, distribution 1.520ns)
  Clock Net Delay (Destination): 2.691ns (routing 1.256ns, distribution 1.435ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.901     3.574    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X13Y90       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X13Y90       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[19])
                                                      0.212     3.786 f  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[19]
                         net (fo=29, routed)          1.520     5.306    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[1]
    DSP48E2_X15Y57       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[1]_A_ALU[1])
                                                      0.194     5.500 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[1]
                         net (fo=1, routed)           0.000     5.500    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<1>
    DSP48E2_X15Y57       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[1]_ALU_OUT[19])
                                                      0.538     6.038 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[19]
                         net (fo=1, routed)           0.000     6.038    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<19>
    DSP48E2_X15Y57       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[19]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.691     5.816    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X15Y57       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.281     6.097    
                         clock uncertainty           -0.035     6.061    
    DSP48E2_X15Y57       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[19])
                                                      0.015     6.076    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          6.076    
                         arrival time                          -6.038    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.038ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[20]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.464ns  (logic 0.944ns (38.309%)  route 1.520ns (61.691%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.081ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.212ns = ( 5.816 - 2.604 ) 
    Source Clock Delay      (SCD):    3.574ns
    Clock Pessimism Removal (CPR):    0.281ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.901ns (routing 1.381ns, distribution 1.520ns)
  Clock Net Delay (Destination): 2.691ns (routing 1.256ns, distribution 1.435ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.901     3.574    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X13Y90       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X13Y90       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[19])
                                                      0.212     3.786 f  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[19]
                         net (fo=29, routed)          1.520     5.306    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[1]
    DSP48E2_X15Y57       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[1]_A_ALU[1])
                                                      0.194     5.500 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[1]
                         net (fo=1, routed)           0.000     5.500    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<1>
    DSP48E2_X15Y57       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[1]_ALU_OUT[20])
                                                      0.538     6.038 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[20]
                         net (fo=1, routed)           0.000     6.038    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<20>
    DSP48E2_X15Y57       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[20]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.691     5.816    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X15Y57       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.281     6.097    
                         clock uncertainty           -0.035     6.061    
    DSP48E2_X15Y57       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[20])
                                                      0.015     6.076    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          6.076    
                         arrival time                          -6.038    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.038ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[21]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.464ns  (logic 0.944ns (38.309%)  route 1.520ns (61.691%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.081ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.212ns = ( 5.816 - 2.604 ) 
    Source Clock Delay      (SCD):    3.574ns
    Clock Pessimism Removal (CPR):    0.281ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.901ns (routing 1.381ns, distribution 1.520ns)
  Clock Net Delay (Destination): 2.691ns (routing 1.256ns, distribution 1.435ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.901     3.574    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X13Y90       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X13Y90       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[19])
                                                      0.212     3.786 f  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[19]
                         net (fo=29, routed)          1.520     5.306    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[1]
    DSP48E2_X15Y57       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[1]_A_ALU[1])
                                                      0.194     5.500 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[1]
                         net (fo=1, routed)           0.000     5.500    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<1>
    DSP48E2_X15Y57       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[1]_ALU_OUT[21])
                                                      0.538     6.038 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[21]
                         net (fo=1, routed)           0.000     6.038    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<21>
    DSP48E2_X15Y57       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[21]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.691     5.816    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X15Y57       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.281     6.097    
                         clock uncertainty           -0.035     6.061    
    DSP48E2_X15Y57       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[21])
                                                      0.015     6.076    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          6.076    
                         arrival time                          -6.038    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.038ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[22]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.464ns  (logic 0.944ns (38.309%)  route 1.520ns (61.691%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.081ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.212ns = ( 5.816 - 2.604 ) 
    Source Clock Delay      (SCD):    3.574ns
    Clock Pessimism Removal (CPR):    0.281ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.901ns (routing 1.381ns, distribution 1.520ns)
  Clock Net Delay (Destination): 2.691ns (routing 1.256ns, distribution 1.435ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.901     3.574    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X13Y90       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X13Y90       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[19])
                                                      0.212     3.786 f  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[19]
                         net (fo=29, routed)          1.520     5.306    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[1]
    DSP48E2_X15Y57       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[1]_A_ALU[1])
                                                      0.194     5.500 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[1]
                         net (fo=1, routed)           0.000     5.500    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<1>
    DSP48E2_X15Y57       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[1]_ALU_OUT[22])
                                                      0.538     6.038 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[22]
                         net (fo=1, routed)           0.000     6.038    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<22>
    DSP48E2_X15Y57       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[22]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.691     5.816    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X15Y57       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.281     6.097    
                         clock uncertainty           -0.035     6.061    
    DSP48E2_X15Y57       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[22])
                                                      0.015     6.076    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          6.076    
                         arrival time                          -6.038    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.038ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[23]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.464ns  (logic 0.944ns (38.309%)  route 1.520ns (61.691%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.081ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.212ns = ( 5.816 - 2.604 ) 
    Source Clock Delay      (SCD):    3.574ns
    Clock Pessimism Removal (CPR):    0.281ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.901ns (routing 1.381ns, distribution 1.520ns)
  Clock Net Delay (Destination): 2.691ns (routing 1.256ns, distribution 1.435ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.901     3.574    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X13Y90       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X13Y90       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[19])
                                                      0.212     3.786 f  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[19]
                         net (fo=29, routed)          1.520     5.306    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[1]
    DSP48E2_X15Y57       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[1]_A_ALU[1])
                                                      0.194     5.500 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[1]
                         net (fo=1, routed)           0.000     5.500    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<1>
    DSP48E2_X15Y57       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[1]_ALU_OUT[23])
                                                      0.538     6.038 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[23]
                         net (fo=1, routed)           0.000     6.038    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<23>
    DSP48E2_X15Y57       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[23]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.691     5.816    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X15Y57       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.281     6.097    
                         clock uncertainty           -0.035     6.061    
    DSP48E2_X15Y57       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[23])
                                                      0.015     6.076    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          6.076    
                         arrival time                          -6.038    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.038ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[24]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.464ns  (logic 0.944ns (38.309%)  route 1.520ns (61.691%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.081ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.212ns = ( 5.816 - 2.604 ) 
    Source Clock Delay      (SCD):    3.574ns
    Clock Pessimism Removal (CPR):    0.281ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.901ns (routing 1.381ns, distribution 1.520ns)
  Clock Net Delay (Destination): 2.691ns (routing 1.256ns, distribution 1.435ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.901     3.574    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X13Y90       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X13Y90       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[19])
                                                      0.212     3.786 f  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[19]
                         net (fo=29, routed)          1.520     5.306    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[1]
    DSP48E2_X15Y57       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[1]_A_ALU[1])
                                                      0.194     5.500 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[1]
                         net (fo=1, routed)           0.000     5.500    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<1>
    DSP48E2_X15Y57       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[1]_ALU_OUT[24])
                                                      0.538     6.038 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[24]
                         net (fo=1, routed)           0.000     6.038    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<24>
    DSP48E2_X15Y57       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[24]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.691     5.816    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X15Y57       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.281     6.097    
                         clock uncertainty           -0.035     6.061    
    DSP48E2_X15Y57       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[24])
                                                      0.015     6.076    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          6.076    
                         arrival time                          -6.038    
  -------------------------------------------------------------------
                         slack                                  0.038    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/opt_has_pipe.first_q_reg[27]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.338ns  (logic 0.083ns (24.558%)  route 0.255ns (75.442%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.268ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.823ns
    Source Clock Delay      (SCD):    3.278ns
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Net Delay (Source):      2.757ns (routing 1.256ns, distribution 1.501ns)
  Clock Net Delay (Destination): 3.150ns (routing 1.381ns, distribution 1.769ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.757     3.278    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/aclk
    SLICE_X106Y225       FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/opt_has_pipe.first_q_reg[27]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y225       FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     3.339 r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/opt_has_pipe.first_q_reg[27]/Q
                         net (fo=2, routed)           0.233     3.572    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/opt_has_pipe.first_q[27]
    SLICE_X106Y243       LUT2 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.022     3.594 r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[9]_i_1/O
                         net (fo=1, routed)           0.022     3.616    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/D[9]
    SLICE_X106Y243       FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.150     3.823    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/aclk
    SLICE_X106Y243       FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[9]/C
                         clock pessimism             -0.277     3.546    
    SLICE_X106Y243       FDRE (Hold_GFF_SLICEL_C_D)
                                                      0.060     3.606    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[9]
  -------------------------------------------------------------------
                         required time                         -3.606    
                         arrival time                           3.616    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ls/opt_has_pipe.first_q_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.191ns  (logic 0.058ns (30.366%)  route 0.133ns (69.633%))
  Logic Levels:           0  
  Clock Path Skew:        0.121ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.743ns
    Source Clock Delay      (SCD):    3.301ns
    Clock Pessimism Removal (CPR):    0.321ns
  Clock Net Delay (Source):      2.780ns (routing 1.256ns, distribution 1.524ns)
  Clock Net Delay (Destination): 3.070ns (routing 1.381ns, distribution 1.689ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.780     3.301    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ls/aclk
    SLICE_X86Y422        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ls/opt_has_pipe.first_q_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y422        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.058     3.359 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ls/opt_has_pipe.first_q_reg[1]/Q
                         net (fo=1, routed)           0.133     3.492    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/D[1]
    SLICE_X86Y418        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.070     3.743    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/aclk
    SLICE_X86Y418        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q_reg[1]/C
                         clock pessimism             -0.321     3.422    
    SLICE_X86Y418        FDRE (Hold_EFF_SLICEM_C_D)
                                                      0.060     3.482    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.482    
                         arrival time                           3.492    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[7][134]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_140_153/RAMB/I
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.303ns  (logic 0.059ns (19.472%)  route 0.244ns (80.528%))
  Logic Levels:           0  
  Clock Path Skew:        0.215ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.556ns
    Source Clock Delay      (SCD):    3.060ns
    Clock Pessimism Removal (CPR):    0.281ns
  Clock Net Delay (Source):      2.539ns (routing 1.256ns, distribution 1.283ns)
  Clock Net Delay (Destination): 2.883ns (routing 1.381ns, distribution 1.502ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.539     3.060    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X64Y179        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[7][134]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y179        FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     3.119 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[7][134]/Q
                         net (fo=1, routed)           0.244     3.363    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_140_153/DIB0
    SLICE_X63Y182        RAMD32                                       r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_140_153/RAMB/I
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.883     3.556    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_140_153/WCLK
    SLICE_X63Y182        RAMD32                                       r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_140_153/RAMB/CLK
                         clock pessimism             -0.281     3.275    
    SLICE_X63Y182        RAMD32 (Hold_B5LUT_SLICEM_CLK_I)
                                                      0.078     3.353    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_140_153/RAMB
  -------------------------------------------------------------------
                         required time                         -3.353    
                         arrival time                           3.363    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMA/I
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.246ns  (logic 0.059ns (23.984%)  route 0.187ns (76.016%))
  Logic Levels:           0  
  Clock Path Skew:        0.161ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.824ns
    Source Clock Delay      (SCD):    3.282ns
    Clock Pessimism Removal (CPR):    0.382ns
  Clock Net Delay (Source):      2.761ns (routing 1.256ns, distribution 1.505ns)
  Clock Net Delay (Destination): 3.151ns (routing 1.381ns, distribution 1.770ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.761     3.282    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X102Y177       FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y177       FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.059     3.341 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][0]/Q
                         net (fo=1, routed)           0.187     3.528    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/DIA0
    SLICE_X104Y179       RAMD32                                       r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMA/I
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.151     3.824    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/WCLK
    SLICE_X104Y179       RAMD32                                       r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMA/CLK
                         clock pessimism             -0.382     3.442    
    SLICE_X104Y179       RAMD32 (Hold_A5LUT_SLICEM_CLK_I)
                                                      0.075     3.517    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMA
  -------------------------------------------------------------------
                         required time                         -3.517    
                         arrival time                           3.528    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[3][59]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_56_69/RAMB_D1/I
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.204ns  (logic 0.061ns (29.902%)  route 0.143ns (70.098%))
  Logic Levels:           0  
  Clock Path Skew:        0.133ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.724ns
    Source Clock Delay      (SCD):    3.216ns
    Clock Pessimism Removal (CPR):    0.374ns
  Clock Net Delay (Source):      2.695ns (routing 1.256ns, distribution 1.439ns)
  Clock Net Delay (Destination): 3.051ns (routing 1.381ns, distribution 1.670ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.695     3.216    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X88Y166        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[3][59]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y166        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     3.277 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[3][59]/Q
                         net (fo=1, routed)           0.143     3.420    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_56_69/DIB1
    SLICE_X89Y166        RAMD32                                       r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_56_69/RAMB_D1/I
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.051     3.724    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_56_69/WCLK
    SLICE_X89Y166        RAMD32                                       r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_56_69/RAMB_D1/CLK
                         clock pessimism             -0.374     3.350    
    SLICE_X89Y166        RAMD32 (Hold_B6LUT_SLICEM_CLK_I)
                                                      0.060     3.410    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_56_69/RAMB_D1
  -------------------------------------------------------------------
                         required time                         -3.410    
                         arrival time                           3.420    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.172ns  (logic 0.059ns (34.302%)  route 0.113ns (65.698%))
  Logic Levels:           0  
  Clock Path Skew:        0.132ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.805ns
    Source Clock Delay      (SCD):    3.289ns
    Clock Pessimism Removal (CPR):    0.384ns
  Clock Net Delay (Source):      2.768ns (routing 1.256ns, distribution 1.512ns)
  Clock Net Delay (Destination): 3.132ns (routing 1.381ns, distribution 1.751ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.768     3.289    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/aclk
    SLICE_X101Y268       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y268       FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     3.348 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[0]/Q
                         net (fo=1, routed)           0.113     3.461    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q[0]
    SLICE_X103Y269       SRL16E                                       r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.132     3.805    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/aclk
    SLICE_X103Y269       SRL16E                                       r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2/CLK
                         clock pessimism             -0.384     3.421    
    SLICE_X103Y269       SRL16E (Hold_A6LUT_SLICEM_CLK_D)
                                                      0.029     3.450    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2
  -------------------------------------------------------------------
                         required time                         -3.450    
                         arrival time                           3.461    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][33]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_28_41/RAMC_D1/I
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.241ns  (logic 0.061ns (25.311%)  route 0.180ns (74.689%))
  Logic Levels:           0  
  Clock Path Skew:        0.170ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.824ns
    Source Clock Delay      (SCD):    3.272ns
    Clock Pessimism Removal (CPR):    0.382ns
  Clock Net Delay (Source):      2.751ns (routing 1.256ns, distribution 1.495ns)
  Clock Net Delay (Destination): 3.151ns (routing 1.381ns, distribution 1.770ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.751     3.272    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X101Y176       FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][33]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y176       FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     3.333 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][33]/Q
                         net (fo=1, routed)           0.180     3.513    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_28_41/DIC1
    SLICE_X104Y178       RAMD32                                       r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_28_41/RAMC_D1/I
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.151     3.824    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_28_41/WCLK
    SLICE_X104Y178       RAMD32                                       r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_28_41/RAMC_D1/CLK
                         clock pessimism             -0.382     3.442    
    SLICE_X104Y178       RAMD32 (Hold_C6LUT_SLICEM_CLK_I)
                                                      0.060     3.502    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_28_41/RAMC_D1
  -------------------------------------------------------------------
                         required time                         -3.502    
                         arrival time                           3.513    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v1_r1_reg[11][10]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[834]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.176ns  (logic 0.058ns (32.955%)  route 0.118ns (67.045%))
  Logic Levels:           0  
  Clock Path Skew:        0.105ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.783ns
    Source Clock Delay      (SCD):    3.295ns
    Clock Pessimism Removal (CPR):    0.383ns
  Clock Net Delay (Source):      2.774ns (routing 1.256ns, distribution 1.518ns)
  Clock Net Delay (Destination): 3.110ns (routing 1.381ns, distribution 1.729ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.774     3.295    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X100Y284       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v1_r1_reg[11][10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y284       FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     3.353 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v1_r1_reg[11][10]/Q
                         net (fo=1, routed)           0.118     3.471    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int[834]
    SLICE_X101Y285       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[834]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.110     3.783    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X101Y285       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[834]/C
                         clock pessimism             -0.383     3.400    
    SLICE_X101Y285       FDRE (Hold_BFF_SLICEL_C_D)
                                                      0.060     3.460    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[834]
  -------------------------------------------------------------------
                         required time                         -3.460    
                         arrival time                           3.471    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/dob_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.245ns  (logic 0.060ns (24.490%)  route 0.185ns (75.510%))
  Logic Levels:           0  
  Clock Path Skew:        0.172ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.759ns
    Source Clock Delay      (SCD):    3.306ns
    Clock Pessimism Removal (CPR):    0.281ns
  Clock Net Delay (Source):      2.785ns (routing 1.256ns, distribution 1.529ns)
  Clock Net Delay (Destination): 3.086ns (routing 1.381ns, distribution 1.705ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.785     3.306    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/aclk
    SLICE_X104Y179       FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/dob_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y179       FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.060     3.366 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/dob_reg[0]/Q
                         net (fo=1, routed)           0.185     3.551    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[148]_0[0]
    SLICE_X104Y197       FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.086     3.759    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X104Y197       FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[0]/C
                         clock pessimism             -0.281     3.478    
    SLICE_X104Y197       FDRE (Hold_HFF2_SLICEM_C_D)
                                                      0.062     3.540    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.540    
                         arrival time                           3.551    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ls/opt_has_pipe.first_q_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.299ns  (logic 0.058ns (19.398%)  route 0.241ns (80.602%))
  Logic Levels:           0  
  Clock Path Skew:        0.226ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.575ns
    Source Clock Delay      (SCD):    3.073ns
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Net Delay (Source):      2.552ns (routing 1.256ns, distribution 1.296ns)
  Clock Net Delay (Destination): 2.902ns (routing 1.381ns, distribution 1.521ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.552     3.073    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ls/aclk
    SLICE_X27Y231        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ls/opt_has_pipe.first_q_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y231        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.058     3.131 r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ls/opt_has_pipe.first_q_reg[5]/Q
                         net (fo=1, routed)           0.241     3.372    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/D[5]
    SLICE_X27Y243        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.902     3.575    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/aclk
    SLICE_X27Y243        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q_reg[5]/C
                         clock pessimism             -0.277     3.298    
    SLICE_X27Y243        FDRE (Hold_BFF2_SLICEM_C_D)
                                                      0.062     3.360    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q_reg[5]
  -------------------------------------------------------------------
                         required time                         -3.360    
                         arrival time                           3.372    
  -------------------------------------------------------------------
                         slack                                  0.011    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         RFDAC0_CLK
Waveform(ns):       { 0.000 1.302 }
Period(ns):         2.604
Sources:            { d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     HSDAC/CLK_DAC       n/a            2.000         2.604       0.604      HSDAC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
Min Period        n/a     HSDAC/FABRIC_CLK    n/a            2.000         2.604       0.604      HSDAC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Min Period        n/a     HSDAC/FABRIC_CLK    n/a            2.000         2.604       0.604      HSDAC_X0Y1     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X11Y89  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X11Y91  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X10Y62  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_real_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X10Y64  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_real_i/RAM_reg_bram_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X11Y59  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[10].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X11Y63  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[10].mem_imag_i/RAM_reg_bram_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X11Y57  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[10].mem_real_i/RAM_reg_bram_0/CLKBWRCLK
Low Pulse Width   Slow    HSDAC/CLK_DAC       n/a            0.800         1.302       0.502      HSDAC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
Low Pulse Width   Fast    HSDAC/CLK_DAC       n/a            0.800         1.302       0.502      HSDAC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
Low Pulse Width   Slow    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Low Pulse Width   Fast    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Low Pulse Width   Slow    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y1     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
Low Pulse Width   Fast    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y1     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.302       0.760      RAMB36_X11Y89  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.302       0.760      RAMB36_X11Y89  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.302       0.760      RAMB36_X11Y91  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_1/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.302       0.760      RAMB36_X11Y91  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_1/CLKBWRCLK
High Pulse Width  Slow    HSDAC/CLK_DAC       n/a            0.800         1.302       0.502      HSDAC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
High Pulse Width  Fast    HSDAC/CLK_DAC       n/a            0.800         1.302       0.502      HSDAC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
High Pulse Width  Slow    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
High Pulse Width  Fast    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
High Pulse Width  Slow    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y1     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
High Pulse Width  Fast    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y1     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.302       0.760      RAMB36_X11Y89  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.302       0.760      RAMB36_X11Y89  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.302       0.760      RAMB36_X11Y91  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_1/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.302       0.760      RAMB36_X11Y91  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_1/CLKBWRCLK



---------------------------------------------------------------------------------------------------
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Setup :            0  Failing Endpoints,  Worst Slack        2.061ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.010ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.061ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg6_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.666ns  (logic 0.672ns (8.766%)  route 6.994ns (91.234%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.169ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.050ns = ( 12.050 - 10.000 ) 
    Source Clock Delay      (SCD):    2.348ns
    Clock Pessimism Removal (CPR):    0.129ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.122ns (routing 0.662ns, distribution 1.460ns)
  Clock Net Delay (Destination): 1.868ns (routing 0.599ns, distribution 1.269ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.122     2.348    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[42])
                                                      0.524     2.872 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[42]
                         net (fo=5, routed)           1.760     4.632    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[42]
    SLICE_X40Y42         LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.148     4.780 r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[10]_INST_0/O
                         net (fo=82, routed)          5.234    10.014    d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/s_axi_wdata[10]
    SLICE_X36Y162        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg6_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.868    12.050    d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X36Y162        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg6_reg[10]/C
                         clock pessimism              0.129    12.179    
                         clock uncertainty           -0.130    12.049    
    SLICE_X36Y162        FDRE (Setup_HFF_SLICEL_C_D)
                                                      0.025    12.074    d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg6_reg[10]
  -------------------------------------------------------------------
                         required time                         12.074    
                         arrival time                         -10.014    
  -------------------------------------------------------------------
                         slack                                  2.061    

Slack (MET) :             2.513ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/data_writer_i/mem_addr_high_r_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[11].mem_real_i/RAM_reg_bram_0/ADDRARDADDR[14]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.101ns  (logic 0.077ns (1.084%)  route 7.024ns (98.916%))
  Logic Levels:           0  
  Clock Path Skew:        0.030ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.325ns = ( 12.325 - 10.000 ) 
    Source Clock Delay      (SCD):    2.402ns
    Clock Pessimism Removal (CPR):    0.107ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.176ns (routing 0.662ns, distribution 1.514ns)
  Clock Net Delay (Destination): 2.143ns (routing 0.599ns, distribution 1.544ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.176     2.402    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/data_writer_i/s0_axis_aclk
    SLICE_X75Y134        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/data_writer_i/mem_addr_high_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y134        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.479 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/data_writer_i/mem_addr_high_r_reg[10]/Q
                         net (fo=32, routed)          7.024     9.503    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[11].mem_real_i/Q[10]
    RAMB36_X9Y74         RAMB36E2                                     r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[11].mem_real_i/RAM_reg_bram_0/ADDRARDADDR[14]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.143    12.325    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[11].mem_real_i/s0_axis_aclk
    RAMB36_X9Y74         RAMB36E2                                     r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[11].mem_real_i/RAM_reg_bram_0/CLKARDCLK
                         clock pessimism              0.107    12.432    
                         clock uncertainty           -0.130    12.302    
    RAMB36_X9Y74         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ADDRARDADDR[14])
                                                     -0.287    12.015    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[11].mem_real_i/RAM_reg_bram_0
  -------------------------------------------------------------------
                         required time                         12.015    
                         arrival time                          -9.503    
  -------------------------------------------------------------------
                         slack                                  2.513    

Slack (MET) :             2.606ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/data_writer_i/mem_addr_high_r_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[0].mem_real_i/RAM_reg_bram_0/ADDRARDADDR[14]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.010ns  (logic 0.077ns (1.098%)  route 6.933ns (98.902%))
  Logic Levels:           0  
  Clock Path Skew:        0.032ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.327ns = ( 12.327 - 10.000 ) 
    Source Clock Delay      (SCD):    2.402ns
    Clock Pessimism Removal (CPR):    0.107ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.176ns (routing 0.662ns, distribution 1.514ns)
  Clock Net Delay (Destination): 2.145ns (routing 0.599ns, distribution 1.546ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.176     2.402    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/data_writer_i/s0_axis_aclk
    SLICE_X75Y134        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/data_writer_i/mem_addr_high_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y134        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.479 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/data_writer_i/mem_addr_high_r_reg[10]/Q
                         net (fo=32, routed)          6.933     9.412    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[0].mem_real_i/Q[10]
    RAMB36_X9Y73         RAMB36E2                                     r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[0].mem_real_i/RAM_reg_bram_0/ADDRARDADDR[14]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.145    12.327    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[0].mem_real_i/s0_axis_aclk
    RAMB36_X9Y73         RAMB36E2                                     r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[0].mem_real_i/RAM_reg_bram_0/CLKARDCLK
                         clock pessimism              0.107    12.434    
                         clock uncertainty           -0.130    12.304    
    RAMB36_X9Y73         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ADDRARDADDR[14])
                                                     -0.287    12.017    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[0].mem_real_i/RAM_reg_bram_0
  -------------------------------------------------------------------
                         required time                         12.017    
                         arrival time                          -9.412    
  -------------------------------------------------------------------
                         slack                                  2.606    

Slack (MET) :             2.650ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg4_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.077ns  (logic 0.672ns (9.495%)  route 6.405ns (90.505%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.168ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.051ns = ( 12.051 - 10.000 ) 
    Source Clock Delay      (SCD):    2.348ns
    Clock Pessimism Removal (CPR):    0.129ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.122ns (routing 0.662ns, distribution 1.460ns)
  Clock Net Delay (Destination): 1.869ns (routing 0.599ns, distribution 1.270ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.122     2.348    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[42])
                                                      0.524     2.872 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[42]
                         net (fo=5, routed)           1.760     4.632    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[42]
    SLICE_X40Y42         LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.148     4.780 r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[10]_INST_0/O
                         net (fo=82, routed)          4.646     9.425    d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/s_axi_wdata[10]
    SLICE_X35Y162        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg4_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.869    12.051    d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X35Y162        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg4_reg[10]/C
                         clock pessimism              0.129    12.180    
                         clock uncertainty           -0.130    12.050    
    SLICE_X35Y162        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    12.075    d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg4_reg[10]
  -------------------------------------------------------------------
                         required time                         12.075    
                         arrival time                          -9.425    
  -------------------------------------------------------------------
                         slack                                  2.650    

Slack (MET) :             2.650ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg14_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.065ns  (logic 0.672ns (9.512%)  route 6.393ns (90.488%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.180ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.039ns = ( 12.039 - 10.000 ) 
    Source Clock Delay      (SCD):    2.348ns
    Clock Pessimism Removal (CPR):    0.129ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.122ns (routing 0.662ns, distribution 1.460ns)
  Clock Net Delay (Destination): 1.857ns (routing 0.599ns, distribution 1.258ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.122     2.348    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[42])
                                                      0.524     2.872 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[42]
                         net (fo=5, routed)           1.760     4.632    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[42]
    SLICE_X40Y42         LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.148     4.780 r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[10]_INST_0/O
                         net (fo=82, routed)          4.633     9.413    d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/s_axi_wdata[10]
    SLICE_X37Y162        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg14_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.857    12.039    d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X37Y162        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg14_reg[10]/C
                         clock pessimism              0.129    12.168    
                         clock uncertainty           -0.130    12.038    
    SLICE_X37Y162        FDRE (Setup_EFF_SLICEM_C_D)
                                                      0.025    12.063    d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg14_reg[10]
  -------------------------------------------------------------------
                         required time                         12.063    
                         arrival time                          -9.413    
  -------------------------------------------------------------------
                         slack                                  2.650    

Slack (MET) :             2.653ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/data_writer_i/mem_addr_high_r_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[10].mem_real_i/RAM_reg_bram_0/ADDRARDADDR[14]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        6.963ns  (logic 0.077ns (1.106%)  route 6.886ns (98.894%))
  Logic Levels:           0  
  Clock Path Skew:        0.033ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.328ns = ( 12.328 - 10.000 ) 
    Source Clock Delay      (SCD):    2.402ns
    Clock Pessimism Removal (CPR):    0.107ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.176ns (routing 0.662ns, distribution 1.514ns)
  Clock Net Delay (Destination): 2.146ns (routing 0.599ns, distribution 1.547ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.176     2.402    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/data_writer_i/s0_axis_aclk
    SLICE_X75Y134        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/data_writer_i/mem_addr_high_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y134        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.479 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/data_writer_i/mem_addr_high_r_reg[10]/Q
                         net (fo=32, routed)          6.886     9.365    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[10].mem_real_i/Q[10]
    RAMB36_X9Y72         RAMB36E2                                     r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[10].mem_real_i/RAM_reg_bram_0/ADDRARDADDR[14]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.146    12.328    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[10].mem_real_i/s0_axis_aclk
    RAMB36_X9Y72         RAMB36E2                                     r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[10].mem_real_i/RAM_reg_bram_0/CLKARDCLK
                         clock pessimism              0.107    12.435    
                         clock uncertainty           -0.130    12.305    
    RAMB36_X9Y72         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ADDRARDADDR[14])
                                                     -0.287    12.018    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[10].mem_real_i/RAM_reg_bram_0
  -------------------------------------------------------------------
                         required time                         12.018    
                         arrival time                          -9.365    
  -------------------------------------------------------------------
                         slack                                  2.653    

Slack (MET) :             2.669ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg11_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.060ns  (logic 0.672ns (9.518%)  route 6.388ns (90.482%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.166ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.053ns = ( 12.053 - 10.000 ) 
    Source Clock Delay      (SCD):    2.348ns
    Clock Pessimism Removal (CPR):    0.129ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.122ns (routing 0.662ns, distribution 1.460ns)
  Clock Net Delay (Destination): 1.871ns (routing 0.599ns, distribution 1.272ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.122     2.348    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[42])
                                                      0.524     2.872 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[42]
                         net (fo=5, routed)           1.760     4.632    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[42]
    SLICE_X40Y42         LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.148     4.780 r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[10]_INST_0/O
                         net (fo=82, routed)          4.629     9.408    d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/s_axi_wdata[10]
    SLICE_X35Y163        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg11_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.871    12.053    d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X35Y163        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg11_reg[10]/C
                         clock pessimism              0.129    12.182    
                         clock uncertainty           -0.130    12.052    
    SLICE_X35Y163        FDRE (Setup_AFF_SLICEM_C_D)
                                                      0.025    12.077    d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg11_reg[10]
  -------------------------------------------------------------------
                         required time                         12.077    
                         arrival time                          -9.408    
  -------------------------------------------------------------------
                         slack                                  2.669    

Slack (MET) :             2.679ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/data_writer_i/mem_addr_high_r_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[14].mem_real_i/RAM_reg_bram_0/ADDRARDADDR[14]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        6.930ns  (logic 0.077ns (1.111%)  route 6.853ns (98.889%))
  Logic Levels:           0  
  Clock Path Skew:        0.026ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.321ns = ( 12.321 - 10.000 ) 
    Source Clock Delay      (SCD):    2.402ns
    Clock Pessimism Removal (CPR):    0.107ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.176ns (routing 0.662ns, distribution 1.514ns)
  Clock Net Delay (Destination): 2.139ns (routing 0.599ns, distribution 1.540ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.176     2.402    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/data_writer_i/s0_axis_aclk
    SLICE_X75Y134        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/data_writer_i/mem_addr_high_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y134        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.479 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/data_writer_i/mem_addr_high_r_reg[10]/Q
                         net (fo=32, routed)          6.853     9.332    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[14].mem_real_i/Q[10]
    RAMB36_X9Y75         RAMB36E2                                     r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[14].mem_real_i/RAM_reg_bram_0/ADDRARDADDR[14]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.139    12.321    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[14].mem_real_i/s0_axis_aclk
    RAMB36_X9Y75         RAMB36E2                                     r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[14].mem_real_i/RAM_reg_bram_0/CLKARDCLK
                         clock pessimism              0.107    12.428    
                         clock uncertainty           -0.130    12.298    
    RAMB36_X9Y75         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ADDRARDADDR[14])
                                                     -0.287    12.011    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/GEN_mem[14].mem_real_i/RAM_reg_bram_0
  -------------------------------------------------------------------
                         required time                         12.011    
                         arrival time                          -9.332    
  -------------------------------------------------------------------
                         slack                                  2.679    

Slack (MET) :             2.727ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg9_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.000ns  (logic 0.672ns (9.599%)  route 6.328ns (90.401%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.168ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.051ns = ( 12.051 - 10.000 ) 
    Source Clock Delay      (SCD):    2.348ns
    Clock Pessimism Removal (CPR):    0.129ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.122ns (routing 0.662ns, distribution 1.460ns)
  Clock Net Delay (Destination): 1.869ns (routing 0.599ns, distribution 1.270ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.122     2.348    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[42])
                                                      0.524     2.872 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[42]
                         net (fo=5, routed)           1.760     4.632    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[42]
    SLICE_X40Y42         LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.148     4.780 r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[10]_INST_0/O
                         net (fo=82, routed)          4.569     9.348    d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/s_axi_wdata[10]
    SLICE_X35Y162        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg9_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.869    12.051    d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X35Y162        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg9_reg[10]/C
                         clock pessimism              0.129    12.180    
                         clock uncertainty           -0.130    12.050    
    SLICE_X35Y162        FDRE (Setup_HFF_SLICEM_C_D)
                                                      0.025    12.075    d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg9_reg[10]
  -------------------------------------------------------------------
                         required time                         12.075    
                         arrival time                          -9.348    
  -------------------------------------------------------------------
                         slack                                  2.727    

Slack (MET) :             2.764ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg12_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        6.962ns  (logic 0.672ns (9.652%)  route 6.290ns (90.348%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.169ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.050ns = ( 12.050 - 10.000 ) 
    Source Clock Delay      (SCD):    2.348ns
    Clock Pessimism Removal (CPR):    0.129ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.122ns (routing 0.662ns, distribution 1.460ns)
  Clock Net Delay (Destination): 1.868ns (routing 0.599ns, distribution 1.269ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.122     2.348    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[42])
                                                      0.524     2.872 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[42]
                         net (fo=5, routed)           1.760     4.632    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[42]
    SLICE_X40Y42         LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.148     4.780 r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[10]_INST_0/O
                         net (fo=82, routed)          4.531     9.310    d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/s_axi_wdata[10]
    SLICE_X36Y162        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg12_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.868    12.050    d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X36Y162        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg12_reg[10]/C
                         clock pessimism              0.129    12.179    
                         clock uncertainty           -0.130    12.049    
    SLICE_X36Y162        FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.025    12.074    d_1_i/axis_signal_gen_v6_1/inst/axi_slv_i/slv_reg12_reg[10]
  -------------------------------------------------------------------
                         required time                         12.074    
                         arrival time                          -9.310    
  -------------------------------------------------------------------
                         slack                                  2.764    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[21]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.178ns  (logic 0.058ns (32.584%)  route 0.120ns (67.416%))
  Logic Levels:           0  
  Clock Path Skew:        0.106ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.407ns
    Source Clock Delay      (SCD):    2.099ns
    Clock Pessimism Removal (CPR):    0.202ns
  Clock Net Delay (Source):      1.917ns (routing 0.599ns, distribution 1.318ns)
  Clock Net Delay (Destination): 2.181ns (routing 0.662ns, distribution 1.519ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.917     2.099    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/clk
    SLICE_X30Y38         FDRE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y38         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.058     2.157 r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[21]/Q
                         net (fo=1, routed)           0.120     2.277    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[21]
    SLICE_X28Y40         FDRE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[21]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.181     2.407    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X28Y40         FDRE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[21]/C
                         clock pessimism             -0.202     2.205    
    SLICE_X28Y40         FDRE (Hold_AFF2_SLICEM_C_D)
                                                      0.062     2.267    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[21]
  -------------------------------------------------------------------
                         required time                         -2.267    
                         arrival time                           2.277    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/m_vector_i_reg[1248]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMB_D1/I
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.224ns  (logic 0.059ns (26.339%)  route 0.165ns (73.661%))
  Logic Levels:           0  
  Clock Path Skew:        0.153ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.440ns
    Source Clock Delay      (SCD):    2.089ns
    Clock Pessimism Removal (CPR):    0.198ns
  Clock Net Delay (Source):      1.907ns (routing 0.599ns, distribution 1.308ns)
  Clock Net Delay (Destination): 2.214ns (routing 0.662ns, distribution 1.552ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.907     2.089    d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/aclk
    SLICE_X26Y64         FDRE                                         r  d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/m_vector_i_reg[1248]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y64         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.059     2.148 r  d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/m_vector_i_reg[1248]/Q
                         net (fo=1, routed)           0.165     2.313    d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/DIB1
    SLICE_X28Y65         RAMD32                                       r  d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMB_D1/I
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.214     2.440    d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/WCLK
    SLICE_X28Y65         RAMD32                                       r  d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMB_D1/CLK
                         clock pessimism             -0.198     2.242    
    SLICE_X28Y65         RAMD32 (Hold_B6LUT_SLICEM_CLK_I)
                                                      0.060     2.302    d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMB_D1
  -------------------------------------------------------------------
                         required time                         -2.302    
                         arrival time                           2.313    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m25_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg[44]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m25_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/cmd_translator_0/wrap_cmd_0/wrap_boundary_axaddr_r_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.237ns  (logic 0.095ns (40.058%)  route 0.142ns (59.942%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.166ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.427ns
    Source Clock Delay      (SCD):    2.062ns
    Clock Pessimism Removal (CPR):    0.199ns
  Clock Net Delay (Source):      1.880ns (routing 0.599ns, distribution 1.281ns)
  Clock Net Delay (Destination): 2.201ns (routing 0.662ns, distribution 1.539ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.880     2.062    d_1_i/ps8_0_axi_periph/m25_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/aclk
    SLICE_X60Y11         FDRE                                         r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg[44]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y11         FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.060     2.122 r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg[44]/Q
                         net (fo=28, routed)          0.113     2.235    d_1_i/ps8_0_axi_periph/m25_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/Q[44]
    SLICE_X61Y11         LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.035     2.270 r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/wrap_boundary_axaddr_r[2]_i_1/O
                         net (fo=1, routed)           0.029     2.299    d_1_i/ps8_0_axi_periph/m25_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/cmd_translator_0/wrap_cmd_0/wrap_boundary_axaddr_r_reg[6]_0[2]
    SLICE_X61Y11         FDRE                                         r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/cmd_translator_0/wrap_cmd_0/wrap_boundary_axaddr_r_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.201     2.427    d_1_i/ps8_0_axi_periph/m25_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/cmd_translator_0/wrap_cmd_0/aclk
    SLICE_X61Y11         FDRE                                         r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/cmd_translator_0/wrap_cmd_0/wrap_boundary_axaddr_r_reg[2]/C
                         clock pessimism             -0.199     2.228    
    SLICE_X61Y11         FDRE (Hold_BFF_SLICEM_C_D)
                                                      0.060     2.288    d_1_i/ps8_0_axi_periph/m25_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/cmd_translator_0/wrap_cmd_0/wrap_boundary_axaddr_r_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.288    
                         arrival time                           2.299    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg[39]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/tier2_xbar_1/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/gen_no_arbiter.m_amesg_i_reg[40]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.171ns  (logic 0.095ns (55.556%)  route 0.076ns (44.444%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.100ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.350ns
    Source Clock Delay      (SCD):    2.054ns
    Clock Pessimism Removal (CPR):    0.196ns
  Clock Net Delay (Source):      1.872ns (routing 0.599ns, distribution 1.273ns)
  Clock Net Delay (Destination): 2.124ns (routing 0.662ns, distribution 1.462ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.872     2.054    d_1_i/ps8_0_axi_periph/i01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/aclk
    SLICE_X49Y56         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg[39]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y56         FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.060     2.114 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg[39]/Q
                         net (fo=1, routed)           0.056     2.170    d_1_i/ps8_0_axi_periph/tier2_xbar_1/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/s_axi_araddr[39]
    SLICE_X47Y56         LUT4 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.035     2.205 r  d_1_i/ps8_0_axi_periph/tier2_xbar_1/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/gen_no_arbiter.m_amesg_i[40]_i_2/O
                         net (fo=1, routed)           0.020     2.225    d_1_i/ps8_0_axi_periph/tier2_xbar_1/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/s_amesg[40]
    SLICE_X47Y56         FDRE                                         r  d_1_i/ps8_0_axi_periph/tier2_xbar_1/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/gen_no_arbiter.m_amesg_i_reg[40]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.124     2.350    d_1_i/ps8_0_axi_periph/tier2_xbar_1/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/aclk
    SLICE_X47Y56         FDRE                                         r  d_1_i/ps8_0_axi_periph/tier2_xbar_1/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/gen_no_arbiter.m_amesg_i_reg[40]/C
                         clock pessimism             -0.196     2.154    
    SLICE_X47Y56         FDRE (Hold_EFF_SLICEL_C_D)
                                                      0.060     2.214    d_1_i/ps8_0_axi_periph/tier2_xbar_1/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/gen_no_arbiter.m_amesg_i_reg[40]
  -------------------------------------------------------------------
                         required time                         -2.214    
                         arrival time                           2.225    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s05_entry_pipeline/s05_transaction_regulator/inst/gen_endpoint.gen_w_singleorder.w_singleorder/gen_cmd_reg.cmd_reg/m_vector_i_reg[1073]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s05_nodes/s05_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMA/I
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.235ns  (logic 0.059ns (25.106%)  route 0.176ns (74.894%))
  Logic Levels:           0  
  Clock Path Skew:        0.149ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.381ns
    Source Clock Delay      (SCD):    2.040ns
    Clock Pessimism Removal (CPR):    0.192ns
  Clock Net Delay (Source):      1.858ns (routing 0.599ns, distribution 1.259ns)
  Clock Net Delay (Destination): 2.155ns (routing 0.662ns, distribution 1.493ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.858     2.040    d_1_i/axi_smc/inst/s05_entry_pipeline/s05_transaction_regulator/inst/gen_endpoint.gen_w_singleorder.w_singleorder/gen_cmd_reg.cmd_reg/aclk
    SLICE_X50Y66         FDRE                                         r  d_1_i/axi_smc/inst/s05_entry_pipeline/s05_transaction_regulator/inst/gen_endpoint.gen_w_singleorder.w_singleorder/gen_cmd_reg.cmd_reg/m_vector_i_reg[1073]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y66         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.059     2.099 r  d_1_i/axi_smc/inst/s05_entry_pipeline/s05_transaction_regulator/inst/gen_endpoint.gen_w_singleorder.w_singleorder/gen_cmd_reg.cmd_reg/m_vector_i_reg[1073]/Q
                         net (fo=1, routed)           0.176     2.275    d_1_i/axi_smc/inst/s05_nodes/s05_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/DIA0
    SLICE_X48Y67         RAMD32                                       r  d_1_i/axi_smc/inst/s05_nodes/s05_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMA/I
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.155     2.381    d_1_i/axi_smc/inst/s05_nodes/s05_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/WCLK
    SLICE_X48Y67         RAMD32                                       r  d_1_i/axi_smc/inst/s05_nodes/s05_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMA/CLK
                         clock pessimism             -0.192     2.189    
    SLICE_X48Y67         RAMD32 (Hold_A5LUT_SLICEM_CLK_I)
                                                      0.075     2.264    d_1_i/axi_smc/inst/s05_nodes/s05_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMA
  -------------------------------------------------------------------
                         required time                         -2.264    
                         arrival time                           2.275    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_buf/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_cntr_lsh_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_buf/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.179ns  (logic 0.058ns (32.472%)  route 0.121ns (67.528%))
  Logic Levels:           0  
  Clock Path Skew:        0.107ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.403ns
    Source Clock Delay      (SCD):    2.096ns
    Clock Pessimism Removal (CPR):    0.200ns
  Clock Net Delay (Source):      1.914ns (routing 0.599ns, distribution 1.315ns)
  Clock Net Delay (Destination): 2.177ns (routing 0.662ns, distribution 1.515ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.914     2.096    d_1_i/axi_dma_buf/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk
    SLICE_X64Y73         FDRE                                         r  d_1_i/axi_dma_buf/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_cntr_lsh_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y73         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     2.154 r  d_1_i/axi_dma_buf/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_cntr_lsh_reg[15]/Q
                         net (fo=4, routed)           0.121     2.274    d_1_i/axi_dma_buf/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/p_1_in7_in
    SLICE_X62Y74         FDRE                                         r  d_1_i/axi_dma_buf/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.177     2.403    d_1_i/axi_dma_buf/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk
    SLICE_X62Y74         FDRE                                         r  d_1_i/axi_dma_buf/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[15]/C
                         clock pessimism             -0.200     2.203    
    SLICE_X62Y74         FDRE (Hold_CFF_SLICEL_C_D)
                                                      0.060     2.263    d_1_i/axi_dma_buf/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[15]
  -------------------------------------------------------------------
                         required time                         -2.263    
                         arrival time                           2.274    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_strb_reg_out_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[2070]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.125ns  (logic 0.059ns (47.200%)  route 0.066ns (52.800%))
  Logic Levels:           0  
  Clock Path Skew:        0.051ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.398ns
    Source Clock Delay      (SCD):    2.099ns
    Clock Pessimism Removal (CPR):    0.248ns
  Clock Net Delay (Source):      1.917ns (routing 0.599ns, distribution 1.318ns)
  Clock Net Delay (Destination): 2.172ns (routing 0.662ns, distribution 1.510ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.917     2.099    d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/m_axi_s2mm_aclk
    SLICE_X29Y64         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_strb_reg_out_reg[21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y64         FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     2.158 r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_strb_reg_out_reg[21]/Q
                         net (fo=2, routed)           0.066     2.224    d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/D[278]
    SLICE_X29Y65         FDRE                                         r  d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[2070]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.172     2.398    d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/aclk
    SLICE_X29Y65         FDRE                                         r  d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[2070]/C
                         clock pessimism             -0.248     2.151    
    SLICE_X29Y65         FDRE (Hold_AFF2_SLICEL_C_D)
                                                      0.062     2.213    d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[2070]
  -------------------------------------------------------------------
                         required time                         -2.213    
                         arrival time                           2.224    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/length_counter_1_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.179ns  (logic 0.083ns (46.264%)  route 0.096ns (53.736%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.108ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.336ns
    Source Clock Delay      (SCD):    2.032ns
    Clock Pessimism Removal (CPR):    0.196ns
  Clock Net Delay (Source):      1.850ns (routing 0.599ns, distribution 1.251ns)
  Clock Net Delay (Destination): 2.110ns (routing 0.662ns, distribution 1.448ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.850     2.032    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X60Y31         FDRE                                         r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y31         FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.060     2.092 r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[9]/Q
                         net (fo=3, routed)           0.072     2.164    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/dout[6]
    SLICE_X58Y30         LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.023     2.187 r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/length_counter_1[7]_i_1__0/O
                         net (fo=1, routed)           0.024     2.211    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/next_length_counter__0[7]
    SLICE_X58Y30         FDRE                                         r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/length_counter_1_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.110     2.336    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/CLK
    SLICE_X58Y30         FDRE                                         r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/length_counter_1_reg[7]/C
                         clock pessimism             -0.196     2.140    
    SLICE_X58Y30         FDRE (Hold_HFF_SLICEL_C_D)
                                                      0.060     2.200    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/length_counter_1_reg[7]
  -------------------------------------------------------------------
                         required time                         -2.200    
                         arrival time                           2.211    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_axi_ctrl_write/data_r_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_reg_bank_1/gen_reg[6].reg_data_reg[207]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.177ns  (logic 0.060ns (33.811%)  route 0.117ns (66.189%))
  Logic Levels:           0  
  Clock Path Skew:        0.104ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.341ns
    Source Clock Delay      (SCD):    2.045ns
    Clock Pessimism Removal (CPR):    0.193ns
  Clock Net Delay (Source):      1.863ns (routing 0.599ns, distribution 1.264ns)
  Clock Net Delay (Destination): 2.115ns (routing 0.662ns, distribution 1.453ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.863     2.045    d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_axi_ctrl_write/s_axi_ctrl_aclk
    SLICE_X37Y139        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_axi_ctrl_write/data_r_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y139        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.060     2.105 r  d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_axi_ctrl_write/data_r_reg[15]/Q
                         net (fo=9, routed)           0.117     2.222    d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_reg_bank_1/D[15]
    SLICE_X36Y138        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_reg_bank_1/gen_reg[6].reg_data_reg[207]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.115     2.341    d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_reg_bank_1/s_axi_ctrl_aclk
    SLICE_X36Y138        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_reg_bank_1/gen_reg[6].reg_data_reg[207]/C
                         clock pessimism             -0.193     2.148    
    SLICE_X36Y138        FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.062     2.210    d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_reg_bank_1/gen_reg[6].reg_data_reg[207]
  -------------------------------------------------------------------
                         required time                         -2.210    
                         arrival time                           2.222    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m25_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/m_payload_i_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[0].S_AXI_RDATA_II_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.166ns  (logic 0.059ns (35.445%)  route 0.107ns (64.555%))
  Logic Levels:           0  
  Clock Path Skew:        0.093ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.401ns
    Source Clock Delay      (SCD):    2.104ns
    Clock Pessimism Removal (CPR):    0.205ns
  Clock Net Delay (Source):      1.922ns (routing 0.599ns, distribution 1.323ns)
  Clock Net Delay (Destination): 2.175ns (routing 0.662ns, distribution 1.513ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.922     2.104    d_1_i/ps8_0_axi_periph/m25_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/aclk
    SLICE_X62Y37         FDRE                                         r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/m_payload_i_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y37         FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     2.163 r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/m_payload_i_reg[3]/Q
                         net (fo=8, routed)           0.107     2.270    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/m_axi_rdata[3]
    SLICE_X64Y35         FDRE                                         r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[0].S_AXI_RDATA_II_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.175     2.401    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/CLK
    SLICE_X64Y35         FDRE                                         r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[0].S_AXI_RDATA_II_reg[3]/C
                         clock pessimism             -0.205     2.196    
    SLICE_X64Y35         FDRE (Hold_DFF2_SLICEL_C_D)
                                                      0.062     2.258    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[0].S_AXI_RDATA_II_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.258    
                         arrival time                           2.270    
  -------------------------------------------------------------------
                         slack                                  0.012    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_pl_0
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location    Pin
Min Period        n/a     HSADC/DCLK         n/a            4.000         10.000      6.000      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
Min Period        n/a     HSADC/DCLK         n/a            4.000         10.000      6.000      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
Min Period        n/a     HSADC/DCLK         n/a            4.000         10.000      6.000      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
Min Period        n/a     HSADC/DCLK         n/a            4.000         10.000      6.000      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
Min Period        n/a     HSDAC/DCLK         n/a            4.000         10.000      6.000      HSDAC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DCLK
Min Period        n/a     HSDAC/DCLK         n/a            4.000         10.000      6.000      HSDAC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/DCLK
Min Period        n/a     PS8/MAXIGP0ACLK    n/a            3.000         10.000      7.000      PS8_X0Y0    d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
Min Period        n/a     PS8/SAXIGP0RCLK    n/a            3.000         10.000      7.000      PS8_X0Y0    d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/SAXIGP0RCLK
Min Period        n/a     PS8/SAXIGP0WCLK    n/a            3.000         10.000      7.000      PS8_X0Y0    d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/SAXIGP0WCLK
Min Period        n/a     HSADC/PLL_MONCLK   n/a            2.500         10.000      7.500      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
Max Period        n/a     MMCME4_ADV/CLKIN1  n/a            100.000       10.000      90.000     MMCM_X0Y5   d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    MMCME4_ADV/CLKIN1  n/a            3.000         5.000       2.000      MMCM_X0Y5   d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Fast    MMCME4_ADV/CLKIN1  n/a            3.000         5.000       2.000      MMCM_X0Y5   d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
Low Pulse Width   Fast    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
Low Pulse Width   Slow    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
Low Pulse Width   Fast    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
Low Pulse Width   Slow    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
Low Pulse Width   Fast    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
Low Pulse Width   Slow    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
Low Pulse Width   Fast    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
High Pulse Width  Slow    MMCME4_ADV/CLKIN1  n/a            3.000         5.000       2.000      MMCM_X0Y5   d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Fast    MMCME4_ADV/CLKIN1  n/a            3.000         5.000       2.000      MMCM_X0Y5   d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Slow    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
High Pulse Width  Fast    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
High Pulse Width  Slow    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
High Pulse Width  Fast    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
High Pulse Width  Slow    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
High Pulse Width  Fast    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
High Pulse Width  Slow    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
High Pulse Width  Fast    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK



---------------------------------------------------------------------------------------------------
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  clk_out1_d_1_clk_core_0

Setup :            0  Failing Endpoints,  Worst Slack        0.287ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.022ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.958ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.287ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_dt_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/DINBDIN[6]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.300ns  (logic 0.810ns (18.836%)  route 3.490ns (81.164%))
  Logic Levels:           8  (CARRY8=3 LUT3=2 LUT6=2 MUXF7=1)
  Clock Path Skew:        -0.096ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.058ns = ( 10.058 - 5.000 ) 
    Source Clock Delay      (SCD):    4.783ns
    Clock Pessimism Removal (CPR):    -0.371ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.269ns (routing 1.037ns, distribution 1.232ns)
  Clock Net Delay (Destination): 2.076ns (routing 0.940ns, distribution 1.136ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.269     4.783    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_clk_i
    SLICE_X67Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_dt_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y167        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.859 f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_dt_reg[0]/Q
                         net (fo=30, routed)          0.891     5.750    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/Q[0]
    SLICE_X55Y188        LUT3 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.099     5.849 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[16]_i_22/O
                         net (fo=1, routed)           0.375     6.224    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/alu/p_0_in[0]
    SLICE_X60Y177        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.153     6.377 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[16]_i_13/CO[7]
                         net (fo=1, routed)           0.026     6.403    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[16]_i_13_n_0
    SLICE_X60Y178        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     6.418 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[16]_i_9/CO[7]
                         net (fo=1, routed)           0.026     6.444    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[16]_i_9_n_0
    SLICE_X60Y179        CARRY8 (Prop_CARRY8_SLICEM_CI_O[7])
                                                      0.116     6.560 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[30]_i_16/O[7]
                         net (fo=1, routed)           0.246     6.806    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/alu/neg_B[24]
    SLICE_X59Y182        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.146     6.952 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[24]_i_9/O
                         net (fo=1, routed)           0.010     6.962    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[24]_i_9_n_0
    SLICE_X59Y182        MUXF7 (Prop_F7MUX_CD_SLICEL_I1_O)
                                                      0.064     7.026 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[24]_i_4/O
                         net (fo=1, routed)           0.279     7.305    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[24]_i_4_n_0
    SLICE_X58Y189        LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.089     7.394 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[24]_i_1/O
                         net (fo=7, routed)           0.342     7.736    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/x1_alu_dt[24]
    SLICE_X61Y182        LUT3 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.052     7.788 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/RAM_reg_bram_8_i_5/O
                         net (fo=4, routed)           1.295     9.083    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/dmem_w_dt[24]
    RAMB36_X6Y60         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/DINBDIN[6]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.076    10.058    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X6Y60         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/CLKBWRCLK
                         clock pessimism             -0.371     9.687    
                         clock uncertainty           -0.062     9.625    
    RAMB36_X6Y60         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[6])
                                                     -0.255     9.370    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11
  -------------------------------------------------------------------
                         required time                          9.370    
                         arrival time                          -9.083    
  -------------------------------------------------------------------
                         slack                                  0.287    

Slack (MET) :             0.296ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/WEBWE[0]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.206ns  (logic 0.615ns (14.622%)  route 3.591ns (85.378%))
  Logic Levels:           5  (LUT4=1 LUT5=3 LUT6=1)
  Clock Path Skew:        -0.042ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.058ns = ( 10.058 - 5.000 ) 
    Source Clock Delay      (SCD):    4.729ns
    Clock Pessimism Removal (CPR):    -0.371ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.215ns (routing 1.037ns, distribution 1.178ns)
  Clock Net Delay (Destination): 2.076ns (routing 0.940ns, distribution 1.136ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.215     4.729    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/c_clk_i
    SLICE_X72Y232        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y232        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     4.809 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[8]/Q
                         net (fo=1, routed)           0.871     5.680    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg[8]
    SLICE_X72Y139        LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.088     5.768 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg_i_3__13/O
                         net (fo=3, routed)           0.238     6.006    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg_i_3__13_n_0
    SLICE_X73Y138        LUT5 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.051     6.057 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/core_en_i_9/O
                         net (fo=4, routed)           0.643     6.700    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]
    SLICE_X77Y170        LUT5 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.123     6.823 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/core_en_i_2/O
                         net (fo=3, routed)           0.154     6.977    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER_n_303
    SLICE_X76Y169        LUT5 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     7.102 r  d_1_i/qick_processor_0/inst/QPROC/core_en/O
                         net (fo=600, routed)         0.955     8.057    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/E[0]
    SLICE_X66Y237        LUT4 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.148     8.205 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/RAM_reg_bram_11_i_6/O
                         net (fo=4, routed)           0.730     8.935    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11_5[0]
    RAMB36_X6Y60         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/WEBWE[0]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.076    10.058    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X6Y60         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/CLKBWRCLK
                         clock pessimism             -0.371     9.687    
                         clock uncertainty           -0.062     9.625    
    RAMB36_X6Y60         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[0])
                                                     -0.394     9.231    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11
  -------------------------------------------------------------------
                         required time                          9.231    
                         arrival time                          -8.935    
  -------------------------------------------------------------------
                         slack                                  0.296    

Slack (MET) :             0.297ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_9/WEBWE[0]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.187ns  (logic 0.564ns (13.471%)  route 3.623ns (86.529%))
  Logic Levels:           5  (LUT4=1 LUT5=3 LUT6=1)
  Clock Path Skew:        -0.060ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.040ns = ( 10.040 - 5.000 ) 
    Source Clock Delay      (SCD):    4.729ns
    Clock Pessimism Removal (CPR):    -0.371ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.215ns (routing 1.037ns, distribution 1.178ns)
  Clock Net Delay (Destination): 2.058ns (routing 0.940ns, distribution 1.118ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.215     4.729    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/c_clk_i
    SLICE_X72Y232        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y232        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     4.809 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[8]/Q
                         net (fo=1, routed)           0.871     5.680    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg[8]
    SLICE_X72Y139        LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.088     5.768 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg_i_3__13/O
                         net (fo=3, routed)           0.238     6.006    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg_i_3__13_n_0
    SLICE_X73Y138        LUT5 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.051     6.057 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/core_en_i_9/O
                         net (fo=4, routed)           0.643     6.700    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]
    SLICE_X77Y170        LUT5 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.123     6.823 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/core_en_i_2/O
                         net (fo=3, routed)           0.154     6.977    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER_n_303
    SLICE_X76Y169        LUT5 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     7.102 r  d_1_i/qick_processor_0/inst/QPROC/core_en/O
                         net (fo=600, routed)         1.032     8.134    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/E[0]
    SLICE_X65Y237        LUT4 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.097     8.231 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/RAM_reg_bram_9_i_6/O
                         net (fo=4, routed)           0.685     8.916    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_9_5[0]
    RAMB36_X6Y58         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_9/WEBWE[0]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.058    10.040    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X6Y58         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_9/CLKBWRCLK
                         clock pessimism             -0.371     9.669    
                         clock uncertainty           -0.062     9.607    
    RAMB36_X6Y58         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[0])
                                                     -0.394     9.213    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_9
  -------------------------------------------------------------------
                         required time                          9.213    
                         arrival time                          -8.916    
  -------------------------------------------------------------------
                         slack                                  0.297    

Slack (MET) :             0.309ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_10/WEBWE[0]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.176ns  (logic 0.518ns (12.404%)  route 3.658ns (87.596%))
  Logic Levels:           5  (LUT4=1 LUT5=3 LUT6=1)
  Clock Path Skew:        -0.059ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.041ns = ( 10.041 - 5.000 ) 
    Source Clock Delay      (SCD):    4.729ns
    Clock Pessimism Removal (CPR):    -0.371ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.215ns (routing 1.037ns, distribution 1.178ns)
  Clock Net Delay (Destination): 2.059ns (routing 0.940ns, distribution 1.119ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.215     4.729    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/c_clk_i
    SLICE_X72Y232        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y232        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     4.809 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[8]/Q
                         net (fo=1, routed)           0.871     5.680    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg[8]
    SLICE_X72Y139        LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.088     5.768 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg_i_3__13/O
                         net (fo=3, routed)           0.238     6.006    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg_i_3__13_n_0
    SLICE_X73Y138        LUT5 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.051     6.057 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/core_en_i_9/O
                         net (fo=4, routed)           0.643     6.700    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]
    SLICE_X77Y170        LUT5 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.123     6.823 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/core_en_i_2/O
                         net (fo=3, routed)           0.154     6.977    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER_n_303
    SLICE_X76Y169        LUT5 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     7.102 r  d_1_i/qick_processor_0/inst/QPROC/core_en/O
                         net (fo=600, routed)         1.041     8.143    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/E[0]
    SLICE_X65Y237        LUT4 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.051     8.194 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/RAM_reg_bram_10_i_6/O
                         net (fo=4, routed)           0.711     8.905    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_10_5[0]
    RAMB36_X6Y59         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_10/WEBWE[0]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.059    10.041    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X6Y59         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_10/CLKBWRCLK
                         clock pessimism             -0.371     9.670    
                         clock uncertainty           -0.062     9.608    
    RAMB36_X6Y59         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[0])
                                                     -0.394     9.214    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_10
  -------------------------------------------------------------------
                         required time                          9.214    
                         arrival time                          -8.905    
  -------------------------------------------------------------------
                         slack                                  0.309    

Slack (MET) :             0.375ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_dt_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_9/DINBDIN[6]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.194ns  (logic 0.810ns (19.313%)  route 3.384ns (80.687%))
  Logic Levels:           8  (CARRY8=3 LUT3=2 LUT6=2 MUXF7=1)
  Clock Path Skew:        -0.114ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.040ns = ( 10.040 - 5.000 ) 
    Source Clock Delay      (SCD):    4.783ns
    Clock Pessimism Removal (CPR):    -0.371ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.269ns (routing 1.037ns, distribution 1.232ns)
  Clock Net Delay (Destination): 2.058ns (routing 0.940ns, distribution 1.118ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.269     4.783    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_clk_i
    SLICE_X67Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_dt_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y167        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.859 f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_dt_reg[0]/Q
                         net (fo=30, routed)          0.891     5.750    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/Q[0]
    SLICE_X55Y188        LUT3 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.099     5.849 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[16]_i_22/O
                         net (fo=1, routed)           0.375     6.224    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/alu/p_0_in[0]
    SLICE_X60Y177        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.153     6.377 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[16]_i_13/CO[7]
                         net (fo=1, routed)           0.026     6.403    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[16]_i_13_n_0
    SLICE_X60Y178        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     6.418 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[16]_i_9/CO[7]
                         net (fo=1, routed)           0.026     6.444    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[16]_i_9_n_0
    SLICE_X60Y179        CARRY8 (Prop_CARRY8_SLICEM_CI_O[7])
                                                      0.116     6.560 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[30]_i_16/O[7]
                         net (fo=1, routed)           0.246     6.806    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/alu/neg_B[24]
    SLICE_X59Y182        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.146     6.952 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[24]_i_9/O
                         net (fo=1, routed)           0.010     6.962    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[24]_i_9_n_0
    SLICE_X59Y182        MUXF7 (Prop_F7MUX_CD_SLICEL_I1_O)
                                                      0.064     7.026 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[24]_i_4/O
                         net (fo=1, routed)           0.279     7.305    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[24]_i_4_n_0
    SLICE_X58Y189        LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.089     7.394 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[24]_i_1/O
                         net (fo=7, routed)           0.342     7.736    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/x1_alu_dt[24]
    SLICE_X61Y182        LUT3 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.052     7.788 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/RAM_reg_bram_8_i_5/O
                         net (fo=4, routed)           1.189     8.977    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/dmem_w_dt[24]
    RAMB36_X6Y58         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_9/DINBDIN[6]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.058    10.040    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X6Y58         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_9/CLKBWRCLK
                         clock pessimism             -0.371     9.669    
                         clock uncertainty           -0.062     9.607    
    RAMB36_X6Y58         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[6])
                                                     -0.255     9.352    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_9
  -------------------------------------------------------------------
                         required time                          9.352    
                         arrival time                          -8.977    
  -------------------------------------------------------------------
                         slack                                  0.375    

Slack (MET) :             0.379ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_dt_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_10/DINBDIN[6]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.191ns  (logic 0.810ns (19.326%)  route 3.381ns (80.674%))
  Logic Levels:           8  (CARRY8=3 LUT3=2 LUT6=2 MUXF7=1)
  Clock Path Skew:        -0.113ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.041ns = ( 10.041 - 5.000 ) 
    Source Clock Delay      (SCD):    4.783ns
    Clock Pessimism Removal (CPR):    -0.371ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.269ns (routing 1.037ns, distribution 1.232ns)
  Clock Net Delay (Destination): 2.059ns (routing 0.940ns, distribution 1.119ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.269     4.783    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_clk_i
    SLICE_X67Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_dt_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y167        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.859 f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_dt_reg[0]/Q
                         net (fo=30, routed)          0.891     5.750    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/Q[0]
    SLICE_X55Y188        LUT3 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.099     5.849 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[16]_i_22/O
                         net (fo=1, routed)           0.375     6.224    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/alu/p_0_in[0]
    SLICE_X60Y177        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.153     6.377 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[16]_i_13/CO[7]
                         net (fo=1, routed)           0.026     6.403    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[16]_i_13_n_0
    SLICE_X60Y178        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     6.418 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[16]_i_9/CO[7]
                         net (fo=1, routed)           0.026     6.444    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[16]_i_9_n_0
    SLICE_X60Y179        CARRY8 (Prop_CARRY8_SLICEM_CI_O[7])
                                                      0.116     6.560 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[30]_i_16/O[7]
                         net (fo=1, routed)           0.246     6.806    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/alu/neg_B[24]
    SLICE_X59Y182        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.146     6.952 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[24]_i_9/O
                         net (fo=1, routed)           0.010     6.962    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[24]_i_9_n_0
    SLICE_X59Y182        MUXF7 (Prop_F7MUX_CD_SLICEL_I1_O)
                                                      0.064     7.026 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[24]_i_4/O
                         net (fo=1, routed)           0.279     7.305    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[24]_i_4_n_0
    SLICE_X58Y189        LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.089     7.394 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[24]_i_1/O
                         net (fo=7, routed)           0.342     7.736    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/x1_alu_dt[24]
    SLICE_X61Y182        LUT3 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.052     7.788 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/RAM_reg_bram_8_i_5/O
                         net (fo=4, routed)           1.186     8.974    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/dmem_w_dt[24]
    RAMB36_X6Y59         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_10/DINBDIN[6]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.059    10.041    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X6Y59         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_10/CLKBWRCLK
                         clock pessimism             -0.371     9.670    
                         clock uncertainty           -0.062     9.608    
    RAMB36_X6Y59         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[6])
                                                     -0.255     9.353    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_10
  -------------------------------------------------------------------
                         required time                          9.353    
                         arrival time                          -8.974    
  -------------------------------------------------------------------
                         slack                                  0.379    

Slack (MET) :             0.380ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[10]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/WAVE_FIFO[4].wave_fifo_inst/fifo_mem/RAM_reg_0/DINADIN[10]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.336ns  (logic 0.078ns (1.799%)  route 4.258ns (98.201%))
  Logic Levels:           0  
  Clock Path Skew:        0.040ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.126ns = ( 10.126 - 5.000 ) 
    Source Clock Delay      (SCD):    4.786ns
    Clock Pessimism Removal (CPR):    -0.300ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.272ns (routing 1.037ns, distribution 1.235ns)
  Clock Net Delay (Destination): 2.144ns (routing 0.940ns, distribution 1.204ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.272     4.786    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_clk_i
    SLICE_X67Y169        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y169        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     4.864 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[10]/Q
                         net (fo=27, routed)          4.258     9.122    d_1_i/qick_processor_0/QPROC/DISPATCHER/c_fifo_time_in_r[10]
    RAMB36_X9Y26         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[4].wave_fifo_inst/fifo_mem/RAM_reg_0/DINADIN[10]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.144    10.126    d_1_i/qick_processor_0/c_clk_i
    RAMB36_X9Y26         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[4].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
                         clock pessimism             -0.300     9.826    
                         clock uncertainty           -0.062     9.764    
    RAMB36_X9Y26         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_DINADIN[10])
                                                     -0.262     9.502    d_1_i/qick_processor_0/WAVE_FIFO[4].wave_fifo_inst/fifo_mem/RAM_reg_0
  -------------------------------------------------------------------
                         required time                          9.502    
                         arrival time                          -9.122    
  -------------------------------------------------------------------
                         slack                                  0.380    

Slack (MET) :             0.398ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_dt_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/DINPBDINP[0]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.199ns  (logic 0.717ns (17.075%)  route 3.482ns (82.925%))
  Logic Levels:           9  (CARRY8=4 LUT3=2 LUT6=2 MUXF7=1)
  Clock Path Skew:        -0.096ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.058ns = ( 10.058 - 5.000 ) 
    Source Clock Delay      (SCD):    4.783ns
    Clock Pessimism Removal (CPR):    -0.371ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.269ns (routing 1.037ns, distribution 1.232ns)
  Clock Net Delay (Destination): 2.076ns (routing 0.940ns, distribution 1.136ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.269     4.783    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_clk_i
    SLICE_X67Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_dt_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y167        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.859 f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_dt_reg[0]/Q
                         net (fo=30, routed)          0.891     5.750    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/Q[0]
    SLICE_X55Y188        LUT3 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.099     5.849 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[16]_i_22/O
                         net (fo=1, routed)           0.375     6.224    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/alu/p_0_in[0]
    SLICE_X60Y177        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.153     6.377 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[16]_i_13/CO[7]
                         net (fo=1, routed)           0.026     6.403    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[16]_i_13_n_0
    SLICE_X60Y178        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     6.418 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[16]_i_9/CO[7]
                         net (fo=1, routed)           0.026     6.444    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[16]_i_9_n_0
    SLICE_X60Y179        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     6.459 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[30]_i_16/CO[7]
                         net (fo=1, routed)           0.026     6.485    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[30]_i_16_n_0
    SLICE_X60Y180        CARRY8 (Prop_CARRY8_SLICEM_CI_O[1])
                                                      0.076     6.561 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[30]_i_11/O[1]
                         net (fo=1, routed)           0.264     6.825    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/alu/neg_B[26]
    SLICE_X61Y182        LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.090     6.915 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[26]_i_9/O
                         net (fo=1, routed)           0.017     6.932    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[26]_i_9_n_0
    SLICE_X61Y182        MUXF7 (Prop_F7MUX_GH_SLICEM_I1_O)
                                                      0.067     6.999 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[26]_i_4/O
                         net (fo=1, routed)           0.244     7.243    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[26]_i_4_n_0
    SLICE_X62Y185        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.036     7.279 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[26]_i_1/O
                         net (fo=7, routed)           0.240     7.519    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/x1_alu_dt[26]
    SLICE_X61Y184        LUT3 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.090     7.609 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/RAM_reg_bram_8_i_12/O
                         net (fo=4, routed)           1.373     8.982    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/dmem_w_dt[26]
    RAMB36_X6Y60         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/DINPBDINP[0]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.076    10.058    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X6Y60         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/CLKBWRCLK
                         clock pessimism             -0.371     9.687    
                         clock uncertainty           -0.062     9.625    
    RAMB36_X6Y60         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_DINPBDINP[0])
                                                     -0.245     9.380    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11
  -------------------------------------------------------------------
                         required time                          9.380    
                         arrival time                          -8.982    
  -------------------------------------------------------------------
                         slack                                  0.398    

Slack (MET) :             0.411ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_8/WEBWE[0]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.070ns  (logic 0.517ns (12.704%)  route 3.553ns (87.296%))
  Logic Levels:           5  (LUT4=1 LUT5=3 LUT6=1)
  Clock Path Skew:        -0.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.037ns = ( 10.037 - 5.000 ) 
    Source Clock Delay      (SCD):    4.729ns
    Clock Pessimism Removal (CPR):    -0.371ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.215ns (routing 1.037ns, distribution 1.178ns)
  Clock Net Delay (Destination): 2.055ns (routing 0.940ns, distribution 1.115ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.215     4.729    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/c_clk_i
    SLICE_X72Y232        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y232        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     4.809 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[8]/Q
                         net (fo=1, routed)           0.871     5.680    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg[8]
    SLICE_X72Y139        LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.088     5.768 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg_i_3__13/O
                         net (fo=3, routed)           0.238     6.006    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg_i_3__13_n_0
    SLICE_X73Y138        LUT5 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.051     6.057 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/core_en_i_9/O
                         net (fo=4, routed)           0.643     6.700    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]
    SLICE_X77Y170        LUT5 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.123     6.823 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/core_en_i_2/O
                         net (fo=3, routed)           0.154     6.977    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER_n_303
    SLICE_X76Y169        LUT5 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     7.102 r  d_1_i/qick_processor_0/inst/QPROC/core_en/O
                         net (fo=600, routed)         1.040     8.142    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/E[0]
    SLICE_X65Y237        LUT4 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.050     8.192 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/RAM_reg_bram_8_i_14/O
                         net (fo=4, routed)           0.607     8.799    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_8_3[0]
    RAMB36_X6Y57         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_8/WEBWE[0]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.055    10.037    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X6Y57         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_8/CLKBWRCLK
                         clock pessimism             -0.371     9.666    
                         clock uncertainty           -0.062     9.604    
    RAMB36_X6Y57         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[0])
                                                     -0.394     9.210    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_8
  -------------------------------------------------------------------
                         required time                          9.210    
                         arrival time                          -8.799    
  -------------------------------------------------------------------
                         slack                                  0.411    

Slack (MET) :             0.421ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[39]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/fifo_mem/RAM_reg/DINBDIN[7]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.110ns  (logic 0.079ns (1.922%)  route 4.031ns (98.078%))
  Logic Levels:           0  
  Clock Path Skew:        -0.125ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.031ns = ( 10.031 - 5.000 ) 
    Source Clock Delay      (SCD):    4.785ns
    Clock Pessimism Removal (CPR):    -0.371ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.271ns (routing 1.037ns, distribution 1.234ns)
  Clock Net Delay (Destination): 2.049ns (routing 0.940ns, distribution 1.109ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.271     4.785    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_clk_i
    SLICE_X67Y172        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[39]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y172        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     4.864 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[39]/Q
                         net (fo=27, routed)          4.031     8.895    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/fifo_mem/data_i[39]
    RAMB36_X7Y49         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/fifo_mem/RAM_reg/DINBDIN[7]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.049    10.031    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/fifo_mem/c_clk_i
    RAMB36_X7Y49         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
                         clock pessimism             -0.371     9.660    
                         clock uncertainty           -0.062     9.598    
    RAMB36_X7Y49         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[7])
                                                     -0.282     9.316    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/fifo_mem/RAM_reg
  -------------------------------------------------------------------
                         required time                          9.316    
                         arrival time                          -8.895    
  -------------------------------------------------------------------
                         slack                                  0.421    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.022ns  (arrival time - required time)
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][22]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[0].port_dt_r_reg[0][22]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.127ns  (logic 0.058ns (45.669%)  route 0.069ns (54.331%))
  Logic Levels:           0  
  Clock Path Skew:        0.043ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.867ns
    Source Clock Delay      (SCD):    5.069ns
    Clock Pessimism Removal (CPR):    -0.245ns
  Clock Net Delay (Source):      2.087ns (routing 0.940ns, distribution 1.147ns)
  Clock Net Delay (Destination): 2.353ns (routing 1.037ns, distribution 1.316ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.087     5.069    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X50Y152        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][22]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y152        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.058     5.127 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][22]/Q
                         net (fo=1, routed)           0.069     5.196    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/s0_axis_tdata[22]
    SLICE_X50Y153        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[0].port_dt_r_reg[0][22]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.353     4.867    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/c_clk_i
    SLICE_X50Y153        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[0].port_dt_r_reg[0][22]/C
                         clock pessimism              0.245     5.112    
    SLICE_X50Y153        FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.062     5.174    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[0].port_dt_r_reg[0][22]
  -------------------------------------------------------------------
                         required time                         -5.174    
                         arrival time                           5.196    
  -------------------------------------------------------------------
                         slack                                  0.022    

Slack (MET) :             0.023ns  (arrival time - required time)
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[58]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][58]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.177ns  (logic 0.060ns (33.898%)  route 0.117ns (66.102%))
  Logic Levels:           0  
  Clock Path Skew:        0.092ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.874ns
    Source Clock Delay      (SCD):    5.076ns
    Clock Pessimism Removal (CPR):    -0.294ns
  Clock Net Delay (Source):      2.094ns (routing 0.940ns, distribution 1.154ns)
  Clock Net Delay (Destination): 2.360ns (routing 1.037ns, distribution 1.323ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.094     5.076    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X47Y147        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[58]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y147        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.060     5.136 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[58]/Q
                         net (fo=1, routed)           0.117     5.253    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[58]
    SLICE_X51Y148        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][58]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.360     4.874    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X51Y148        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][58]/C
                         clock pessimism              0.294     5.168    
    SLICE_X51Y148        FDRE (Hold_AFF2_SLICEL_C_D)
                                                      0.062     5.230    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][58]
  -------------------------------------------------------------------
                         required time                         -5.230    
                         arrival time                           5.253    
  -------------------------------------------------------------------
                         slack                                  0.023    

Slack (MET) :             0.024ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/C_dt_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_has_c.i_c3/opt_has_pipe.first_q_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.205ns  (logic 0.058ns (28.293%)  route 0.147ns (71.707%))
  Logic Levels:           0  
  Clock Path Skew:        0.119ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.814ns
    Source Clock Delay      (SCD):    4.994ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Net Delay (Source):      2.012ns (routing 0.940ns, distribution 1.072ns)
  Clock Net Delay (Destination): 2.300ns (routing 1.037ns, distribution 1.263ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.012     4.994    d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/c_clk_i
    SLICE_X61Y163        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/C_dt_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X61Y163        FDCE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     5.052 r  d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/C_dt_reg[13]/Q
                         net (fo=1, routed)           0.147     5.199    d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_has_c.i_c3/C[13]
    SLICE_X60Y162        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_has_c.i_c3/opt_has_pipe.first_q_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.300     4.814    d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_has_c.i_c3/CLK
    SLICE_X60Y162        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_has_c.i_c3/opt_has_pipe.first_q_reg[13]/C
                         clock pessimism              0.299     5.113    
    SLICE_X60Y162        FDRE (Hold_GFF2_SLICEM_C_D)
                                                      0.062     5.175    d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_has_c.i_c3/opt_has_pipe.first_q_reg[13]
  -------------------------------------------------------------------
                         required time                         -5.175    
                         arrival time                           5.199    
  -------------------------------------------------------------------
                         slack                                  0.024    

Slack (MET) :             0.024ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/reg_D_reg[0][24]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/A_dt_reg[24]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.251ns  (logic 0.058ns (23.070%)  route 0.193ns (76.930%))
  Logic Levels:           0  
  Clock Path Skew:        0.168ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.859ns
    Source Clock Delay      (SCD):    4.991ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Net Delay (Source):      2.009ns (routing 0.940ns, distribution 1.069ns)
  Clock Net Delay (Destination): 2.345ns (routing 1.037ns, distribution 1.308ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.009     4.991    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_clk_i
    SLICE_X61Y177        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/reg_D_reg[0][24]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X61Y177        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.058     5.049 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/reg_D_reg[0][24]/Q
                         net (fo=19, routed)          0.193     5.242    d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/A_dt_reg[26]_0[24]
    SLICE_X58Y171        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/A_dt_reg[24]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.345     4.859    d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/c_clk_i
    SLICE_X58Y171        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/A_dt_reg[24]/C
                         clock pessimism              0.299     5.158    
    SLICE_X58Y171        FDCE (Hold_EFF_SLICEL_C_D)
                                                      0.060     5.218    d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/A_dt_reg[24]
  -------------------------------------------------------------------
                         required time                         -5.218    
                         arrival time                           5.242    
  -------------------------------------------------------------------
                         slack                                  0.024    

Slack (MET) :             0.026ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/clear_cdc_reg/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.079ns  (logic 0.039ns (49.508%)  route 0.040ns (50.493%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.734ns
    Source Clock Delay      (SCD):    2.916ns
    Clock Pessimism Removal (CPR):    -0.188ns
  Clock Net Delay (Source):      1.230ns (routing 0.571ns, distribution 0.659ns)
  Clock Net Delay (Destination): 1.386ns (routing 0.639ns, distribution 0.747ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.230     2.916    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/c_clk_i
    SLICE_X74Y137        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y137        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.955 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.040     2.995    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/clr_fifo_req
    SLICE_X74Y137        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/clear_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.386     2.734    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X74Y137        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/clear_cdc_reg/C
                         clock pessimism              0.188     2.922    
    SLICE_X74Y137        FDCE (Hold_GFF2_SLICEL_C_D)
                                                      0.047     2.969    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/clear_cdc_reg
  -------------------------------------------------------------------
                         required time                         -2.969    
                         arrival time                           2.995    
  -------------------------------------------------------------------
                         slack                                  0.026    

Slack (MET) :             0.029ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_id_imm_addr_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_addr_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.129ns  (logic 0.060ns (46.512%)  route 0.069ns (53.488%))
  Logic Levels:           0  
  Clock Path Skew:        0.038ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.765ns
    Source Clock Delay      (SCD):    4.981ns
    Clock Pessimism Removal (CPR):    -0.255ns
  Clock Net Delay (Source):      1.999ns (routing 0.940ns, distribution 1.059ns)
  Clock Net Delay (Destination): 2.251ns (routing 1.037ns, distribution 1.214ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.999     4.981    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_clk_i
    SLICE_X68Y163        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_id_imm_addr_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y163        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.060     5.041 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_id_imm_addr_reg[7]/Q
                         net (fo=1, routed)           0.069     5.110    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_id_imm_addr[7]
    SLICE_X68Y165        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_addr_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.251     4.765    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_clk_i
    SLICE_X68Y165        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_addr_reg[7]/C
                         clock pessimism              0.255     5.020    
    SLICE_X68Y165        FDRE (Hold_AFF2_SLICEL_C_D)
                                                      0.062     5.082    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_addr_reg[7]
  -------------------------------------------------------------------
                         required time                         -5.082    
                         arrival time                           5.110    
  -------------------------------------------------------------------
                         slack                                  0.029    

Slack (MET) :             0.029ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_has_c.i_c3/opt_has_pipe.first_q_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_c4/opt_has_pipe.first_q_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.081ns  (logic 0.039ns (48.148%)  route 0.042ns (51.852%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.744ns
    Source Clock Delay      (SCD):    2.927ns
    Clock Pessimism Removal (CPR):    -0.188ns
  Clock Net Delay (Source):      1.241ns (routing 0.571ns, distribution 0.670ns)
  Clock Net Delay (Destination): 1.396ns (routing 0.639ns, distribution 0.757ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.241     2.927    d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_has_c.i_c3/CLK
    SLICE_X64Y160        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_has_c.i_c3/opt_has_pipe.first_q_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y160        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     2.966 r  d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_has_c.i_c3/opt_has_pipe.first_q_reg[6]/Q
                         net (fo=1, routed)           0.042     3.008    d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_c4/opt_has_pipe.first_q_reg[6]_0
    SLICE_X64Y160        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_c4/opt_has_pipe.first_q_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.396     2.744    d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_c4/CLK
    SLICE_X64Y160        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_c4/opt_has_pipe.first_q_reg[6]/C
                         clock pessimism              0.188     2.933    
    SLICE_X64Y160        FDRE (Hold_EFF_SLICEL_C_D)
                                                      0.046     2.979    d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_c4/opt_has_pipe.first_q_reg[6]
  -------------------------------------------------------------------
                         required time                         -2.979    
                         arrival time                           3.008    
  -------------------------------------------------------------------
                         slack                                  0.029    

Slack (MET) :             0.029ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[3].port_dt_r_reg[3][50]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/in_port_dt_r_reg[50]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.183ns  (logic 0.080ns (43.716%)  route 0.103ns (56.284%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.094ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.848ns
    Source Clock Delay      (SCD):    5.048ns
    Clock Pessimism Removal (CPR):    -0.293ns
  Clock Net Delay (Source):      2.066ns (routing 0.940ns, distribution 1.126ns)
  Clock Net Delay (Destination): 2.334ns (routing 1.037ns, distribution 1.297ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.066     5.048    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/c_clk_i
    SLICE_X54Y142        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[3].port_dt_r_reg[3][50]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y142        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     5.106 r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[3].port_dt_r_reg[3][50]/Q
                         net (fo=1, routed)           0.074     5.180    d_1_i/qick_processor_0/inst/QPROC/CORE_0/in_port_dt_r_reg[63]_2[50]
    SLICE_X53Y143        LUT6 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.022     5.202 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/in_port_dt_r[50]_i_1/O
                         net (fo=1, routed)           0.029     5.231    d_1_i/qick_processor_0/inst/QPROC/CORE_0/p_0_in_0[50]
    SLICE_X53Y143        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/in_port_dt_r_reg[50]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.334     4.848    d_1_i/qick_processor_0/inst/QPROC/CORE_0/c_clk_i
    SLICE_X53Y143        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/in_port_dt_r_reg[50]/C
                         clock pessimism              0.293     5.142    
    SLICE_X53Y143        FDRE (Hold_BFF_SLICEM_C_D)
                                                      0.060     5.202    d_1_i/qick_processor_0/inst/QPROC/CORE_0/in_port_dt_r_reg[50]
  -------------------------------------------------------------------
                         required time                         -5.202    
                         arrival time                           5.231    
  -------------------------------------------------------------------
                         slack                                  0.029    

Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[45]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][45]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.177ns  (logic 0.059ns (33.333%)  route 0.118ns (66.667%))
  Logic Levels:           0  
  Clock Path Skew:        0.087ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.865ns
    Source Clock Delay      (SCD):    5.072ns
    Clock Pessimism Removal (CPR):    -0.294ns
  Clock Net Delay (Source):      2.090ns (routing 0.940ns, distribution 1.150ns)
  Clock Net Delay (Destination): 2.351ns (routing 1.037ns, distribution 1.314ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.090     5.072    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X47Y152        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[45]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y152        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     5.131 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[45]/Q
                         net (fo=1, routed)           0.118     5.249    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[45]
    SLICE_X50Y152        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][45]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.351     4.865    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X50Y152        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][45]/C
                         clock pessimism              0.294     5.159    
    SLICE_X50Y152        FDRE (Hold_HFF_SLICEL_C_D)
                                                      0.060     5.219    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][45]
  -------------------------------------------------------------------
                         required time                         -5.219    
                         arrival time                           5.249    
  -------------------------------------------------------------------
                         slack                                  0.030    

Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][57]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[2].port_dt_r_reg[2][57]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.059ns (30.729%)  route 0.133ns (69.271%))
  Logic Levels:           0  
  Clock Path Skew:        0.102ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.870ns
    Source Clock Delay      (SCD):    5.062ns
    Clock Pessimism Removal (CPR):    -0.294ns
  Clock Net Delay (Source):      2.080ns (routing 0.940ns, distribution 1.140ns)
  Clock Net Delay (Destination): 2.356ns (routing 1.037ns, distribution 1.319ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.080     5.062    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X58Y122        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][57]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y122        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.059     5.121 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][57]/Q
                         net (fo=1, routed)           0.133     5.254    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/s2_axis_tdata[57]
    SLICE_X56Y124        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[2].port_dt_r_reg[2][57]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.356     4.870    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/c_clk_i
    SLICE_X56Y124        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[2].port_dt_r_reg[2][57]/C
                         clock pessimism              0.294     5.164    
    SLICE_X56Y124        FDRE (Hold_HFF_SLICEM_C_D)
                                                      0.060     5.224    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[2].port_dt_r_reg[2][57]
  -------------------------------------------------------------------
                         required time                         -5.224    
                         arrival time                           5.254    
  -------------------------------------------------------------------
                         slack                                  0.030    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out1_d_1_clk_core_0
Waveform(ns):       { 0.000 2.500 }
Period(ns):         5.000
Sources:            { d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X5Y34  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X5Y35  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X6Y59  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_10/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X6Y60  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X6Y41  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_12/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X6Y42  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_13/CLKBWRCLK
Min Period        n/a     RAMB18E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB18_X6Y86  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_14/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X5Y36  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X5Y37  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X5Y38  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X9Y35  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X9Y35  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X9Y34  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X9Y34  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X9Y30  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X9Y30  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X8Y26  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X8Y26  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X9Y28  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X9Y28  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X9Y35  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X9Y35  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X9Y34  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X9Y34  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X9Y30  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X9Y30  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X8Y26  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X8Y26  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X9Y28  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X9Y28  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK



---------------------------------------------------------------------------------------------------
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Setup :            0  Failing Endpoints,  Worst Slack       11.071ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.032ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack       24.468ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             11.071ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDO_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDO
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        2.833ns  (logic 0.239ns (8.436%)  route 2.594ns (91.564%))
  Logic Levels:           2  (LUT3=1 LUT6=1)
  Clock Path Skew:        -10.861ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.000ns = ( 25.000 - 25.000 ) 
    Source Clock Delay      (SCD):    10.861ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      2.926ns (routing 1.680ns, distribution 1.246ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.926    10.861    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/m_bscan_tck[0]
    SLICE_X103Y287       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDO_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y287       FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079    10.940 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDO_reg/Q
                         net (fo=1, routed)           1.667    12.607    dbg_hub/inst/BSCANID.u_xsdbm_id/TDO
    SLICE_X107Y96        LUT3 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.124    12.731 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch_i_1/O
                         net (fo=2, routed)           0.450    13.181    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_tdo[0]
    SLICE_X108Y96        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.036    13.217 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdo_INST_0/O
                         net (fo=1, routed)           0.477    13.694    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TDO
    CONFIG_SITE_X0Y0     BSCANE2                                      r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDO
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                         clock pessimism              0.000    25.000    
                         clock uncertainty           -0.235    24.765    
    CONFIG_SITE_X0Y0     BSCANE2 (Setup_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TDO)
                                                      0.000    24.765    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst
  -------------------------------------------------------------------
                         required time                         24.765    
                         arrival time                         -13.694    
  -------------------------------------------------------------------
                         slack                                 11.071    

Slack (MET) :             21.384ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        7.289ns  (logic 5.273ns (72.345%)  route 2.016ns (27.655%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.953ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.953ns = ( 53.953 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.603ns (routing 0.916ns, distribution 0.687ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.440    30.540    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X109Y98        LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.061    30.601 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.342    31.944    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X104Y287       LUT4 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.060    32.004 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.103    32.107    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X104Y287       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.052    32.159 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.130    32.289    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X103Y287       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868    52.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.603    53.953    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X103Y287       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]/C
                         clock pessimism              0.000    53.953    
                         clock uncertainty           -0.235    53.717    
    SLICE_X103Y287       FDRE (Setup_BFF2_SLICEM_C_R)
                                                     -0.044    53.673    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]
  -------------------------------------------------------------------
                         required time                         53.673    
                         arrival time                         -32.289    
  -------------------------------------------------------------------
                         slack                                 21.384    

Slack (MET) :             21.384ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        7.289ns  (logic 5.273ns (72.345%)  route 2.016ns (27.655%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.953ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.953ns = ( 53.953 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.603ns (routing 0.916ns, distribution 0.687ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.440    30.540    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X109Y98        LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.061    30.601 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.342    31.944    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X104Y287       LUT4 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.060    32.004 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.103    32.107    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X104Y287       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.052    32.159 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.130    32.289    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X103Y287       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868    52.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.603    53.953    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X103Y287       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]/C
                         clock pessimism              0.000    53.953    
                         clock uncertainty           -0.235    53.717    
    SLICE_X103Y287       FDRE (Setup_DFF_SLICEM_C_R)
                                                     -0.044    53.673    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]
  -------------------------------------------------------------------
                         required time                         53.673    
                         arrival time                         -32.289    
  -------------------------------------------------------------------
                         slack                                 21.384    

Slack (MET) :             21.384ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        7.289ns  (logic 5.273ns (72.345%)  route 2.016ns (27.655%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.953ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.953ns = ( 53.953 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.603ns (routing 0.916ns, distribution 0.687ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.440    30.540    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X109Y98        LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.061    30.601 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.342    31.944    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X104Y287       LUT4 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.060    32.004 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.103    32.107    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X104Y287       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.052    32.159 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.130    32.289    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X103Y287       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868    52.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.603    53.953    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X103Y287       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]/C
                         clock pessimism              0.000    53.953    
                         clock uncertainty           -0.235    53.717    
    SLICE_X103Y287       FDRE (Setup_DFF2_SLICEM_C_R)
                                                     -0.044    53.673    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]
  -------------------------------------------------------------------
                         required time                         53.673    
                         arrival time                         -32.289    
  -------------------------------------------------------------------
                         slack                                 21.384    

Slack (MET) :             21.384ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[3]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        7.289ns  (logic 5.273ns (72.345%)  route 2.016ns (27.655%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.953ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.953ns = ( 53.953 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.603ns (routing 0.916ns, distribution 0.687ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.440    30.540    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X109Y98        LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.061    30.601 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.342    31.944    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X104Y287       LUT4 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.060    32.004 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.103    32.107    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X104Y287       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.052    32.159 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.130    32.289    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X103Y287       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[3]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868    52.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.603    53.953    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X103Y287       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[3]/C
                         clock pessimism              0.000    53.953    
                         clock uncertainty           -0.235    53.717    
    SLICE_X103Y287       FDRE (Setup_CFF_SLICEM_C_R)
                                                     -0.044    53.673    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[3]
  -------------------------------------------------------------------
                         required time                         53.673    
                         arrival time                         -32.289    
  -------------------------------------------------------------------
                         slack                                 21.384    

Slack (MET) :             21.384ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[4]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        7.289ns  (logic 5.273ns (72.345%)  route 2.016ns (27.655%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.953ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.953ns = ( 53.953 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.603ns (routing 0.916ns, distribution 0.687ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.440    30.540    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X109Y98        LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.061    30.601 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.342    31.944    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X104Y287       LUT4 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.060    32.004 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.103    32.107    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X104Y287       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.052    32.159 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.130    32.289    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X103Y287       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[4]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868    52.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.603    53.953    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X103Y287       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[4]/C
                         clock pessimism              0.000    53.953    
                         clock uncertainty           -0.235    53.717    
    SLICE_X103Y287       FDRE (Setup_CFF2_SLICEM_C_R)
                                                     -0.044    53.673    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[4]
  -------------------------------------------------------------------
                         required time                         53.673    
                         arrival time                         -32.289    
  -------------------------------------------------------------------
                         slack                                 21.384    

Slack (MET) :             21.384ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[5]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        7.289ns  (logic 5.273ns (72.345%)  route 2.016ns (27.655%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.953ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.953ns = ( 53.953 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.603ns (routing 0.916ns, distribution 0.687ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.440    30.540    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X109Y98        LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.061    30.601 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.342    31.944    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X104Y287       LUT4 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.060    32.004 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.103    32.107    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X104Y287       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.052    32.159 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.130    32.289    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X103Y287       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[5]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868    52.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.603    53.953    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X103Y287       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[5]/C
                         clock pessimism              0.000    53.953    
                         clock uncertainty           -0.235    53.717    
    SLICE_X103Y287       FDRE (Setup_AFF_SLICEM_C_R)
                                                     -0.044    53.673    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[5]
  -------------------------------------------------------------------
                         required time                         53.673    
                         arrival time                         -32.289    
  -------------------------------------------------------------------
                         slack                                 21.384    

Slack (MET) :             21.461ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        7.211ns  (logic 5.222ns (72.420%)  route 1.989ns (27.580%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        3.952ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.952ns = ( 53.952 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.602ns (routing 0.916ns, distribution 0.686ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.440    30.540    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X109Y98        LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.061    30.601 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.343    31.945    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[0]_0
    SLICE_X104Y287       LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.061    32.006 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en[3]_i_1/O
                         net (fo=4, routed)           0.205    32.211    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en[3]_i_1_n_0
    SLICE_X104Y289       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868    52.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.602    53.952    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X104Y289       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[0]/C
                         clock pessimism              0.000    53.952    
                         clock uncertainty           -0.235    53.716    
    SLICE_X104Y289       FDRE (Setup_EFF_SLICEM_C_R)
                                                     -0.044    53.672    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[0]
  -------------------------------------------------------------------
                         required time                         53.672    
                         arrival time                         -32.211    
  -------------------------------------------------------------------
                         slack                                 21.461    

Slack (MET) :             21.461ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        7.211ns  (logic 5.222ns (72.420%)  route 1.989ns (27.580%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        3.952ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.952ns = ( 53.952 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.602ns (routing 0.916ns, distribution 0.686ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.440    30.540    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X109Y98        LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.061    30.601 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.343    31.945    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[0]_0
    SLICE_X104Y287       LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.061    32.006 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en[3]_i_1/O
                         net (fo=4, routed)           0.205    32.211    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en[3]_i_1_n_0
    SLICE_X104Y289       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[1]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868    52.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.602    53.952    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X104Y289       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[1]/C
                         clock pessimism              0.000    53.952    
                         clock uncertainty           -0.235    53.716    
    SLICE_X104Y289       FDRE (Setup_EFF2_SLICEM_C_R)
                                                     -0.044    53.672    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[1]
  -------------------------------------------------------------------
                         required time                         53.672    
                         arrival time                         -32.211    
  -------------------------------------------------------------------
                         slack                                 21.461    

Slack (MET) :             21.461ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        7.211ns  (logic 5.222ns (72.420%)  route 1.989ns (27.580%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        3.952ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.952ns = ( 53.952 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.602ns (routing 0.916ns, distribution 0.686ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.440    30.540    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X109Y98        LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.061    30.601 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.343    31.945    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[0]_0
    SLICE_X104Y287       LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.061    32.006 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en[3]_i_1/O
                         net (fo=4, routed)           0.205    32.211    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en[3]_i_1_n_0
    SLICE_X104Y289       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868    52.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.602    53.952    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X104Y289       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[2]/C
                         clock pessimism              0.000    53.952    
                         clock uncertainty           -0.235    53.716    
    SLICE_X104Y289       FDRE (Setup_FFF_SLICEM_C_R)
                                                     -0.044    53.672    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[2]
  -------------------------------------------------------------------
                         required time                         53.672    
                         arrival time                         -32.211    
  -------------------------------------------------------------------
                         slack                                 21.461    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.084ns  (logic 0.039ns (46.605%)  route 0.045ns (53.396%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.592ns
    Source Clock Delay      (SCD):    3.968ns
    Clock Pessimism Removal (CPR):    4.618ns
  Clock Net Delay (Source):      1.618ns (routing 0.916ns, distribution 0.702ns)
  Clock Net Delay (Destination): 1.821ns (routing 1.028ns, distribution 0.793ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.618     3.968    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y301       FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     4.007 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[5]/Q
                         net (fo=2, routed)           0.045     4.052    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[5]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.821     8.592    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[4]/C
                         clock pessimism             -4.618     3.974    
    SLICE_X101Y301       FDRE (Hold_CFF_SLICEL_C_D)
                                                      0.046     4.020    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[4]
  -------------------------------------------------------------------
                         required time                         -4.020    
                         arrival time                           4.052    
  -------------------------------------------------------------------
                         slack                                  0.032    

Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid_reg[27]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid_reg[26]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.085ns  (logic 0.039ns (46.054%)  route 0.046ns (53.946%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.555ns
    Source Clock Delay      (SCD):    3.932ns
    Clock Pessimism Removal (CPR):    4.618ns
  Clock Net Delay (Source):      1.582ns (routing 0.916ns, distribution 0.666ns)
  Clock Net Delay (Destination): 1.784ns (routing 1.028ns, distribution 0.756ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.582     3.932    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X109Y92        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid_reg[27]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y92        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.971 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid_reg[27]/Q
                         net (fo=2, routed)           0.046     4.016    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[27]
    SLICE_X109Y92        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid_reg[26]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.784     8.555    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X109Y92        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid_reg[26]/C
                         clock pessimism             -4.618     3.938    
    SLICE_X109Y92        FDRE (Hold_CFF2_SLICEM_C_D)
                                                      0.047     3.985    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid_reg[26]
  -------------------------------------------------------------------
                         required time                         -3.985    
                         arrival time                           4.016    
  -------------------------------------------------------------------
                         slack                                  0.032    

Slack (MET) :             0.034ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[14]/CE
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.203ns  (logic 0.061ns (29.999%)  route 0.142ns (70.001%))
  Logic Levels:           0  
  Clock Path Skew:        0.182ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    10.902ns
    Source Clock Delay      (SCD):    5.458ns
    Clock Pessimism Removal (CPR):    5.262ns
  Clock Net Delay (Source):      2.622ns (routing 1.525ns, distribution 1.097ns)
  Clock Net Delay (Destination): 2.967ns (routing 1.680ns, distribution 1.287ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.622     5.458    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y298       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y298       FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     5.519 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/Q
                         net (fo=19, routed)          0.142     5.661    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[14]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.967    10.902    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[14]/C
                         clock pessimism             -5.262     5.640    
    SLICE_X101Y301       FDRE (Hold_EFF2_SLICEL_C_CE)
                                                     -0.013     5.627    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[14]
  -------------------------------------------------------------------
                         required time                         -5.627    
                         arrival time                           5.661    
  -------------------------------------------------------------------
                         slack                                  0.034    

Slack (MET) :             0.034ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[15]/CE
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.203ns  (logic 0.061ns (29.999%)  route 0.142ns (70.001%))
  Logic Levels:           0  
  Clock Path Skew:        0.182ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    10.902ns
    Source Clock Delay      (SCD):    5.458ns
    Clock Pessimism Removal (CPR):    5.262ns
  Clock Net Delay (Source):      2.622ns (routing 1.525ns, distribution 1.097ns)
  Clock Net Delay (Destination): 2.967ns (routing 1.680ns, distribution 1.287ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.622     5.458    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y298       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y298       FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     5.519 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/Q
                         net (fo=19, routed)          0.142     5.661    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[15]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.967    10.902    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[15]/C
                         clock pessimism             -5.262     5.640    
    SLICE_X101Y301       FDRE (Hold_FFF2_SLICEL_C_CE)
                                                     -0.013     5.627    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[15]
  -------------------------------------------------------------------
                         required time                         -5.627    
                         arrival time                           5.661    
  -------------------------------------------------------------------
                         slack                                  0.034    

Slack (MET) :             0.034ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[16]/CE
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.203ns  (logic 0.061ns (29.999%)  route 0.142ns (70.001%))
  Logic Levels:           0  
  Clock Path Skew:        0.182ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    10.902ns
    Source Clock Delay      (SCD):    5.458ns
    Clock Pessimism Removal (CPR):    5.262ns
  Clock Net Delay (Source):      2.622ns (routing 1.525ns, distribution 1.097ns)
  Clock Net Delay (Destination): 2.967ns (routing 1.680ns, distribution 1.287ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.622     5.458    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y298       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y298       FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     5.519 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/Q
                         net (fo=19, routed)          0.142     5.661    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[16]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.967    10.902    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[16]/C
                         clock pessimism             -5.262     5.640    
    SLICE_X101Y301       FDRE (Hold_GFF2_SLICEL_C_CE)
                                                     -0.013     5.627    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[16]
  -------------------------------------------------------------------
                         required time                         -5.627    
                         arrival time                           5.661    
  -------------------------------------------------------------------
                         slack                                  0.034    

Slack (MET) :             0.034ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]/CE
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.203ns  (logic 0.061ns (29.999%)  route 0.142ns (70.001%))
  Logic Levels:           0  
  Clock Path Skew:        0.182ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    10.902ns
    Source Clock Delay      (SCD):    5.458ns
    Clock Pessimism Removal (CPR):    5.262ns
  Clock Net Delay (Source):      2.622ns (routing 1.525ns, distribution 1.097ns)
  Clock Net Delay (Destination): 2.967ns (routing 1.680ns, distribution 1.287ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.622     5.458    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y298       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y298       FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     5.519 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/Q
                         net (fo=19, routed)          0.142     5.661    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.967    10.902    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]/C
                         clock pessimism             -5.262     5.640    
    SLICE_X101Y301       FDRE (Hold_HFF2_SLICEL_C_CE)
                                                     -0.013     5.627    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]
  -------------------------------------------------------------------
                         required time                         -5.627    
                         arrival time                           5.661    
  -------------------------------------------------------------------
                         slack                                  0.034    

Slack (MET) :             0.034ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[6]/CE
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.202ns  (logic 0.061ns (30.147%)  route 0.141ns (69.853%))
  Logic Levels:           0  
  Clock Path Skew:        0.182ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    10.902ns
    Source Clock Delay      (SCD):    5.458ns
    Clock Pessimism Removal (CPR):    5.262ns
  Clock Net Delay (Source):      2.622ns (routing 1.525ns, distribution 1.097ns)
  Clock Net Delay (Destination): 2.967ns (routing 1.680ns, distribution 1.287ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.622     5.458    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y298       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y298       FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     5.519 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/Q
                         net (fo=19, routed)          0.141     5.660    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[6]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.967    10.902    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[6]/C
                         clock pessimism             -5.262     5.640    
    SLICE_X101Y301       FDRE (Hold_EFF_SLICEL_C_CE)
                                                     -0.014     5.626    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[6]
  -------------------------------------------------------------------
                         required time                         -5.626    
                         arrival time                           5.660    
  -------------------------------------------------------------------
                         slack                                  0.034    

Slack (MET) :             0.034ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/CE
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.202ns  (logic 0.061ns (30.147%)  route 0.141ns (69.853%))
  Logic Levels:           0  
  Clock Path Skew:        0.182ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    10.902ns
    Source Clock Delay      (SCD):    5.458ns
    Clock Pessimism Removal (CPR):    5.262ns
  Clock Net Delay (Source):      2.622ns (routing 1.525ns, distribution 1.097ns)
  Clock Net Delay (Destination): 2.967ns (routing 1.680ns, distribution 1.287ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.622     5.458    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y298       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y298       FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     5.519 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/Q
                         net (fo=19, routed)          0.141     5.660    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.967    10.902    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/C
                         clock pessimism             -5.262     5.640    
    SLICE_X101Y301       FDRE (Hold_FFF_SLICEL_C_CE)
                                                     -0.014     5.626    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]
  -------------------------------------------------------------------
                         required time                         -5.626    
                         arrival time                           5.660    
  -------------------------------------------------------------------
                         slack                                  0.034    

Slack (MET) :             0.034ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[8]/CE
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.202ns  (logic 0.061ns (30.147%)  route 0.141ns (69.853%))
  Logic Levels:           0  
  Clock Path Skew:        0.182ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    10.902ns
    Source Clock Delay      (SCD):    5.458ns
    Clock Pessimism Removal (CPR):    5.262ns
  Clock Net Delay (Source):      2.622ns (routing 1.525ns, distribution 1.097ns)
  Clock Net Delay (Destination): 2.967ns (routing 1.680ns, distribution 1.287ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.622     5.458    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y298       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y298       FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     5.519 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/Q
                         net (fo=19, routed)          0.141     5.660    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[8]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.967    10.902    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[8]/C
                         clock pessimism             -5.262     5.640    
    SLICE_X101Y301       FDRE (Hold_GFF_SLICEL_C_CE)
                                                     -0.014     5.626    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[8]
  -------------------------------------------------------------------
                         required time                         -5.626    
                         arrival time                           5.660    
  -------------------------------------------------------------------
                         slack                                  0.034    

Slack (MET) :             0.034ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[9]/CE
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.202ns  (logic 0.061ns (30.147%)  route 0.141ns (69.853%))
  Logic Levels:           0  
  Clock Path Skew:        0.182ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    10.902ns
    Source Clock Delay      (SCD):    5.458ns
    Clock Pessimism Removal (CPR):    5.262ns
  Clock Net Delay (Source):      2.622ns (routing 1.525ns, distribution 1.097ns)
  Clock Net Delay (Destination): 2.967ns (routing 1.680ns, distribution 1.287ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.622     5.458    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y298       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y298       FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     5.519 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/Q
                         net (fo=19, routed)          0.141     5.660    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[9]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.967    10.902    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[9]/C
                         clock pessimism             -5.262     5.640    
    SLICE_X101Y301       FDRE (Hold_HFF_SLICEL_C_CE)
                                                     -0.014     5.626    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[9]
  -------------------------------------------------------------------
                         required time                         -5.626    
                         arrival time                           5.660    
  -------------------------------------------------------------------
                         slack                                  0.034    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
Waveform(ns):       { 0.000 25.000 }
Period(ns):         50.000
Sources:            { dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK }

Check Type        Corner  Lib Pin     Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     BUFGCE/I    n/a            1.290         50.000      48.710     BUFGCE_X0Y181  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/I
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAME/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y296  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK



---------------------------------------------------------------------------------------------------
From Clock:  sys_clk_ddr4_clk_p
  To Clock:  sys_clk_ddr4_clk_p

Setup :            0  Failing Endpoints,  Worst Slack        1.760ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.054ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.500ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.760ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.479ns  (logic 0.354ns (23.932%)  route 1.125ns (76.068%))
  Logic Levels:           2  (LUT3=1 LUT5=1)
  Clock Path Skew:        -0.085ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.903ns = ( 5.237 - 3.334 ) 
    Source Clock Delay      (SCD):    2.229ns
    Clock Pessimism Removal (CPR):    0.241ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.143ns (routing 0.171ns, distribution 0.972ns)
  Clock Net Delay (Destination): 0.988ns (routing 0.155ns, distribution 0.833ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.143     2.229    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y340        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y340        FDSE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.310 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/Q
                         net (fo=7, routed)           0.597     2.907    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[5]
    SLICE_X81Y340        LUT3 (Prop_C5LUT_SLICEL_I0_O)
                                                      0.136     3.043 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_i_2/O
                         net (fo=1, routed)           0.125     3.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_i_2_n_0
    SLICE_X82Y340        LUT5 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.137     3.305 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_i_1/O
                         net (fo=1, routed)           0.403     3.708    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_i_1_n_0
    SLICE_X82Y331        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.988     5.237    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X82Y331        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_reg/C
                         clock pessimism              0.241     5.478    
                         clock uncertainty           -0.035     5.443    
    SLICE_X82Y331        FDRE (Setup_EFF_SLICEM_C_D)
                                                      0.025     5.468    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_reg
  -------------------------------------------------------------------
                         required time                          5.468    
                         arrival time                          -3.708    
  -------------------------------------------------------------------
                         slack                                  1.760    

Slack (MET) :             1.859ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.396ns  (logic 0.178ns (12.748%)  route 1.218ns (87.252%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.068ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.920ns = ( 5.254 - 3.334 ) 
    Source Clock Delay      (SCD):    2.229ns
    Clock Pessimism Removal (CPR):    0.241ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.143ns (routing 0.171ns, distribution 0.972ns)
  Clock Net Delay (Destination): 1.005ns (routing 0.155ns, distribution 0.850ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.143     2.229    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y340        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y340        FDSE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     2.308 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/Q
                         net (fo=5, routed)           1.146     3.454    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]
    SLICE_X82Y340        LUT3 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.099     3.553 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]_i_1/O
                         net (fo=1, routed)           0.072     3.625    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst0[2]
    SLICE_X82Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.005     5.254    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X82Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                         clock pessimism              0.241     5.495    
                         clock uncertainty           -0.035     5.460    
    SLICE_X82Y340        FDRE (Setup_DFF_SLICEM_C_D)
                                                      0.025     5.485    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]
  -------------------------------------------------------------------
                         required time                          5.485    
                         arrival time                          -3.625    
  -------------------------------------------------------------------
                         slack                                  1.859    

Slack (MET) :             1.890ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.365ns  (logic 0.189ns (13.843%)  route 1.176ns (86.157%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.068ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.920ns = ( 5.254 - 3.334 ) 
    Source Clock Delay      (SCD):    2.229ns
    Clock Pessimism Removal (CPR):    0.241ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.143ns (routing 0.171ns, distribution 0.972ns)
  Clock Net Delay (Destination): 1.005ns (routing 0.155ns, distribution 0.850ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.143     2.229    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y340        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y340        FDSE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     2.308 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/Q
                         net (fo=5, routed)           1.146     3.454    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]
    SLICE_X82Y340        LUT4 (Prop_D5LUT_SLICEM_I0_O)
                                                      0.110     3.564 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[3]_i_1/O
                         net (fo=1, routed)           0.030     3.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst0[3]
    SLICE_X82Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.005     5.254    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X82Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                         clock pessimism              0.241     5.495    
                         clock uncertainty           -0.035     5.460    
    SLICE_X82Y340        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     5.485    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]
  -------------------------------------------------------------------
                         required time                          5.485    
                         arrival time                          -3.594    
  -------------------------------------------------------------------
                         slack                                  1.890    

Slack (MET) :             1.934ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.238ns  (logic 0.205ns (16.561%)  route 1.033ns (83.439%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.053ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.920ns = ( 5.254 - 3.334 ) 
    Source Clock Delay      (SCD):    2.214ns
    Clock Pessimism Removal (CPR):    0.241ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.128ns (routing 0.171ns, distribution 0.957ns)
  Clock Net Delay (Destination): 1.005ns (routing 0.155ns, distribution 0.850ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.128     2.214    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y337        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.295 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/Q
                         net (fo=4, routed)           0.728     3.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[3]
    SLICE_X81Y340        LUT5 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.124     3.146 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.305     3.452    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X82Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.005     5.254    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X82Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
                         clock pessimism              0.241     5.495    
                         clock uncertainty           -0.035     5.460    
    SLICE_X82Y340        FDRE (Setup_BFF2_SLICEM_C_R)
                                                     -0.074     5.386    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]
  -------------------------------------------------------------------
                         required time                          5.386    
                         arrival time                          -3.452    
  -------------------------------------------------------------------
                         slack                                  1.934    

Slack (MET) :             1.934ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.238ns  (logic 0.205ns (16.561%)  route 1.033ns (83.439%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.053ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.920ns = ( 5.254 - 3.334 ) 
    Source Clock Delay      (SCD):    2.214ns
    Clock Pessimism Removal (CPR):    0.241ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.128ns (routing 0.171ns, distribution 0.957ns)
  Clock Net Delay (Destination): 1.005ns (routing 0.155ns, distribution 0.850ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.128     2.214    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y337        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.295 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/Q
                         net (fo=4, routed)           0.728     3.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[3]
    SLICE_X81Y340        LUT5 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.124     3.146 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.305     3.452    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X82Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.005     5.254    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X82Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                         clock pessimism              0.241     5.495    
                         clock uncertainty           -0.035     5.460    
    SLICE_X82Y340        FDRE (Setup_DFF_SLICEM_C_R)
                                                     -0.074     5.386    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]
  -------------------------------------------------------------------
                         required time                          5.386    
                         arrival time                          -3.452    
  -------------------------------------------------------------------
                         slack                                  1.934    

Slack (MET) :             1.934ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/R
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.238ns  (logic 0.205ns (16.561%)  route 1.033ns (83.439%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.053ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.920ns = ( 5.254 - 3.334 ) 
    Source Clock Delay      (SCD):    2.214ns
    Clock Pessimism Removal (CPR):    0.241ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.128ns (routing 0.171ns, distribution 0.957ns)
  Clock Net Delay (Destination): 1.005ns (routing 0.155ns, distribution 0.850ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.128     2.214    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y337        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.295 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/Q
                         net (fo=4, routed)           0.728     3.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[3]
    SLICE_X81Y340        LUT5 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.124     3.146 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.305     3.452    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X82Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/R
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.005     5.254    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X82Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                         clock pessimism              0.241     5.495    
                         clock uncertainty           -0.035     5.460    
    SLICE_X82Y340        FDRE (Setup_DFF2_SLICEM_C_R)
                                                     -0.074     5.386    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]
  -------------------------------------------------------------------
                         required time                          5.386    
                         arrival time                          -3.452    
  -------------------------------------------------------------------
                         slack                                  1.934    

Slack (MET) :             1.936ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/R
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.235ns  (logic 0.205ns (16.601%)  route 1.030ns (83.399%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.054ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.919ns = ( 5.253 - 3.334 ) 
    Source Clock Delay      (SCD):    2.214ns
    Clock Pessimism Removal (CPR):    0.241ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.128ns (routing 0.171ns, distribution 0.957ns)
  Clock Net Delay (Destination): 1.004ns (routing 0.155ns, distribution 0.849ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.128     2.214    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y337        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.295 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/Q
                         net (fo=4, routed)           0.728     3.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[3]
    SLICE_X81Y340        LUT5 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.124     3.146 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.302     3.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X82Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/R
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.004     5.253    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X82Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
                         clock pessimism              0.241     5.494    
                         clock uncertainty           -0.035     5.459    
    SLICE_X82Y340        FDRE (Setup_EFF_SLICEM_C_R)
                                                     -0.074     5.385    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]
  -------------------------------------------------------------------
                         required time                          5.385    
                         arrival time                          -3.449    
  -------------------------------------------------------------------
                         slack                                  1.936    

Slack (MET) :             2.123ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/S
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.085ns  (logic 0.081ns (7.469%)  route 1.004ns (92.531%))
  Logic Levels:           0  
  Clock Path Skew:        -0.017ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.909ns = ( 5.243 - 3.334 ) 
    Source Clock Delay      (SCD):    2.214ns
    Clock Pessimism Removal (CPR):    0.288ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.128ns (routing 0.171ns, distribution 0.957ns)
  Clock Net Delay (Destination): 0.994ns (routing 0.155ns, distribution 0.839ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.128     2.214    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y337        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.295 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/Q
                         net (fo=4, routed)           1.004     3.298    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[3]
    SLICE_X81Y340        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/S
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.994     5.243    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y340        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                         clock pessimism              0.288     5.531    
                         clock uncertainty           -0.035     5.496    
    SLICE_X81Y340        FDSE (Setup_BFF_SLICEL_C_S)
                                                     -0.074     5.422    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]
  -------------------------------------------------------------------
                         required time                          5.422    
                         arrival time                          -3.298    
  -------------------------------------------------------------------
                         slack                                  2.123    

Slack (MET) :             2.123ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/S
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.085ns  (logic 0.081ns (7.469%)  route 1.004ns (92.531%))
  Logic Levels:           0  
  Clock Path Skew:        -0.017ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.909ns = ( 5.243 - 3.334 ) 
    Source Clock Delay      (SCD):    2.214ns
    Clock Pessimism Removal (CPR):    0.288ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.128ns (routing 0.171ns, distribution 0.957ns)
  Clock Net Delay (Destination): 0.994ns (routing 0.155ns, distribution 0.839ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.128     2.214    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y337        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.295 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/Q
                         net (fo=4, routed)           1.004     3.298    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[3]
    SLICE_X81Y340        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/S
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.994     5.243    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y340        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                         clock pessimism              0.288     5.531    
                         clock uncertainty           -0.035     5.496    
    SLICE_X81Y340        FDSE (Setup_DFF_SLICEL_C_S)
                                                     -0.074     5.422    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]
  -------------------------------------------------------------------
                         required time                          5.422    
                         arrival time                          -3.298    
  -------------------------------------------------------------------
                         slack                                  2.123    

Slack (MET) :             2.123ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/S
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.085ns  (logic 0.081ns (7.469%)  route 1.004ns (92.531%))
  Logic Levels:           0  
  Clock Path Skew:        -0.017ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.909ns = ( 5.243 - 3.334 ) 
    Source Clock Delay      (SCD):    2.214ns
    Clock Pessimism Removal (CPR):    0.288ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.128ns (routing 0.171ns, distribution 0.957ns)
  Clock Net Delay (Destination): 0.994ns (routing 0.155ns, distribution 0.839ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.128     2.214    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y337        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.295 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/Q
                         net (fo=4, routed)           1.004     3.298    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[3]
    SLICE_X81Y340        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/S
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.994     5.243    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y340        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
                         clock pessimism              0.288     5.531    
                         clock uncertainty           -0.035     5.496    
    SLICE_X81Y340        FDSE (Setup_DFF2_SLICEL_C_S)
                                                     -0.074     5.422    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]
  -------------------------------------------------------------------
                         required time                          5.422    
                         arrival time                          -3.298    
  -------------------------------------------------------------------
                         slack                                  2.123    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.054ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/D
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.106ns  (logic 0.062ns (58.743%)  route 0.044ns (41.257%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.528ns
    Source Clock Delay      (SCD):    1.266ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      0.649ns (routing 0.096ns, distribution 0.553ns)
  Clock Net Delay (Destination): 0.741ns (routing 0.108ns, distribution 0.633ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.649     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y340        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y340        FDSE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.305 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/Q
                         net (fo=7, routed)           0.029     1.333    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]
    SLICE_X81Y340        LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.023     1.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]_i_1/O
                         net (fo=1, routed)           0.015     1.371    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]_i_1_n_0
    SLICE_X81Y340        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.741     1.528    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y340        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                         clock pessimism             -0.256     1.272    
    SLICE_X81Y340        FDSE (Hold_BFF_SLICEL_C_D)
                                                      0.046     1.318    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.318    
                         arrival time                           1.371    
  -------------------------------------------------------------------
                         slack                                  0.054    

Slack (MET) :             0.054ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/D
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.107ns  (logic 0.072ns (67.578%)  route 0.035ns (32.422%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.528ns
    Source Clock Delay      (SCD):    1.266ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      0.649ns (routing 0.096ns, distribution 0.553ns)
  Clock Net Delay (Destination): 0.741ns (routing 0.108ns, distribution 0.633ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.649     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y340        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y340        FDSE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.305 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/Q
                         net (fo=7, routed)           0.029     1.333    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]
    SLICE_X81Y340        LUT4 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.033     1.366 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[5]_i_1/O
                         net (fo=1, routed)           0.006     1.372    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[5]_i_1_n_0
    SLICE_X81Y340        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.741     1.528    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y340        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
                         clock pessimism             -0.256     1.272    
    SLICE_X81Y340        FDSE (Hold_DFF2_SLICEL_C_D)
                                                      0.047     1.319    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]
  -------------------------------------------------------------------
                         required time                         -1.319    
                         arrival time                           1.372    
  -------------------------------------------------------------------
                         slack                                  0.054    

Slack (MET) :             0.054ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        0.018ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.522ns
    Source Clock Delay      (SCD):    1.259ns
    Clock Pessimism Removal (CPR):    0.245ns
  Clock Net Delay (Source):      0.642ns (routing 0.096ns, distribution 0.546ns)
  Clock Net Delay (Destination): 0.735ns (routing 0.108ns, distribution 0.627ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.642     1.259    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y336        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y336        FDPE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     1.299 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/Q
                         net (fo=1, routed)           0.079     1.378    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async[1]
    SLICE_X81Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.735     1.522    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/C
                         clock pessimism             -0.245     1.277    
    SLICE_X81Y337        FDRE (Hold_AFF2_SLICEL_C_D)
                                                      0.047     1.324    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.324    
                         arrival time                           1.378    
  -------------------------------------------------------------------
                         slack                                  0.054    

Slack (MET) :             0.061ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.114ns  (logic 0.076ns (66.657%)  route 0.038ns (33.343%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.538ns
    Source Clock Delay      (SCD):    1.274ns
    Clock Pessimism Removal (CPR):    0.258ns
  Clock Net Delay (Source):      0.657ns (routing 0.096ns, distribution 0.561ns)
  Clock Net Delay (Destination): 0.751ns (routing 0.108ns, distribution 0.643ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.657     1.274    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X82Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y340        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.313 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/Q
                         net (fo=4, routed)           0.029     1.342    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]
    SLICE_X82Y340        LUT4 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.037     1.379 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[3]_i_1/O
                         net (fo=1, routed)           0.009     1.388    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst0[3]
    SLICE_X82Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.751     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X82Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                         clock pessimism             -0.258     1.280    
    SLICE_X82Y340        FDRE (Hold_DFF2_SLICEM_C_D)
                                                      0.047     1.327    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.327    
                         arrival time                           1.388    
  -------------------------------------------------------------------
                         slack                                  0.061    

Slack (MET) :             0.067ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/D
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.119ns  (logic 0.074ns (62.424%)  route 0.045ns (37.576%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.528ns
    Source Clock Delay      (SCD):    1.266ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      0.649ns (routing 0.096ns, distribution 0.553ns)
  Clock Net Delay (Destination): 0.741ns (routing 0.108ns, distribution 0.633ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.649     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y340        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y340        FDSE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.305 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/Q
                         net (fo=7, routed)           0.029     1.333    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]
    SLICE_X81Y340        LUT4 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.035     1.368 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]_i_1/O
                         net (fo=1, routed)           0.016     1.384    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]_i_1_n_0
    SLICE_X81Y340        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.741     1.528    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y340        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                         clock pessimism             -0.256     1.272    
    SLICE_X81Y340        FDSE (Hold_DFF_SLICEL_C_D)
                                                      0.046     1.318    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.318    
                         arrival time                           1.384    
  -------------------------------------------------------------------
                         slack                                  0.067    

Slack (MET) :             0.068ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.121ns  (logic 0.040ns (33.058%)  route 0.081ns (66.942%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.522ns
    Source Clock Delay      (SCD):    1.260ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      0.643ns (routing 0.096ns, distribution 0.547ns)
  Clock Net Delay (Destination): 0.735ns (routing 0.108ns, distribution 0.627ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.643     1.260    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y337        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.300 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/Q
                         net (fo=1, routed)           0.081     1.381    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[0]
    SLICE_X81Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.735     1.522    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/C
                         clock pessimism             -0.256     1.266    
    SLICE_X81Y337        FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.047     1.313    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.313    
                         arrival time                           1.381    
  -------------------------------------------------------------------
                         slack                                  0.068    

Slack (MET) :             0.068ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/D
                            (rising edge-triggered cell FDPE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.121ns  (logic 0.040ns (33.058%)  route 0.081ns (66.942%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.521ns
    Source Clock Delay      (SCD):    1.259ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      0.642ns (routing 0.096ns, distribution 0.546ns)
  Clock Net Delay (Destination): 0.734ns (routing 0.108ns, distribution 0.626ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.642     1.259    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y336        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y336        FDPE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.299 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/Q
                         net (fo=1, routed)           0.081     1.380    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async[0]
    SLICE_X81Y336        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.734     1.521    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y336        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C
                         clock pessimism             -0.256     1.265    
    SLICE_X81Y336        FDPE (Hold_BFF2_SLICEL_C_D)
                                                      0.047     1.312    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.312    
                         arrival time                           1.380    
  -------------------------------------------------------------------
                         slack                                  0.068    

Slack (MET) :             0.069ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.122ns  (logic 0.040ns (32.787%)  route 0.082ns (67.213%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.522ns
    Source Clock Delay      (SCD):    1.260ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      0.643ns (routing 0.096ns, distribution 0.547ns)
  Clock Net Delay (Destination): 0.735ns (routing 0.108ns, distribution 0.627ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.643     1.260    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y337        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     1.300 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/Q
                         net (fo=1, routed)           0.082     1.382    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[2]
    SLICE_X81Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.735     1.522    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                         clock pessimism             -0.256     1.266    
    SLICE_X81Y337        FDRE (Hold_DFF2_SLICEL_C_D)
                                                      0.047     1.313    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.313    
                         arrival time                           1.382    
  -------------------------------------------------------------------
                         slack                                  0.069    

Slack (MET) :             0.077ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.129ns  (logic 0.074ns (57.357%)  route 0.055ns (42.643%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.538ns
    Source Clock Delay      (SCD):    1.274ns
    Clock Pessimism Removal (CPR):    0.258ns
  Clock Net Delay (Source):      0.657ns (routing 0.096ns, distribution 0.561ns)
  Clock Net Delay (Destination): 0.751ns (routing 0.108ns, distribution 0.643ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.657     1.274    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X82Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y340        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.313 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/Q
                         net (fo=4, routed)           0.029     1.342    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]
    SLICE_X82Y340        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.035     1.377 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]_i_1/O
                         net (fo=1, routed)           0.026     1.403    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst0[2]
    SLICE_X82Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.751     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X82Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                         clock pessimism             -0.258     1.280    
    SLICE_X82Y340        FDRE (Hold_DFF_SLICEM_C_D)
                                                      0.046     1.326    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.326    
                         arrival time                           1.403    
  -------------------------------------------------------------------
                         slack                                  0.077    

Slack (MET) :             0.098ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.189ns  (logic 0.076ns (40.147%)  route 0.113ns (59.853%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.045ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.532ns
    Source Clock Delay      (SCD):    1.273ns
    Clock Pessimism Removal (CPR):    0.215ns
  Clock Net Delay (Source):      0.656ns (routing 0.096ns, distribution 0.560ns)
  Clock Net Delay (Destination): 0.745ns (routing 0.108ns, distribution 0.637ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.656     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X82Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y340        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.311 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/Q
                         net (fo=7, routed)           0.107     1.418    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]
    SLICE_X81Y340        LUT4 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.038     1.456 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_i_1/O
                         net (fo=1, routed)           0.006     1.462    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_i_1_n_0
    SLICE_X81Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.745     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
                         clock pessimism             -0.215     1.317    
    SLICE_X81Y340        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.047     1.364    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg
  -------------------------------------------------------------------
                         required time                         -1.364    
                         arrival time                           1.462    
  -------------------------------------------------------------------
                         slack                                  0.098    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         sys_clk_ddr4_clk_p
Waveform(ns):       { 0.000 1.667 }
Period(ns):         3.334
Sources:            { sys_clk_ddr4_clk_p }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     BUFGCE/I           n/a            1.290         3.334       2.044      BUFGCE_X0Y124  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/I
Min Period        n/a     MMCME4_ADV/CLKIN1  n/a            1.071         3.334       2.263      MMCM_X0Y4      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X82Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
Min Period        n/a     FDSE/C             n/a            0.550         3.334       2.784      SLICE_X81Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X82Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X82Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
Min Period        n/a     FDSE/C             n/a            0.550         3.334       2.784      SLICE_X81Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
Min Period        n/a     FDSE/C             n/a            0.550         3.334       2.784      SLICE_X81Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X82Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X81Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
Max Period        n/a     MMCME4_ADV/CLKIN1  n/a            100.000       3.334       96.666     MMCM_X0Y4      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Low Pulse Width   Slow    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y4      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Low Pulse Width   Fast    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y4      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X82Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X82Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
Low Pulse Width   Slow    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X81Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
Low Pulse Width   Fast    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X81Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X82Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X82Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X82Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X82Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
High Pulse Width  Slow    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y4      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
High Pulse Width  Fast    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y4      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X82Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X82Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
High Pulse Width  Slow    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X81Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
High Pulse Width  Fast    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X81Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X82Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X82Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X82Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X82Y340  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        0.078ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.010ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.078ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[3].sync_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/cal_DQOut_pre_reg[35]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.690ns  (logic 0.080ns (2.974%)  route 2.610ns (97.026%))
  Logic Levels:           0  
  Clock Path Skew:        -0.195ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.423ns = ( 7.423 - 3.001 ) 
    Source Clock Delay      (SCD):    4.261ns
    Clock Pessimism Removal (CPR):    -0.357ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.051ns (routing 0.788ns, distribution 1.263ns)
  Clock Net Delay (Destination): 1.776ns (routing 0.716ns, distribution 1.060ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.051     4.261    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[30].sync_reg_reg[1]_0
    SLICE_X82Y348        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[3].sync_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y348        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     4.341 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[3].sync_reg_reg[1]/Q
                         net (fo=45, routed)          2.610     6.951    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_write_data[3]
    SLICE_X95Y263        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/cal_DQOut_pre_reg[35]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.776     7.423    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X95Y263        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/cal_DQOut_pre_reg[35]/C
                         clock pessimism             -0.357     7.066    
                         clock uncertainty           -0.062     7.004    
    SLICE_X95Y263        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025     7.029    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/cal_DQOut_pre_reg[35]
  -------------------------------------------------------------------
                         required time                          7.029    
                         arrival time                          -6.951    
  -------------------------------------------------------------------
                         slack                                  0.078    

Slack (MET) :             0.084ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo_reg[0][0][3][4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.833ns  (logic 0.177ns (6.248%)  route 2.656ns (93.752%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.046ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.476ns = ( 7.477 - 3.001 ) 
    Source Clock Delay      (SCD):    4.228ns
    Clock Pessimism Removal (CPR):    -0.295ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.018ns (routing 0.788ns, distribution 1.230ns)
  Clock Net Delay (Destination): 1.829ns (routing 0.716ns, distribution 1.113ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.018     4.228    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X87Y331        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y331        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     4.306 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg/Q
                         net (fo=431, routed)         2.607     6.913    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1
    SLICE_X84Y349        LUT4 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.099     7.012 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo[0][0][3][4]_i_1__0/O
                         net (fo=1, routed)           0.049     7.061    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo[0][0][3][4]_i_1__0_n_0
    SLICE_X84Y349        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo_reg[0][0][3][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.829     7.477    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X84Y349        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo_reg[0][0][3][4]/C
                         clock pessimism             -0.295     7.182    
                         clock uncertainty           -0.062     7.120    
    SLICE_X84Y349        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025     7.145    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo_reg[0][0][3][4]
  -------------------------------------------------------------------
                         required time                          7.145    
                         arrival time                          -7.061    
  -------------------------------------------------------------------
                         slack                                  0.084    

Slack (MET) :             0.088ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo_reg[0][0][1][15]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.815ns  (logic 0.200ns (7.105%)  route 2.615ns (92.895%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.060ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.463ns = ( 7.463 - 3.001 ) 
    Source Clock Delay      (SCD):    4.228ns
    Clock Pessimism Removal (CPR):    -0.295ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.018ns (routing 0.788ns, distribution 1.230ns)
  Clock Net Delay (Destination): 1.816ns (routing 0.716ns, distribution 1.100ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.018     4.228    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X87Y331        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y331        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     4.306 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg/Q
                         net (fo=431, routed)         2.566     6.872    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1
    SLICE_X85Y348        LUT4 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.122     6.994 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo[0][0][1][15]_i_1__0/O
                         net (fo=1, routed)           0.049     7.043    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo[0][0][1][15]_i_1__0_n_0
    SLICE_X85Y348        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo_reg[0][0][1][15]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.816     7.463    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X85Y348        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo_reg[0][0][1][15]/C
                         clock pessimism             -0.295     7.169    
                         clock uncertainty           -0.062     7.106    
    SLICE_X85Y348        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025     7.131    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo_reg[0][0][1][15]
  -------------------------------------------------------------------
                         required time                          7.131    
                         arrival time                          -7.043    
  -------------------------------------------------------------------
                         slack                                  0.088    

Slack (MET) :             0.098ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo_reg[0][0][1][11]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.761ns  (logic 0.823ns (29.805%)  route 1.938ns (70.195%))
  Logic Levels:           8  (CARRY8=1 LUT5=1 LUT6=6)
  Clock Path Skew:        -0.104ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.466ns = ( 7.467 - 3.001 ) 
    Source Clock Delay      (SCD):    4.275ns
    Clock Pessimism Removal (CPR):    -0.295ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.065ns (routing 0.788ns, distribution 1.277ns)
  Clock Net Delay (Destination): 1.819ns (routing 0.716ns, distribution 1.103ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.065     4.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X84Y342        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo_reg[0][0][1][11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y342        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.354 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo_reg[0][0][1][11]/Q
                         net (fo=1, routed)           0.460     4.814    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo_reg_n_0_[0][0][1][11]
    SLICE_X93Y350        LUT6 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.148     4.962 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/i__carry_i_11__1/O
                         net (fo=1, routed)           0.222     5.184    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/i__carry_i_11__1_n_0
    SLICE_X93Y359        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.122     5.306 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/i__carry_i_3__1/O
                         net (fo=1, routed)           0.025     5.331    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/i__carry_i_3__1_n_0
    SLICE_X93Y359        CARRY8 (Prop_CARRY8_SLICEM_S[3]_CO[5])
                                                      0.146     5.477 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.225     5.702    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X91Y359        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.035     5.737 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0/O
                         net (fo=1, routed)           0.085     5.822    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0_n_0
    SLICE_X90Y359        LUT6 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.037     5.859 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__1/O
                         net (fo=4, routed)           0.098     5.957    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__1_n_0
    SLICE_X90Y359        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.037     5.994 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__1/O
                         net (fo=80, routed)          0.642     6.636    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__1_n_0
    SLICE_X81Y334        LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.123     6.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[11]_i_3__1/O
                         net (fo=1, routed)           0.131     6.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[11]_i_3__1_n_0
    SLICE_X81Y334        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.096     6.986 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[11]_i_1__1/O
                         net (fo=1, routed)           0.050     7.036    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[11]_i_1__1_n_0
    SLICE_X81Y334        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.819     7.467    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X81Y334        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[11]/C
                         clock pessimism             -0.295     7.172    
                         clock uncertainty           -0.062     7.110    
    SLICE_X81Y334        FDRE (Setup_CFF_SLICEL_C_D)
                                                      0.025     7.135    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[11]
  -------------------------------------------------------------------
                         required time                          7.135    
                         arrival time                          -7.036    
  -------------------------------------------------------------------
                         slack                                  0.098    

Slack (MET) :             0.101ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo_reg[0][0][2][7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.798ns  (logic 0.200ns (7.147%)  route 2.598ns (92.853%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.459ns = ( 7.460 - 3.001 ) 
    Source Clock Delay      (SCD):    4.228ns
    Clock Pessimism Removal (CPR):    -0.295ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.018ns (routing 0.788ns, distribution 1.230ns)
  Clock Net Delay (Destination): 1.812ns (routing 0.716ns, distribution 1.096ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.018     4.228    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X87Y331        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y331        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     4.306 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg/Q
                         net (fo=431, routed)         2.526     6.832    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1
    SLICE_X86Y348        LUT4 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.122     6.954 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo[0][0][2][7]_i_1__0/O
                         net (fo=1, routed)           0.072     7.026    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo[0][0][2][7]_i_1__0_n_0
    SLICE_X86Y348        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo_reg[0][0][2][7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.812     7.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X86Y348        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo_reg[0][0][2][7]/C
                         clock pessimism             -0.295     7.165    
                         clock uncertainty           -0.062     7.103    
    SLICE_X86Y348        FDRE (Setup_DFF_SLICEM_C_D)
                                                      0.025     7.128    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo_reg[0][0][2][7]
  -------------------------------------------------------------------
                         required time                          7.128    
                         arrival time                          -7.026    
  -------------------------------------------------------------------
                         slack                                  0.101    

Slack (MET) :             0.107ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_cmd/app_addr_r1_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.752ns  (logic 0.306ns (11.119%)  route 2.446ns (88.881%))
  Logic Levels:           3  (LUT3=1 LUT6=2)
  Clock Path Skew:        -0.104ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.465ns = ( 7.466 - 3.001 ) 
    Source Clock Delay      (SCD):    4.204ns
    Clock Pessimism Removal (CPR):    -0.365ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.994ns (routing 0.788ns, distribution 1.206ns)
  Clock Net Delay (Destination): 1.818ns (routing 0.716ns, distribution 1.102ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.994     4.204    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_cmd/app_cmd_r1_reg[0]_0
    SLICE_X82Y190        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_cmd/app_addr_r1_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y190        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.282 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_cmd/app_addr_r1_reg[10]/Q
                         net (fo=2, routed)           1.356     5.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_cmd/app_addr_r1[10]
    SLICE_X82Y319        LUT3 (Prop_D5LUT_SLICEM_I0_O)
                                                      0.066     5.704 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_cmd/txn_fifo[0][15]_i_2/O
                         net (fo=23, routed)          0.537     6.241    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/col[4]
    SLICE_X90Y345        LUT6 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.038     6.279 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[15]_i_3__1/O
                         net (fo=1, routed)           0.498     6.777    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[15]_i_3__1_n_0
    SLICE_X83Y330        LUT6 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.124     6.901 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[15]_i_1__1/O
                         net (fo=1, routed)           0.055     6.956    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[15]_i_1__1_n_0
    SLICE_X83Y330        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.818     7.466    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X83Y330        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[15]/C
                         clock pessimism             -0.365     7.100    
                         clock uncertainty           -0.062     7.038    
    SLICE_X83Y330        FDRE (Setup_EFF_SLICEM_C_D)
                                                      0.025     7.063    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[15]
  -------------------------------------------------------------------
                         required time                          7.063    
                         arrival time                          -6.956    
  -------------------------------------------------------------------
                         slack                                  0.107    

Slack (MET) :             0.114ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo_reg[0][0][1][11]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[1]_replica/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.741ns  (logic 0.818ns (29.848%)  route 1.923ns (70.152%))
  Logic Levels:           8  (CARRY8=1 LUT5=1 LUT6=6)
  Clock Path Skew:        -0.109ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.461ns = ( 7.462 - 3.001 ) 
    Source Clock Delay      (SCD):    4.275ns
    Clock Pessimism Removal (CPR):    -0.295ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.065ns (routing 0.788ns, distribution 1.277ns)
  Clock Net Delay (Destination): 1.814ns (routing 0.716ns, distribution 1.098ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.065     4.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X84Y342        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo_reg[0][0][1][11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y342        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.354 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo_reg[0][0][1][11]/Q
                         net (fo=1, routed)           0.460     4.814    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/pageInfo_reg_n_0_[0][0][1][11]
    SLICE_X93Y350        LUT6 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.148     4.962 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/i__carry_i_11__1/O
                         net (fo=1, routed)           0.222     5.184    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/i__carry_i_11__1_n_0
    SLICE_X93Y359        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.122     5.306 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/i__carry_i_3__1/O
                         net (fo=1, routed)           0.025     5.331    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/i__carry_i_3__1_n_0
    SLICE_X93Y359        CARRY8 (Prop_CARRY8_SLICEM_S[3]_CO[5])
                                                      0.146     5.477 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.225     5.702    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X91Y359        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.035     5.737 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0/O
                         net (fo=1, routed)           0.085     5.822    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0_n_0
    SLICE_X90Y359        LUT6 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.037     5.859 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__1/O
                         net (fo=4, routed)           0.098     5.957    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__1_n_0
    SLICE_X90Y359        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.037     5.994 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__1/O
                         net (fo=80, routed)          0.396     6.390    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__1_n_0
    SLICE_X86Y346        LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.089     6.479 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[1]_i_2__1/O
                         net (fo=1, routed)           0.156     6.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[1]_i_2__1_n_0
    SLICE_X87Y347        LUT6 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.125     6.760 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[1]_i_1__1/O
                         net (fo=4, routed)           0.255     7.015    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[1]_i_1__1_n_0
    SLICE_X86Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[1]_replica/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.814     7.462    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X86Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[1]_replica/C
                         clock pessimism             -0.295     7.167    
                         clock uncertainty           -0.062     7.104    
    SLICE_X86Y351        FDRE (Setup_BFF2_SLICEM_C_D)
                                                      0.025     7.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[1]_replica
  -------------------------------------------------------------------
                         required time                          7.129    
                         arrival time                          -7.015    
  -------------------------------------------------------------------
                         slack                                  0.114    

Slack (MET) :             0.114ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_cmd/app_addr_r1_reg[27]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[38]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.742ns  (logic 0.358ns (13.057%)  route 2.384ns (86.943%))
  Logic Levels:           3  (LUT3=2 LUT6=1)
  Clock Path Skew:        -0.107ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.450ns = ( 7.450 - 3.001 ) 
    Source Clock Delay      (SCD):    4.192ns
    Clock Pessimism Removal (CPR):    -0.365ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.982ns (routing 0.788ns, distribution 1.194ns)
  Clock Net Delay (Destination): 1.803ns (routing 0.716ns, distribution 1.087ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.982     4.192    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_cmd/app_cmd_r1_reg[0]_0
    SLICE_X85Y189        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_cmd/app_addr_r1_reg[27]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y189        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.271 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_cmd/app_addr_r1_reg[27]/Q
                         net (fo=2, routed)           1.578     5.849    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_cmd/app_addr_r1[27]
    SLICE_X86Y327        LUT3 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.088     5.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_cmd/txn_fifo[0][38]_i_2/O
                         net (fo=23, routed)          0.345     6.282    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/row[14]
    SLICE_X87Y318        LUT3 (Prop_B5LUT_SLICEM_I0_O)
                                                      0.103     6.385 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo[2][38]_i_1__0/O
                         net (fo=2, routed)           0.389     6.774    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo[2][38]_i_1__0_n_0
    SLICE_X90Y319        LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.088     6.862 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[38]_i_1__0/O
                         net (fo=1, routed)           0.072     6.934    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[38]_i_1__0_n_0
    SLICE_X90Y319        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[38]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.803     7.450    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X90Y319        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[38]/C
                         clock pessimism             -0.365     7.085    
                         clock uncertainty           -0.062     7.023    
    SLICE_X90Y319        FDRE (Setup_DFF_SLICEM_C_D)
                                                      0.025     7.048    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[38]
  -------------------------------------------------------------------
                         required time                          7.048    
                         arrival time                          -6.934    
  -------------------------------------------------------------------
                         slack                                  0.114    

Slack (MET) :             0.114ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/u_ddr_cal_cplx_data/rd_addr_101_reg_rep/CLKARDCLK
                            (rising edge-triggered cell RAMB18E2 clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/cplx_DQOut_reg[436]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.588ns  (logic 0.317ns (12.250%)  route 2.271ns (87.750%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.261ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.399ns = ( 7.400 - 3.001 ) 
    Source Clock Delay      (SCD):    4.295ns
    Clock Pessimism Removal (CPR):    -0.365ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.085ns (routing 0.788ns, distribution 1.297ns)
  Clock Net Delay (Destination): 1.752ns (routing 0.716ns, distribution 1.036ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.085     4.295    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/u_ddr_cal_cplx_data/rd_addr_101_reg[7]_0
    RAMB18_X9Y108        RAMB18E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/u_ddr_cal_cplx_data/rd_addr_101_reg_rep/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X9Y108        RAMB18E2 (Prop_RAMB18E2_L_RAMB180_CLKARDCLK_DOUTADOUT[3])
                                                      0.219     4.514 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/u_ddr_cal_cplx_data/rd_addr_101_reg_rep/DOUTADOUT[3]
                         net (fo=75, routed)          2.222     6.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/u_ddr_cal_cplx_data/p_2_in15_in
    SLICE_X91Y196        LUT4 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.098     6.834 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/u_ddr_cal_cplx_data/cplx_DQOut[436]_i_1/O
                         net (fo=1, routed)           0.049     6.883    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/u_ddr_cal_cplx_data_n_77
    SLICE_X91Y196        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/cplx_DQOut_reg[436]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.752     7.400    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/rd_addr_101_reg[7]
    SLICE_X91Y196        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/cplx_DQOut_reg[436]/C
                         clock pessimism             -0.365     7.034    
                         clock uncertainty           -0.062     6.972    
    SLICE_X91Y196        FDRE (Setup_BFF_SLICEL_C_D)
                                                      0.025     6.997    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/cplx_DQOut_reg[436]
  -------------------------------------------------------------------
                         required time                          6.997    
                         arrival time                          -6.883    
  -------------------------------------------------------------------
                         slack                                  0.114    

Slack (MET) :             0.116ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[3].sync_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value_reg[45]/D
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.677ns  (logic 0.080ns (2.989%)  route 2.597ns (97.011%))
  Logic Levels:           0  
  Clock Path Skew:        -0.170ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.448ns = ( 7.448 - 3.001 ) 
    Source Clock Delay      (SCD):    4.261ns
    Clock Pessimism Removal (CPR):    -0.357ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.051ns (routing 0.788ns, distribution 1.263ns)
  Clock Net Delay (Destination): 1.801ns (routing 0.716ns, distribution 1.085ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.051     4.261    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[30].sync_reg_reg[1]_0
    SLICE_X82Y348        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[3].sync_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y348        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     4.341 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[3].sync_reg_reg[1]/Q
                         net (fo=45, routed)          2.597     6.937    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_write_data[3]
    SLICE_X82Y268        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value_reg[45]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.801     7.448    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X82Y268        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value_reg[45]/C
                         clock pessimism             -0.357     7.091    
                         clock uncertainty           -0.062     7.029    
    SLICE_X82Y268        FDSE (Setup_AFF_SLICEM_C_D)
                                                      0.025     7.054    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value_reg[45]
  -------------------------------------------------------------------
                         required time                          7.054    
                         arrival time                          -6.937    
  -------------------------------------------------------------------
                         slack                                  0.116    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_dout_r_reg[485]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1510]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.180ns  (logic 0.061ns (33.862%)  route 0.119ns (66.138%))
  Logic Levels:           0  
  Clock Path Skew:        0.110ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.378ns
    Source Clock Delay      (SCD):    4.564ns
    Clock Pessimism Removal (CPR):    -0.297ns
  Clock Net Delay (Source):      1.917ns (routing 0.716ns, distribution 1.201ns)
  Clock Net Delay (Destination): 2.168ns (routing 0.788ns, distribution 1.380ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.917     4.564    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X62Y198        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_dout_r_reg[485]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y198        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     4.625 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_dout_r_reg[485]/Q
                         net (fo=2, routed)           0.119     4.744    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[2112]_0[486]
    SLICE_X63Y198        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1510]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.168     4.378    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/aclk
    SLICE_X63Y198        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1510]/C
                         clock pessimism              0.297     4.674    
    SLICE_X63Y198        FDRE (Hold_BFF_SLICEM_C_D)
                                                      0.060     4.734    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1510]
  -------------------------------------------------------------------
                         required time                         -4.734    
                         arrival time                           4.744    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/rdData_reg[130]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0/RAMA/I
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.195ns  (logic 0.058ns (29.714%)  route 0.137ns (70.286%))
  Logic Levels:           0  
  Clock Path Skew:        0.105ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.255ns
    Source Clock Delay      (SCD):    4.450ns
    Clock Pessimism Removal (CPR):    -0.300ns
  Clock Net Delay (Source):      1.803ns (routing 0.716ns, distribution 1.087ns)
  Clock Net Delay (Destination): 2.045ns (routing 0.788ns, distribution 1.257ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.803     4.450    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X83Y270        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/rdData_reg[130]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.058     4.508 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/rdData_reg[130]/Q
                         net (fo=3, routed)           0.137     4.645    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0/DIA0
    SLICE_X83Y267        RAMD32                                       r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0/RAMA/I
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.045     4.255    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0/WCLK
    SLICE_X83Y267        RAMD32                                       r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0/RAMA/CLK
                         clock pessimism              0.300     4.555    
    SLICE_X83Y267        RAMD32 (Hold_E5LUT_SLICEM_CLK_I)
                                                      0.077     4.632    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0/RAMA
  -------------------------------------------------------------------
                         required time                         -4.632    
                         arrival time                           4.645    
  -------------------------------------------------------------------
                         slack                                  0.013    

Slack (MET) :             0.015ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/m_vector_i_reg[1071]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer_reg[1071]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.181ns  (logic 0.059ns (32.541%)  route 0.122ns (67.459%))
  Logic Levels:           0  
  Clock Path Skew:        0.106ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.512ns
    Source Clock Delay      (SCD):    4.682ns
    Clock Pessimism Removal (CPR):    -0.276ns
  Clock Net Delay (Source):      2.035ns (routing 0.716ns, distribution 1.319ns)
  Clock Net Delay (Destination): 2.302ns (routing 0.788ns, distribution 1.514ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.035     4.682    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/aclk
    SLICE_X49Y103        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/m_vector_i_reg[1071]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y103        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.059     4.741 r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/m_vector_i_reg[1071]/Q
                         net (fo=2, routed)           0.122     4.863    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer_reg[1144]_0[16]
    SLICE_X47Y105        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer_reg[1071]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.302     4.512    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/aclk
    SLICE_X47Y105        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer_reg[1071]/C
                         clock pessimism              0.276     4.788    
    SLICE_X47Y105        FDRE (Hold_EFF_SLICEL_C_D)
                                                      0.060     4.848    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer_reg[1071]
  -------------------------------------------------------------------
                         required time                         -4.848    
                         arrival time                           4.863    
  -------------------------------------------------------------------
                         slack                                  0.015    

Slack (MET) :             0.015ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_dout_r_reg[497]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1522]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.184ns  (logic 0.060ns (32.609%)  route 0.124ns (67.391%))
  Logic Levels:           0  
  Clock Path Skew:        0.107ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.371ns
    Source Clock Delay      (SCD):    4.561ns
    Clock Pessimism Removal (CPR):    -0.297ns
  Clock Net Delay (Source):      1.914ns (routing 0.716ns, distribution 1.198ns)
  Clock Net Delay (Destination): 2.161ns (routing 0.788ns, distribution 1.373ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.914     4.561    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X61Y201        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_dout_r_reg[497]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X61Y201        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.060     4.621 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_dout_r_reg[497]/Q
                         net (fo=2, routed)           0.124     4.745    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[2112]_0[498]
    SLICE_X63Y203        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1522]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.161     4.371    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/aclk
    SLICE_X63Y203        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1522]/C
                         clock pessimism              0.297     4.667    
    SLICE_X63Y203        FDRE (Hold_EFF2_SLICEM_C_D)
                                                      0.062     4.729    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1522]
  -------------------------------------------------------------------
                         required time                         -4.729    
                         arrival time                           4.745    
  -------------------------------------------------------------------
                         slack                                  0.015    

Slack (MET) :             0.017ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/m_vector_i_reg[1128]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer_reg[1128]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.131ns  (logic 0.059ns (45.038%)  route 0.072ns (54.962%))
  Logic Levels:           0  
  Clock Path Skew:        0.052ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.509ns
    Source Clock Delay      (SCD):    4.683ns
    Clock Pessimism Removal (CPR):    -0.226ns
  Clock Net Delay (Source):      2.036ns (routing 0.716ns, distribution 1.320ns)
  Clock Net Delay (Destination): 2.299ns (routing 0.788ns, distribution 1.511ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.036     4.683    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/aclk
    SLICE_X49Y105        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/m_vector_i_reg[1128]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y105        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.059     4.742 r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/m_vector_i_reg[1128]/Q
                         net (fo=2, routed)           0.072     4.814    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer_reg[1144]_0[41]
    SLICE_X49Y106        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer_reg[1128]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.299     4.509    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/aclk
    SLICE_X49Y106        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer_reg[1128]/C
                         clock pessimism              0.226     4.735    
    SLICE_X49Y106        FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.062     4.797    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer_reg[1128]
  -------------------------------------------------------------------
                         required time                         -4.797    
                         arrival time                           4.814    
  -------------------------------------------------------------------
                         slack                                  0.017    

Slack (MET) :             0.017ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.182ns  (logic 0.058ns (31.868%)  route 0.124ns (68.132%))
  Logic Levels:           0  
  Clock Path Skew:        0.103ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.201ns
    Source Clock Delay      (SCD):    4.402ns
    Clock Pessimism Removal (CPR):    -0.304ns
  Clock Net Delay (Source):      1.755ns (routing 0.716ns, distribution 1.039ns)
  Clock Net Delay (Destination): 1.991ns (routing 0.788ns, distribution 1.203ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.755     4.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X90Y196        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y196        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     4.460 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[9]/Q
                         net (fo=1, routed)           0.124     4.584    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg__5[9]
    SLICE_X88Y196        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.991     4.201    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X88Y196        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[1]/C
                         clock pessimism              0.304     4.505    
    SLICE_X88Y196        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.062     4.567    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[1]
  -------------------------------------------------------------------
                         required time                         -4.567    
                         arrival time                           4.584    
  -------------------------------------------------------------------
                         slack                                  0.017    

Slack (MET) :             0.018ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.194ns  (logic 0.058ns (29.897%)  route 0.136ns (70.103%))
  Logic Levels:           0  
  Clock Path Skew:        0.114ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.254ns
    Source Clock Delay      (SCD):    4.440ns
    Clock Pessimism Removal (CPR):    -0.300ns
  Clock Net Delay (Source):      1.793ns (routing 0.716ns, distribution 1.077ns)
  Clock Net Delay (Destination): 2.044ns (routing 0.788ns, distribution 1.256ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.793     4.440    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X85Y265        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y265        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.058     4.498 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[9]/Q
                         net (fo=1, routed)           0.136     4.634    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg__5[9]
    SLICE_X83Y265        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.044     4.254    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X83Y265        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[1]/C
                         clock pessimism              0.300     4.554    
    SLICE_X83Y265        FDRE (Hold_HFF2_SLICEM_C_D)
                                                      0.062     4.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[1]
  -------------------------------------------------------------------
                         required time                         -4.616    
                         arrival time                           4.634    
  -------------------------------------------------------------------
                         slack                                  0.018    

Slack (MET) :             0.018ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[142]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][340]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.179ns  (logic 0.095ns (53.073%)  route 0.084ns (46.927%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.101ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.351ns
    Source Clock Delay      (SCD):    4.546ns
    Clock Pessimism Removal (CPR):    -0.296ns
  Clock Net Delay (Source):      1.899ns (routing 0.716ns, distribution 1.183ns)
  Clock Net Delay (Destination): 2.141ns (routing 0.788ns, distribution 1.353ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.899     4.546    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/clka
    SLICE_X72Y207        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[142]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y207        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.060     4.606 r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[142]/Q
                         net (fo=1, routed)           0.062     4.668    d_1_i/ddr4/axi_smc_1/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_mux_payld/s_sc_payld[328]
    SLICE_X71Y207        LUT3 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.035     4.703 r  d_1_i/ddr4/axi_smc_1/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_mux_payld/gen_pipe[1].pipe[1][340]_i_1/O
                         net (fo=1, routed)           0.022     4.725    d_1_i/ddr4/axi_smc_1/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/pipe[0][328]
    SLICE_X71Y207        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][340]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.141     4.351    d_1_i/ddr4/axi_smc_1/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/aclk
    SLICE_X71Y207        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][340]/C
                         clock pessimism              0.296     4.647    
    SLICE_X71Y207        FDRE (Hold_DFF_SLICEL_C_D)
                                                      0.060     4.707    d_1_i/ddr4/axi_smc_1/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][340]
  -------------------------------------------------------------------
                         required time                         -4.707    
                         arrival time                           4.725    
  -------------------------------------------------------------------
                         slack                                  0.018    

Slack (MET) :             0.018ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[12].sync_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/cal_WE_A_reg[4]/D
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.136ns  (logic 0.060ns (44.180%)  route 0.076ns (55.820%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.286ns
    Source Clock Delay      (SCD):    4.477ns
    Clock Pessimism Removal (CPR):    -0.247ns
  Clock Net Delay (Source):      1.830ns (routing 0.716ns, distribution 1.114ns)
  Clock Net Delay (Destination): 2.076ns (routing 0.788ns, distribution 1.288ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.830     4.477    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[30].sync_reg_reg[1]_0
    SLICE_X84Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[12].sync_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y351        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.060     4.537 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[12].sync_reg_reg[1]/Q
                         net (fo=24, routed)          0.076     4.613    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_write_data[12]
    SLICE_X84Y352        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/cal_WE_A_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.076     4.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X84Y352        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/cal_WE_A_reg[4]/C
                         clock pessimism              0.247     4.533    
    SLICE_X84Y352        FDSE (Hold_FFF2_SLICEL_C_D)
                                                      0.062     4.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/cal_WE_A_reg[4]
  -------------------------------------------------------------------
                         required time                         -4.595    
                         arrival time                           4.613    
  -------------------------------------------------------------------
                         slack                                  0.018    

Slack (MET) :             0.019ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][200]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMA_D1/I
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.196ns  (logic 0.058ns (29.592%)  route 0.138ns (70.408%))
  Logic Levels:           0  
  Clock Path Skew:        0.119ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.421ns
    Source Clock Delay      (SCD):    4.594ns
    Clock Pessimism Removal (CPR):    -0.292ns
  Clock Net Delay (Source):      1.947ns (routing 0.716ns, distribution 1.231ns)
  Clock Net Delay (Destination): 2.211ns (routing 0.788ns, distribution 1.423ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.947     4.594    d_1_i/ddr4/axi_smc_1/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/aclk
    SLICE_X71Y255        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][200]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y255        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.058     4.652 r  d_1_i/ddr4/axi_smc_1/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][200]/Q
                         net (fo=1, routed)           0.138     4.790    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/DIA1
    SLICE_X72Y254        RAMD32                                       r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMA_D1/I
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.211     4.421    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/WCLK
    SLICE_X72Y254        RAMD32                                       r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMA_D1/CLK
                         clock pessimism              0.292     4.713    
    SLICE_X72Y254        RAMD32 (Hold_A6LUT_SLICEM_CLK_I)
                                                      0.058     4.771    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMA_D1
  -------------------------------------------------------------------
                         required time                         -4.771    
                         arrival time                           4.790    
  -------------------------------------------------------------------
                         slack                                  0.019    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mmcm_clkout0
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin                    Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location               Pin
Min Period        n/a     PS8/MAXIGP1ACLK            n/a            3.000         3.001       0.001      PS8_X0Y0               d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y162  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y164  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y165  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y166  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Max Period        n/a     PLLE4_ADV/CLKIN            n/a            14.286        3.001       11.285     PLL_X0Y7               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Max Period        n/a     PLLE4_ADV/CLKIN            n/a            14.286        3.001       11.285     PLL_X0Y9               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Max Period        n/a     PLLE4_ADV/CLKIN            n/a            14.286        3.001       11.285     PLL_X0Y10              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Slow    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0               d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
Low Pulse Width   Fast    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0               d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
Low Pulse Width   Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y7               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y7               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y9               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y9               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y10              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y10              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Slow    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Low Pulse Width   Fast    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
High Pulse Width  Fast    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0               d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
High Pulse Width  Slow    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0               d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
High Pulse Width  Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y7               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y7               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y9               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y9               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y10              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y10              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Slow    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
High Pulse Width  Fast    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[0]
  To Clock:  pll_clk[0]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[0]
Waveform(ns):       { 0.000 0.188 }
Period(ns):         0.375
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY }

Check Type        Corner  Lib Pin                   Reference Pin             Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y29  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y30  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y31  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     PLLE4_ADV/CLKOUTPHY       n/a                       0.333         0.375       0.042      PLL_X0Y7                d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.316      1.016      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.319      1.019      BITSLICE_CONTROL_X0Y30  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.322      1.022      BITSLICE_CONTROL_X0Y29  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.323      1.023      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.323      1.023      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.323      1.023      BITSLICE_CONTROL_X0Y31  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.324      1.024      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.326      1.026      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.469      1.169      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.476      1.176      BITSLICE_CONTROL_X0Y30  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[0]_DIV
  To Clock:  pll_clk[0]_DIV

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.300ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[0]_DIV
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q }

Check Type        Corner  Lib Pin                           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location               Pin
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y162  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y164  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y165  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y166  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y167  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[1]
  To Clock:  pll_clk[1]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[1]
Waveform(ns):       { 0.000 0.188 }
Period(ns):         0.375
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY }

Check Type        Corner  Lib Pin                   Reference Pin             Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y37  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y38  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y39  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     PLLE4_ADV/CLKOUTPHY       n/a                       0.333         0.375       0.042      PLL_X0Y9                d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.313      1.013      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.316      1.016      BITSLICE_CONTROL_X0Y38  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.320      1.020      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.320      1.020      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.320      1.020      BITSLICE_CONTROL_X0Y39  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.321      1.021      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.322      1.022      BITSLICE_CONTROL_X0Y37  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.323      1.023      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.465      1.165      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.472      1.172      BITSLICE_CONTROL_X0Y38  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[1]_DIV
  To Clock:  pll_clk[1]_DIV

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.300ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[1]_DIV
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q }

Check Type        Corner  Lib Pin                           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location               Pin
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y208  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y210  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y211  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y212  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y213  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y214  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y216  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y217  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y218  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y219  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y208  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y208  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y210  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y210  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y211  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y211  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y212  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y212  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y213  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y213  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y208  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y208  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y210  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y210  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y211  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y211  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y212  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y212  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y213  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y213  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[2]
  To Clock:  pll_clk[2]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[2]
Waveform(ns):       { 0.000 0.188 }
Period(ns):         0.375
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY }

Check Type        Corner  Lib Pin                   Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y42  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y43  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     PLLE4_ADV/CLKOUTPHY       n/a            0.333         0.375       0.042      PLL_X0Y10               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y42  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y42  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y42  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y42  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[2]_DIV
  To Clock:  pll_clk[2]_DIV

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.300ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[2]_DIV
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q }

Check Type        Corner  Lib Pin                           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location               Pin
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y286  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y288  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y289  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y290  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y291  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y292  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y293  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y294  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y295  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y296  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y286  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y286  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y288  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y288  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y289  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y289  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y290  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y290  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y291  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y291  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y286  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y286  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y288  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y288  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y289  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y289  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y290  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y290  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y291  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y291  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack        9.755ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.022ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        5.469ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             9.755ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.113ns  (logic 0.554ns (26.224%)  route 1.559ns (73.776%))
  Logic Levels:           5  (LUT5=3 LUT6=2)
  Clock Path Skew:        -0.084ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.666ns = ( 15.668 - 12.002 ) 
    Source Clock Delay      (SCD):    3.382ns
    Clock Pessimism Removal (CPR):    -0.368ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.181ns (routing 0.171ns, distribution 1.010ns)
  Clock Net Delay (Destination): 1.027ns (routing 0.155ns, distribution 0.872ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.181     3.382    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/clk
    SLICE_X100Y300       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y300       FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     3.462 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/Q
                         net (fo=6, routed)           0.372     3.834    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/abort_rd_edge
    SLICE_X102Y301       LUT5 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050     3.884 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/FSM_onehot_current_state[17]_i_1/O
                         net (fo=2, routed)           0.342     4.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_reg_2[0]
    SLICE_X102Y300       LUT5 (Prop_D5LUT_SLICEL_I4_O)
                                                      0.096     4.322 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_2/O
                         net (fo=1, routed)           0.163     4.485    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_2_n_0
    SLICE_X102Y300       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.097     4.582 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_1/O
                         net (fo=24, routed)          0.480     5.061    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state_reg[11]
    SLICE_X101Y304       LUT5 (Prop_D5LUT_SLICEL_I3_O)
                                                      0.133     5.194 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9/O
                         net (fo=1, routed)           0.154     5.348    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_n_0
    SLICE_X101Y304       LUT6 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.098     5.446 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/sl_dwe_r[0]_i_1/O
                         net (fo=1, routed)           0.048     5.494    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_13
    SLICE_X101Y304       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863    13.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.027    15.668    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X101Y304       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]/C
                         clock pessimism             -0.368    15.300    
                         clock uncertainty           -0.076    15.225    
    SLICE_X101Y304       FDCE (Setup_AFF_SLICEL_C_D)
                                                      0.025    15.250    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]
  -------------------------------------------------------------------
                         required time                         15.250    
                         arrival time                          -5.494    
  -------------------------------------------------------------------
                         slack                                  9.755    

Slack (MET) :             9.811ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/dec_wdc_r_reg/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.069ns  (logic 0.581ns (28.079%)  route 1.488ns (71.921%))
  Logic Levels:           5  (LUT3=1 LUT5=3 LUT6=1)
  Clock Path Skew:        -0.072ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.678ns = ( 15.680 - 12.002 ) 
    Source Clock Delay      (SCD):    3.382ns
    Clock Pessimism Removal (CPR):    -0.368ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.181ns (routing 0.171ns, distribution 1.010ns)
  Clock Net Delay (Destination): 1.039ns (routing 0.155ns, distribution 0.884ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.181     3.382    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/clk
    SLICE_X100Y300       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y300       FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     3.462 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/Q
                         net (fo=6, routed)           0.372     3.834    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/abort_rd_edge
    SLICE_X102Y301       LUT5 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050     3.884 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/FSM_onehot_current_state[17]_i_1/O
                         net (fo=2, routed)           0.342     4.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_reg_2[0]
    SLICE_X102Y300       LUT5 (Prop_D5LUT_SLICEL_I4_O)
                                                      0.096     4.322 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_2/O
                         net (fo=1, routed)           0.163     4.485    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_2_n_0
    SLICE_X102Y300       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.097     4.582 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_1/O
                         net (fo=24, routed)          0.409     4.991    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state_reg[11]
    SLICE_X104Y302       LUT5 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.159     5.150 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__6/O
                         net (fo=1, routed)           0.130     5.280    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__6_n_0
    SLICE_X104Y302       LUT3 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.099     5.379 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/dec_wdc_r_i_1/O
                         net (fo=1, routed)           0.072     5.451    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_10
    SLICE_X104Y302       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/dec_wdc_r_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863    13.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.039    15.680    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y302       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/dec_wdc_r_reg/C
                         clock pessimism             -0.368    15.312    
                         clock uncertainty           -0.076    15.237    
    SLICE_X104Y302       FDCE (Setup_DFF_SLICEM_C_D)
                                                      0.025    15.262    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/dec_wdc_r_reg
  -------------------------------------------------------------------
                         required time                         15.262    
                         arrival time                          -5.451    
  -------------------------------------------------------------------
                         slack                                  9.811    

Slack (MET) :             9.819ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.049ns  (logic 0.591ns (28.849%)  route 1.458ns (71.151%))
  Logic Levels:           5  (LUT5=3 LUT6=2)
  Clock Path Skew:        -0.084ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.666ns = ( 15.668 - 12.002 ) 
    Source Clock Delay      (SCD):    3.382ns
    Clock Pessimism Removal (CPR):    -0.368ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.181ns (routing 0.171ns, distribution 1.010ns)
  Clock Net Delay (Destination): 1.027ns (routing 0.155ns, distribution 0.872ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.181     3.382    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/clk
    SLICE_X100Y300       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y300       FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     3.462 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/Q
                         net (fo=6, routed)           0.372     3.834    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/abort_rd_edge
    SLICE_X102Y301       LUT5 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050     3.884 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/FSM_onehot_current_state[17]_i_1/O
                         net (fo=2, routed)           0.342     4.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_reg_2[0]
    SLICE_X102Y300       LUT5 (Prop_D5LUT_SLICEL_I4_O)
                                                      0.096     4.322 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_2/O
                         net (fo=1, routed)           0.163     4.485    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_2_n_0
    SLICE_X102Y300       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.097     4.582 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_1/O
                         net (fo=24, routed)          0.480     5.061    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state_reg[11]
    SLICE_X101Y304       LUT5 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.122     5.183 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__8/O
                         net (fo=1, routed)           0.051     5.234    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__8_n_0
    SLICE_X101Y304       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.146     5.380 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/sl_den_r[0]_i_1/O
                         net (fo=1, routed)           0.050     5.430    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_12
    SLICE_X101Y304       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863    13.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.027    15.668    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X101Y304       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]/C
                         clock pessimism             -0.368    15.300    
                         clock uncertainty           -0.076    15.225    
    SLICE_X101Y304       FDCE (Setup_CFF_SLICEL_C_D)
                                                      0.025    15.250    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]
  -------------------------------------------------------------------
                         required time                         15.250    
                         arrival time                          -5.430    
  -------------------------------------------------------------------
                         slack                                  9.819    

Slack (MET) :             9.864ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.917ns  (logic 0.483ns (25.193%)  route 1.434ns (74.807%))
  Logic Levels:           5  (LUT3=1 LUT5=3 LUT6=1)
  Clock Path Skew:        -0.171ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.633ns = ( 15.636 - 12.002 ) 
    Source Clock Delay      (SCD):    3.382ns
    Clock Pessimism Removal (CPR):    -0.422ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.181ns (routing 0.171ns, distribution 1.010ns)
  Clock Net Delay (Destination): 0.994ns (routing 0.155ns, distribution 0.839ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.181     3.382    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/clk
    SLICE_X100Y300       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y300       FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     3.462 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/Q
                         net (fo=6, routed)           0.372     3.834    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/abort_rd_edge
    SLICE_X102Y301       LUT5 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050     3.884 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/FSM_onehot_current_state[17]_i_1/O
                         net (fo=2, routed)           0.342     4.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_reg_2[0]
    SLICE_X102Y300       LUT5 (Prop_D5LUT_SLICEL_I4_O)
                                                      0.096     4.322 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_2/O
                         net (fo=1, routed)           0.163     4.485    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_2_n_0
    SLICE_X102Y300       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.097     4.582 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_1/O
                         net (fo=24, routed)          0.330     4.912    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state_reg[11]
    SLICE_X101Y299       LUT5 (Prop_E5LUT_SLICEL_I3_O)
                                                      0.070     4.982 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__2/O
                         net (fo=1, routed)           0.176     5.158    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__2_n_0
    SLICE_X101Y299       LUT3 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.090     5.248 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/auto_sl_drdy_i_1/O
                         net (fo=1, routed)           0.051     5.299    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_8
    SLICE_X101Y299       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863    13.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.994    15.636    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X101Y299       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/C
                         clock pessimism             -0.422    15.213    
                         clock uncertainty           -0.076    15.138    
    SLICE_X101Y299       FDCE (Setup_HFF_SLICEL_C_D)
                                                      0.025    15.163    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg
  -------------------------------------------------------------------
                         required time                         15.163    
                         arrival time                          -5.299    
  -------------------------------------------------------------------
                         slack                                  9.864    

Slack (MET) :             9.872ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/inc_addr_r_reg/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.008ns  (logic 0.568ns (28.284%)  route 1.440ns (71.716%))
  Logic Levels:           5  (LUT3=1 LUT5=3 LUT6=1)
  Clock Path Skew:        -0.072ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.678ns = ( 15.680 - 12.002 ) 
    Source Clock Delay      (SCD):    3.382ns
    Clock Pessimism Removal (CPR):    -0.368ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.181ns (routing 0.171ns, distribution 1.010ns)
  Clock Net Delay (Destination): 1.039ns (routing 0.155ns, distribution 0.884ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.181     3.382    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/clk
    SLICE_X100Y300       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y300       FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     3.462 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/Q
                         net (fo=6, routed)           0.372     3.834    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/abort_rd_edge
    SLICE_X102Y301       LUT5 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050     3.884 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/FSM_onehot_current_state[17]_i_1/O
                         net (fo=2, routed)           0.342     4.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_reg_2[0]
    SLICE_X102Y300       LUT5 (Prop_D5LUT_SLICEL_I4_O)
                                                      0.096     4.322 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_2/O
                         net (fo=1, routed)           0.163     4.485    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_2_n_0
    SLICE_X102Y300       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.097     4.582 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_1/O
                         net (fo=24, routed)          0.409     4.991    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state_reg[11]
    SLICE_X104Y302       LUT5 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.145     5.136 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__4/O
                         net (fo=1, routed)           0.095     5.231    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__4_n_0
    SLICE_X104Y302       LUT3 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.100     5.331 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/inc_addr_r_i_1/O
                         net (fo=1, routed)           0.059     5.390    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_9
    SLICE_X104Y302       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/inc_addr_r_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863    13.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.039    15.680    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y302       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/inc_addr_r_reg/C
                         clock pessimism             -0.368    15.312    
                         clock uncertainty           -0.076    15.237    
    SLICE_X104Y302       FDCE (Setup_BFF_SLICEM_C_D)
                                                      0.025    15.262    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/inc_addr_r_reg
  -------------------------------------------------------------------
                         required time                         15.262    
                         arrival time                          -5.390    
  -------------------------------------------------------------------
                         slack                                  9.872    

Slack (MET) :             9.957ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.824ns  (logic 0.541ns (29.656%)  route 1.283ns (70.344%))
  Logic Levels:           5  (LUT4=1 LUT5=3 LUT6=1)
  Clock Path Skew:        -0.171ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.633ns = ( 15.636 - 12.002 ) 
    Source Clock Delay      (SCD):    3.382ns
    Clock Pessimism Removal (CPR):    -0.422ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.181ns (routing 0.171ns, distribution 1.010ns)
  Clock Net Delay (Destination): 0.994ns (routing 0.155ns, distribution 0.839ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.181     3.382    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/clk
    SLICE_X100Y300       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y300       FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     3.462 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/Q
                         net (fo=6, routed)           0.372     3.834    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/abort_rd_edge
    SLICE_X102Y301       LUT5 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050     3.884 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/FSM_onehot_current_state[17]_i_1/O
                         net (fo=2, routed)           0.342     4.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_reg_2[0]
    SLICE_X102Y300       LUT5 (Prop_D5LUT_SLICEL_I4_O)
                                                      0.096     4.322 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_2/O
                         net (fo=1, routed)           0.163     4.485    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_2_n_0
    SLICE_X102Y300       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.097     4.582 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_1/O
                         net (fo=24, routed)          0.330     4.912    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state_reg[11]
    SLICE_X101Y299       LUT5 (Prop_E6LUT_SLICEL_I3_O)
                                                      0.051     4.963 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b1/O
                         net (fo=1, routed)           0.057     5.020    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_16
    SLICE_X101Y299       LUT4 (Prop_F5LUT_SLICEL_I2_O)
                                                      0.167     5.187 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r[1]_i_1/O
                         net (fo=1, routed)           0.019     5.206    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r[1]_i_1_n_0
    SLICE_X101Y299       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863    13.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.994    15.636    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X101Y299       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r_reg[1]/C
                         clock pessimism             -0.422    15.213    
                         clock uncertainty           -0.076    15.138    
    SLICE_X101Y299       FDCE (Setup_FFF2_SLICEL_C_D)
                                                      0.025    15.163    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r_reg[1]
  -------------------------------------------------------------------
                         required time                         15.163    
                         arrival time                          -5.206    
  -------------------------------------------------------------------
                         slack                                  9.957    

Slack (MET) :             9.974ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.836ns  (logic 0.373ns (20.315%)  route 1.463ns (79.685%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        -0.142ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.609ns = ( 15.611 - 12.002 ) 
    Source Clock Delay      (SCD):    3.377ns
    Clock Pessimism Removal (CPR):    -0.374ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.176ns (routing 0.171ns, distribution 1.005ns)
  Clock Net Delay (Destination): 0.970ns (routing 0.155ns, distribution 0.815ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.176     3.377    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X100Y302       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y302       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.456 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[0]/Q
                         net (fo=45, routed)          0.817     4.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[4]
    SLICE_X96Y307        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.053     4.326 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[0]_i_3/O
                         net (fo=1, routed)           0.327     4.653    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[0]_i_3_n_0
    SLICE_X94Y310        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.125     4.778 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[0]_i_2/O
                         net (fo=1, routed)           0.293     5.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[0]_i_2_n_0
    SLICE_X96Y307        LUT5 (Prop_B5LUT_SLICEM_I0_O)
                                                      0.116     5.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[0]_i_1/O
                         net (fo=1, routed)           0.026     5.213    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[0]
    SLICE_X96Y307        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863    13.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.970    15.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y307        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[0]/C
                         clock pessimism             -0.374    15.238    
                         clock uncertainty           -0.076    15.162    
    SLICE_X96Y307        FDRE (Setup_BFF2_SLICEM_C_D)
                                                      0.025    15.187    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[0]
  -------------------------------------------------------------------
                         required time                         15.187    
                         arrival time                          -5.213    
  -------------------------------------------------------------------
                         slack                                  9.974    

Slack (MET) :             9.983ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rst_r_reg[0]/CE
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.812ns  (logic 0.413ns (22.796%)  route 1.399ns (77.204%))
  Logic Levels:           4  (LUT5=3 LUT6=1)
  Clock Path Skew:        -0.072ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.678ns = ( 15.680 - 12.002 ) 
    Source Clock Delay      (SCD):    3.382ns
    Clock Pessimism Removal (CPR):    -0.368ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.181ns (routing 0.171ns, distribution 1.010ns)
  Clock Net Delay (Destination): 1.039ns (routing 0.155ns, distribution 0.884ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.181     3.382    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/clk
    SLICE_X100Y300       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y300       FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     3.462 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/Q
                         net (fo=6, routed)           0.372     3.834    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/abort_rd_edge
    SLICE_X102Y301       LUT5 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050     3.884 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/FSM_onehot_current_state[17]_i_1/O
                         net (fo=2, routed)           0.342     4.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_reg_2[0]
    SLICE_X102Y300       LUT5 (Prop_D5LUT_SLICEL_I4_O)
                                                      0.096     4.322 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_2/O
                         net (fo=1, routed)           0.163     4.485    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_2_n_0
    SLICE_X102Y300       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.097     4.582 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_1/O
                         net (fo=24, routed)          0.338     4.919    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state_reg[11]
    SLICE_X104Y300       LUT5 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.090     5.009 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/sl_rst_r[0]_i_1/O
                         net (fo=2, routed)           0.184     5.194    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode
    SLICE_X104Y300       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rst_r_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863    13.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.039    15.680    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y300       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rst_r_reg[0]/C
                         clock pessimism             -0.368    15.312    
                         clock uncertainty           -0.076    15.237    
    SLICE_X104Y300       FDCE (Setup_DFF2_SLICEM_C_CE)
                                                     -0.060    15.177    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rst_r_reg[0]
  -------------------------------------------------------------------
                         required time                         15.177    
                         arrival time                          -5.194    
  -------------------------------------------------------------------
                         slack                                  9.983    

Slack (MET) :             9.991ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_write_mode_reg/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.879ns  (logic 0.475ns (25.285%)  route 1.404ns (74.715%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        -0.083ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.667ns = ( 15.669 - 12.002 ) 
    Source Clock Delay      (SCD):    3.382ns
    Clock Pessimism Removal (CPR):    -0.368ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.181ns (routing 0.171ns, distribution 1.010ns)
  Clock Net Delay (Destination): 1.028ns (routing 0.155ns, distribution 0.873ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.181     3.382    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/clk
    SLICE_X100Y300       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y300       FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     3.462 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/Q
                         net (fo=6, routed)           0.372     3.834    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/abort_rd_edge
    SLICE_X102Y301       LUT5 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050     3.884 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/FSM_onehot_current_state[17]_i_1/O
                         net (fo=2, routed)           0.342     4.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_reg_2[0]
    SLICE_X102Y300       LUT5 (Prop_D5LUT_SLICEL_I4_O)
                                                      0.096     4.322 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_2/O
                         net (fo=1, routed)           0.163     4.485    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_2_n_0
    SLICE_X102Y300       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.097     4.582 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_1/O
                         net (fo=24, routed)          0.469     5.050    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state_reg[11]
    SLICE_X103Y301       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.152     5.202 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_write_mode_i_1/O
                         net (fo=1, routed)           0.058     5.260    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_4
    SLICE_X103Y301       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_write_mode_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863    13.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.028    15.669    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X103Y301       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_write_mode_reg/C
                         clock pessimism             -0.368    15.302    
                         clock uncertainty           -0.076    15.226    
    SLICE_X103Y301       FDCE (Setup_HFF_SLICEM_C_D)
                                                      0.025    15.251    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_write_mode_reg
  -------------------------------------------------------------------
                         required time                         15.251    
                         arrival time                          -5.260    
  -------------------------------------------------------------------
                         slack                                  9.991    

Slack (MET) :             10.001ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[12]/CE
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.725ns  (logic 0.221ns (12.810%)  route 1.504ns (87.190%))
  Logic Levels:           2  (LUT6=2)
  Clock Path Skew:        -0.141ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.609ns = ( 15.612 - 12.002 ) 
    Source Clock Delay      (SCD):    3.377ns
    Clock Pessimism Removal (CPR):    -0.374ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.176ns (routing 0.171ns, distribution 1.005ns)
  Clock Net Delay (Destination): 0.970ns (routing 0.155ns, distribution 0.815ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.176     3.377    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X100Y304       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y304       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.456 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[16]/Q
                         net (fo=3, routed)           0.507     3.963    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[20]
    SLICE_X96Y304        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.090     4.053 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_den_r_i_2/O
                         net (fo=3, routed)           0.046     4.099    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_den_r_i_2_n_0
    SLICE_X96Y304        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.052     4.151 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test[15]_i_1/O
                         net (fo=16, routed)          0.951     5.102    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test0
    SLICE_X95Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[12]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863    13.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.970    15.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[12]/C
                         clock pessimism             -0.374    15.238    
                         clock uncertainty           -0.076    15.163    
    SLICE_X95Y312        FDRE (Setup_HFF_SLICEL_C_CE)
                                                     -0.060    15.103    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[12]
  -------------------------------------------------------------------
                         required time                         15.103    
                         arrival time                          -5.102    
  -------------------------------------------------------------------
                         slack                                 10.001    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.022ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[18]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.253ns  (logic 0.124ns (48.971%)  route 0.129ns (51.029%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.169ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.380ns
    Source Clock Delay      (SCD):    3.633ns
    Clock Pessimism Removal (CPR):    -0.422ns
  Clock Net Delay (Source):      0.994ns (routing 0.155ns, distribution 0.839ns)
  Clock Net Delay (Destination): 1.179ns (routing 0.171ns, distribution 1.008ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.639 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.994     3.633    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X101Y299       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y299       FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     3.691 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/Q
                         net (fo=12, routed)          0.109     3.801    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/auto_sl_drdy
    SLICE_X102Y302       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.066     3.867 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state[18]_i_1/O
                         net (fo=1, routed)           0.020     3.887    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_20
    SLICE_X102Y302       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[18]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.179     3.380    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X102Y302       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[18]/C
                         clock pessimism              0.422     3.802    
    SLICE_X102Y302       FDCE (Hold_DFF2_SLICEL_C_D)
                                                      0.062     3.864    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[18]
  -------------------------------------------------------------------
                         required time                         -3.864    
                         arrival time                           3.887    
  -------------------------------------------------------------------
                         slack                                  0.022    

Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[10]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.272ns  (logic 0.150ns (55.206%)  route 0.122ns (44.794%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.180ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.391ns
    Source Clock Delay      (SCD):    3.633ns
    Clock Pessimism Removal (CPR):    -0.422ns
  Clock Net Delay (Source):      0.994ns (routing 0.155ns, distribution 0.839ns)
  Clock Net Delay (Destination): 1.190ns (routing 0.171ns, distribution 1.019ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.639 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.994     3.633    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/wr_clk
    SLICE_X102Y299       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y299       FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     3.692 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/Q
                         net (fo=8, routed)           0.113     3.805    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/FULL_O
    SLICE_X101Y300       LUT2 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.091     3.896 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/FSM_onehot_current_state[10]_i_1/O
                         net (fo=1, routed)           0.009     3.905    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/D[0]
    SLICE_X101Y300       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.190     3.391    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X101Y300       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[10]/C
                         clock pessimism              0.422     3.813    
    SLICE_X101Y300       FDCE (Hold_DFF2_SLICEL_C_D)
                                                      0.062     3.875    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[10]
  -------------------------------------------------------------------
                         required time                         -3.875    
                         arrival time                           3.905    
  -------------------------------------------------------------------
                         slack                                  0.030    

Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[11]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.272ns  (logic 0.150ns (55.206%)  route 0.122ns (44.794%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.180ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.391ns
    Source Clock Delay      (SCD):    3.633ns
    Clock Pessimism Removal (CPR):    -0.422ns
  Clock Net Delay (Source):      0.994ns (routing 0.155ns, distribution 0.839ns)
  Clock Net Delay (Destination): 1.190ns (routing 0.171ns, distribution 1.019ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.639 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.994     3.633    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/wr_clk
    SLICE_X102Y299       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y299       FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     3.692 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/Q
                         net (fo=8, routed)           0.113     3.805    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FULL_O
    SLICE_X101Y300       LUT3 (Prop_C5LUT_SLICEL_I0_O)
                                                      0.091     3.896 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state[11]_i_1/O
                         net (fo=1, routed)           0.009     3.905    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state[11]_i_1_n_0
    SLICE_X101Y300       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.190     3.391    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X101Y300       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[11]/C
                         clock pessimism              0.422     3.813    
    SLICE_X101Y300       FDCE (Hold_CFF2_SLICEL_C_D)
                                                      0.062     3.875    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[11]
  -------------------------------------------------------------------
                         required time                         -3.875    
                         arrival time                           3.905    
  -------------------------------------------------------------------
                         slack                                  0.030    

Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[62]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[62]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.082ns  (logic 0.039ns (47.561%)  route 0.043ns (52.439%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.999ns
    Source Clock Delay      (SCD):    2.173ns
    Clock Pessimism Removal (CPR):    -0.180ns
  Clock Net Delay (Source):      0.624ns (routing 0.096ns, distribution 0.528ns)
  Clock Net Delay (Destination): 0.714ns (routing 0.108ns, distribution 0.606ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.624     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y310        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[62]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y310        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     2.212 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[62]/Q
                         net (fo=2, routed)           0.043     2.255    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[62]
    SLICE_X95Y310        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[62]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.714     1.999    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y310        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[62]/C
                         clock pessimism              0.180     2.179    
    SLICE_X95Y310        FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.046     2.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[62]
  -------------------------------------------------------------------
                         required time                         -2.225    
                         arrival time                           2.255    
  -------------------------------------------------------------------
                         slack                                  0.030    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.083ns  (logic 0.039ns (47.074%)  route 0.044ns (52.926%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.999ns
    Source Clock Delay      (SCD):    2.174ns
    Clock Pessimism Removal (CPR):    -0.181ns
  Clock Net Delay (Source):      0.625ns (routing 0.096ns, distribution 0.529ns)
  Clock Net Delay (Destination): 0.714ns (routing 0.108ns, distribution 0.606ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.625     2.174    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y305        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]/Q
                         net (fo=2, routed)           0.044     2.256    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[7]
    SLICE_X96Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.714     1.999    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]/C
                         clock pessimism              0.181     2.180    
    SLICE_X96Y305        FDRE (Hold_HFF_SLICEM_C_D)
                                                      0.046     2.226    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]
  -------------------------------------------------------------------
                         required time                         -2.226    
                         arrival time                           2.256    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.035ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[8]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.282ns  (logic 0.081ns (28.698%)  route 0.201ns (71.302%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.187ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.396ns
    Source Clock Delay      (SCD):    3.631ns
    Clock Pessimism Removal (CPR):    -0.422ns
  Clock Net Delay (Source):      0.992ns (routing 0.155ns, distribution 0.837ns)
  Clock Net Delay (Destination): 1.195ns (routing 0.171ns, distribution 1.024ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.639 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.992     3.631    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X101Y299       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y299       FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.059     3.690 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[5]/Q
                         net (fo=6, routed)           0.177     3.868    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/Q[2]
    SLICE_X101Y300       LUT6 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.022     3.890 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state[8]_i_1/O
                         net (fo=1, routed)           0.024     3.914    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_24
    SLICE_X101Y300       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.195     3.396    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X101Y300       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[8]/C
                         clock pessimism              0.422     3.818    
    SLICE_X101Y300       FDCE (Hold_FFF_SLICEL_C_D)
                                                      0.060     3.878    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[8]
  -------------------------------------------------------------------
                         required time                         -3.878    
                         arrival time                           3.914    
  -------------------------------------------------------------------
                         slack                                  0.035    

Slack (MET) :             0.037ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/count_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.090ns  (logic 0.060ns (66.667%)  route 0.030ns (33.333%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.037ns
    Source Clock Delay      (SCD):    2.209ns
    Clock Pessimism Removal (CPR):    -0.178ns
  Clock Net Delay (Source):      0.660ns (routing 0.096ns, distribution 0.564ns)
  Clock Net Delay (Destination): 0.752ns (routing 0.108ns, distribution 0.644ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.660     2.209    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/clk
    SLICE_X101Y303       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/count_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y303       FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     2.248 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/count_reg[6]/Q
                         net (fo=2, routed)           0.023     2.271    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/count_reg[6]
    SLICE_X101Y303       LUT2 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.021     2.292 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_i_1/O
                         net (fo=1, routed)           0.007     2.299    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_i_1_n_0
    SLICE_X101Y303       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.752     2.037    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/clk
    SLICE_X101Y303       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg/C
                         clock pessimism              0.178     2.215    
    SLICE_X101Y303       FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.047     2.262    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg
  -------------------------------------------------------------------
                         required time                         -2.262    
                         arrival time                           2.299    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.136ns  (logic 0.061ns (44.853%)  route 0.075ns (55.147%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.052ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.000ns
    Source Clock Delay      (SCD):    2.172ns
    Clock Pessimism Removal (CPR):    -0.224ns
  Clock Net Delay (Source):      0.623ns (routing 0.096ns, distribution 0.527ns)
  Clock Net Delay (Destination): 0.715ns (routing 0.108ns, distribution 0.607ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.623     2.172    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y312        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.211 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[12]/Q
                         net (fo=1, routed)           0.049     2.260    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg_n_0_[12]
    SLICE_X96Y312        LUT3 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.022     2.282 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r[12]_i_1/O
                         net (fo=1, routed)           0.026     2.308    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/p_0_in[12]
    SLICE_X96Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.715     2.000    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[12]/C
                         clock pessimism              0.224     2.224    
    SLICE_X96Y312        FDRE (Hold_DFF_SLICEM_C_D)
                                                      0.046     2.270    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[12]
  -------------------------------------------------------------------
                         required time                         -2.270    
                         arrival time                           2.308    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[23]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.090ns  (logic 0.037ns (41.111%)  route 0.053ns (58.889%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.999ns
    Source Clock Delay      (SCD):    2.174ns
    Clock Pessimism Removal (CPR):    -0.181ns
  Clock Net Delay (Source):      0.625ns (routing 0.096ns, distribution 0.529ns)
  Clock Net Delay (Destination): 0.714ns (routing 0.108ns, distribution 0.606ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.625     2.174    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y305        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.211 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[23]/Q
                         net (fo=2, routed)           0.053     2.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[23]
    SLICE_X96Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[23]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.714     1.999    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[23]/C
                         clock pessimism              0.181     2.180    
    SLICE_X96Y305        FDRE (Hold_FFF_SLICEM_C_D)
                                                      0.046     2.226    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[23]
  -------------------------------------------------------------------
                         required time                         -2.226    
                         arrival time                           2.264    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.045ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[33]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[33]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.098ns  (logic 0.040ns (40.816%)  route 0.058ns (59.184%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.996ns
    Source Clock Delay      (SCD):    2.169ns
    Clock Pessimism Removal (CPR):    -0.179ns
  Clock Net Delay (Source):      0.620ns (routing 0.096ns, distribution 0.524ns)
  Clock Net Delay (Destination): 0.711ns (routing 0.108ns, distribution 0.603ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.620     2.169    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y309        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[33]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y309        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.040     2.209 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[33]/Q
                         net (fo=2, routed)           0.058     2.267    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[33]
    SLICE_X95Y309        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[33]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.711     1.996    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y309        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[33]/C
                         clock pessimism              0.179     2.175    
    SLICE_X95Y309        FDRE (Hold_FFF2_SLICEL_C_D)
                                                      0.047     2.222    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[33]
  -------------------------------------------------------------------
                         required time                         -2.222    
                         arrival time                           2.267    
  -------------------------------------------------------------------
                         slack                                  0.045    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mmcm_clkout5
Waveform(ns):       { 0.000 6.001 }
Period(ns):         12.002
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     BUFGCE/I            n/a            1.290         12.002      10.712     BUFGCE_X0Y102  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/I
Min Period        n/a     MMCME4_ADV/CLKOUT5  n/a            1.071         12.002      10.931     MMCM_X0Y4      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC_D1/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y298  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout6

Setup :            0  Failing Endpoints,  Worst Slack        0.768ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.014ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.972ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.768ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        5.100ns  (logic 0.745ns (14.609%)  route 4.355ns (85.391%))
  Logic Levels:           6  (LUT2=1 LUT5=1 LUT6=3 MUXF7=1)
  Clock Path Skew:        -0.090ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.509ns = ( 10.510 - 6.001 ) 
    Source Clock Delay      (SCD):    4.311ns
    Clock Pessimism Removal (CPR):    -0.288ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.084ns (routing 0.799ns, distribution 1.285ns)
  Clock Net Delay (Destination): 1.850ns (routing 0.726ns, distribution 1.124ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.084     4.311    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y350        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y350        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     4.391 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/Q
                         net (fo=38, routed)          0.622     5.013    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[8]
    SLICE_X81Y345        LUT2 (Prop_C5LUT_SLICEL_I1_O)
                                                      0.158     5.171 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_26/O
                         net (fo=7, routed)           0.350     5.521    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_26_n_0
    SLICE_X84Y347        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.097     5.618 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_11/O
                         net (fo=2, routed)           0.251     5.868    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_11_n_0
    SLICE_X81Y346        LUT5 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.124     5.992 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_9/O
                         net (fo=64, routed)          1.944     7.937    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_9_n_0
    SLICE_X81Y201        LUT6 (Prop_E6LUT_SLICEL_I3_O)
                                                      0.099     8.036 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[4]_i_4/O
                         net (fo=1, routed)           1.149     9.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[4]_i_4_n_0
    SLICE_X81Y316        LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.124     9.309 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[4]_i_2/O
                         net (fo=1, routed)           0.009     9.318    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[4]_i_2_n_0
    SLICE_X81Y316        MUXF7 (Prop_F7MUX_AB_SLICEL_I0_O)
                                                      0.063     9.381 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[4]_i_1/O
                         net (fo=1, routed)           0.030     9.411    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[4]_i_1_n_0
    SLICE_X81Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     7.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     8.636    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.660 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.850    10.510    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[4]/C
                         clock pessimism             -0.288    10.222    
                         clock uncertainty           -0.068    10.153    
    SLICE_X81Y316        FDRE (Setup_BFF_SLICEL_C_D)
                                                      0.025    10.178    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[4]
  -------------------------------------------------------------------
                         required time                         10.178    
                         arrival time                          -9.411    
  -------------------------------------------------------------------
                         slack                                  0.768    

Slack (MET) :             0.896ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.974ns  (logic 0.771ns (15.500%)  route 4.203ns (84.500%))
  Logic Levels:           6  (LUT2=1 LUT5=1 LUT6=3 MUXF7=1)
  Clock Path Skew:        -0.088ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.511ns = ( 10.512 - 6.001 ) 
    Source Clock Delay      (SCD):    4.311ns
    Clock Pessimism Removal (CPR):    -0.288ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.084ns (routing 0.799ns, distribution 1.285ns)
  Clock Net Delay (Destination): 1.852ns (routing 0.726ns, distribution 1.126ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.084     4.311    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y350        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y350        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     4.391 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/Q
                         net (fo=38, routed)          0.622     5.013    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[8]
    SLICE_X81Y345        LUT2 (Prop_C5LUT_SLICEL_I1_O)
                                                      0.158     5.171 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_26/O
                         net (fo=7, routed)           0.350     5.521    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_26_n_0
    SLICE_X84Y347        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.097     5.618 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_11/O
                         net (fo=2, routed)           0.251     5.868    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_11_n_0
    SLICE_X81Y346        LUT5 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.124     5.992 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_9/O
                         net (fo=64, routed)          1.744     7.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_9_n_0
    SLICE_X81Y191        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.124     7.860 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[8]_i_4/O
                         net (fo=1, routed)           1.196     9.056    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[8]_i_4_n_0
    SLICE_X81Y307        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.124     9.180 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[8]_i_2/O
                         net (fo=1, routed)           0.010     9.190    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[8]_i_2_n_0
    SLICE_X81Y307        MUXF7 (Prop_F7MUX_GH_SLICEL_I0_O)
                                                      0.064     9.254 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[8]_i_1/O
                         net (fo=1, routed)           0.031     9.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[8]_i_1_n_0
    SLICE_X81Y307        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     7.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     8.636    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.660 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.852    10.512    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y307        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[8]/C
                         clock pessimism             -0.288    10.224    
                         clock uncertainty           -0.068    10.156    
    SLICE_X81Y307        FDRE (Setup_HFF_SLICEL_C_D)
                                                      0.025    10.181    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[8]
  -------------------------------------------------------------------
                         required time                         10.181    
                         arrival time                          -9.285    
  -------------------------------------------------------------------
                         slack                                  0.896    

Slack (MET) :             0.913ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.963ns  (logic 0.662ns (13.339%)  route 4.301ns (86.661%))
  Logic Levels:           6  (LUT2=1 LUT5=1 LUT6=3 MUXF7=1)
  Clock Path Skew:        -0.082ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.517ns = ( 10.518 - 6.001 ) 
    Source Clock Delay      (SCD):    4.311ns
    Clock Pessimism Removal (CPR):    -0.288ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.084ns (routing 0.799ns, distribution 1.285ns)
  Clock Net Delay (Destination): 1.858ns (routing 0.726ns, distribution 1.132ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.084     4.311    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y350        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y350        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     4.391 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/Q
                         net (fo=38, routed)          0.622     5.013    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[8]
    SLICE_X81Y345        LUT2 (Prop_C5LUT_SLICEL_I1_O)
                                                      0.158     5.171 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_26/O
                         net (fo=7, routed)           0.350     5.521    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_26_n_0
    SLICE_X84Y347        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.097     5.618 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_11/O
                         net (fo=2, routed)           0.251     5.868    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_11_n_0
    SLICE_X81Y346        LUT5 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.124     5.992 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_9/O
                         net (fo=64, routed)          1.942     7.935    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_9_n_0
    SLICE_X81Y201        LUT6 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.097     8.032 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_4/O
                         net (fo=1, routed)           1.079     9.111    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_4_n_0
    SLICE_X82Y307        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     9.148 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_2/O
                         net (fo=1, routed)           0.025     9.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_2_n_0
    SLICE_X82Y307        MUXF7 (Prop_F7MUX_CD_SLICEM_I0_O)
                                                      0.069     9.242 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[15]_i_1/O
                         net (fo=1, routed)           0.032     9.274    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[15]_i_1_n_0
    SLICE_X82Y307        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     7.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     8.636    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.660 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.858    10.518    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y307        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[15]/C
                         clock pessimism             -0.288    10.230    
                         clock uncertainty           -0.068    10.161    
    SLICE_X82Y307        FDRE (Setup_DFF_SLICEM_C_D)
                                                      0.025    10.186    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[15]
  -------------------------------------------------------------------
                         required time                         10.186    
                         arrival time                          -9.274    
  -------------------------------------------------------------------
                         slack                                  0.913    

Slack (MET) :             0.932ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.934ns  (logic 0.791ns (16.032%)  route 4.143ns (83.968%))
  Logic Levels:           6  (LUT2=1 LUT5=1 LUT6=3 MUXF7=1)
  Clock Path Skew:        -0.092ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.507ns = ( 10.508 - 6.001 ) 
    Source Clock Delay      (SCD):    4.311ns
    Clock Pessimism Removal (CPR):    -0.288ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.084ns (routing 0.799ns, distribution 1.285ns)
  Clock Net Delay (Destination): 1.848ns (routing 0.726ns, distribution 1.122ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.084     4.311    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y350        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y350        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     4.391 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/Q
                         net (fo=38, routed)          0.622     5.013    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[8]
    SLICE_X81Y345        LUT2 (Prop_C5LUT_SLICEL_I1_O)
                                                      0.158     5.171 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_26/O
                         net (fo=7, routed)           0.350     5.521    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_26_n_0
    SLICE_X84Y347        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.097     5.618 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_11/O
                         net (fo=2, routed)           0.251     5.868    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_11_n_0
    SLICE_X81Y346        LUT5 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.124     5.992 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_9/O
                         net (fo=64, routed)          1.686     7.679    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_9_n_0
    SLICE_X82Y201        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.123     7.802 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[0]_i_4/O
                         net (fo=1, routed)           1.194     8.996    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[0]_i_4_n_0
    SLICE_X81Y318        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.146     9.142 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[0]_i_2/O
                         net (fo=1, routed)           0.009     9.151    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[0]_i_2_n_0
    SLICE_X81Y318        MUXF7 (Prop_F7MUX_CD_SLICEL_I0_O)
                                                      0.063     9.214 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[0]_i_1/O
                         net (fo=1, routed)           0.031     9.245    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[0]_i_1_n_0
    SLICE_X81Y318        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     7.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     8.636    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.660 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.848    10.508    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y318        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[0]/C
                         clock pessimism             -0.288    10.220    
                         clock uncertainty           -0.068    10.151    
    SLICE_X81Y318        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025    10.176    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[0]
  -------------------------------------------------------------------
                         required time                         10.176    
                         arrival time                          -9.245    
  -------------------------------------------------------------------
                         slack                                  0.932    

Slack (MET) :             0.956ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.461ns  (logic 0.373ns (8.362%)  route 4.088ns (91.638%))
  Logic Levels:           4  (LUT2=3 LUT6=1)
  Clock Path Skew:        -0.174ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.445ns = ( 10.446 - 6.001 ) 
    Source Clock Delay      (SCD):    4.260ns
    Clock Pessimism Removal (CPR):    -0.359ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.033ns (routing 0.799ns, distribution 1.234ns)
  Clock Net Delay (Destination): 1.786ns (routing 0.726ns, distribution 1.060ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.033     4.260    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/LMB_Clk
    SLICE_X93Y345        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y345        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     4.340 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/Q
                         net (fo=1, routed)           0.131     4.471    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/Sl_Rdy
    SLICE_X93Y345        LUT2 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.039     4.510 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/Sl_Ready_INST_0/O
                         net (fo=33, routed)          0.927     5.437    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0/Sl_Ready[0]
    SLICE_X92Y314        LUT2 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.104     5.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0/LMB_Ready_INST_0/O
                         net (fo=80, routed)          0.694     6.236    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/IReady
    SLICE_X94Y349        LUT6 (Prop_A6LUT_SLICEM_I5_O)
                                                      0.100     6.336 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/I_AS_INST_0/O
                         net (fo=5, routed)           0.174     6.509    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/enb
    SLICE_X92Y349        LUT2 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.050     6.559 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram_i_2/O
                         net (fo=16, routed)          2.161     8.720    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/ENB_I
    RAMB36_X9Y46         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     7.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     8.636    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.660 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.786    10.446    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/clkb
    RAMB36_X9Y46         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.359    10.087    
                         clock uncertainty           -0.068    10.018    
    RAMB36_X9Y46         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ENBWREN)
                                                     -0.342     9.676    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                          9.676    
                         arrival time                          -8.720    
  -------------------------------------------------------------------
                         slack                                  0.956    

Slack (MET) :             0.991ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.905ns  (logic 0.757ns (15.433%)  route 4.148ns (84.567%))
  Logic Levels:           7  (LUT2=1 LUT6=4 MUXF7=2)
  Clock Path Skew:        -0.062ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.514ns = ( 10.515 - 6.001 ) 
    Source Clock Delay      (SCD):    4.288ns
    Clock Pessimism Removal (CPR):    -0.288ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.061ns (routing 0.799ns, distribution 1.262ns)
  Clock Net Delay (Destination): 1.855ns (routing 0.726ns, distribution 1.129ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.061     4.288    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y349        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y349        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.367 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[1]/Q
                         net (fo=33, routed)          0.705     5.072    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[1]
    SLICE_X81Y356        LUT2 (Prop_A5LUT_SLICEL_I0_O)
                                                      0.069     5.141 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[2]_INST_0_i_12/O
                         net (fo=5, routed)           0.242     5.383    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[2]_INST_0_i_12_n_0
    SLICE_X81Y350        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.088     5.471 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_15/O
                         net (fo=1, routed)           0.010     5.481    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_15_n_0
    SLICE_X81Y350        MUXF7 (Prop_F7MUX_CD_SLICEL_I1_O)
                                                      0.064     5.545 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_9/O
                         net (fo=1, routed)           0.149     5.694    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_9_n_0
    SLICE_X81Y352        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.150     5.844 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_2/O
                         net (fo=65, routed)          1.865     7.709    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_2_n_0
    SLICE_X81Y196        LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.122     7.831 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[12]_i_4/O
                         net (fo=1, routed)           1.137     8.968    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[12]_i_4_n_0
    SLICE_X81Y305        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.122     9.090 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[12]_i_2/O
                         net (fo=1, routed)           0.009     9.099    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[12]_i_2_n_0
    SLICE_X81Y305        MUXF7 (Prop_F7MUX_CD_SLICEL_I0_O)
                                                      0.063     9.162 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[12]_i_1/O
                         net (fo=1, routed)           0.031     9.193    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[12]_i_1_n_0
    SLICE_X81Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     7.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     8.636    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.660 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.855    10.515    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[12]/C
                         clock pessimism             -0.288    10.227    
                         clock uncertainty           -0.068    10.158    
    SLICE_X81Y305        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025    10.183    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[12]
  -------------------------------------------------------------------
                         required time                         10.183    
                         arrival time                          -9.193    
  -------------------------------------------------------------------
                         slack                                  0.991    

Slack (MET) :             0.995ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.876ns  (logic 0.796ns (16.323%)  route 4.080ns (83.677%))
  Logic Levels:           6  (LUT2=1 LUT5=1 LUT6=3 MUXF7=1)
  Clock Path Skew:        -0.086ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.513ns = ( 10.514 - 6.001 ) 
    Source Clock Delay      (SCD):    4.311ns
    Clock Pessimism Removal (CPR):    -0.288ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.084ns (routing 0.799ns, distribution 1.285ns)
  Clock Net Delay (Destination): 1.854ns (routing 0.726ns, distribution 1.128ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.084     4.311    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y350        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y350        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     4.391 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/Q
                         net (fo=38, routed)          0.622     5.013    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[8]
    SLICE_X81Y345        LUT2 (Prop_C5LUT_SLICEL_I1_O)
                                                      0.158     5.171 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_26/O
                         net (fo=7, routed)           0.350     5.521    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_26_n_0
    SLICE_X84Y347        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.097     5.618 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_11/O
                         net (fo=2, routed)           0.251     5.868    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_11_n_0
    SLICE_X81Y346        LUT5 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.124     5.992 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_9/O
                         net (fo=64, routed)          1.644     7.636    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_9_n_0
    SLICE_X81Y195        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.146     7.782 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[2]_i_4/O
                         net (fo=1, routed)           1.157     8.939    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[2]_i_4_n_0
    SLICE_X82Y315        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.122     9.061 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[2]_i_2/O
                         net (fo=1, routed)           0.025     9.086    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[2]_i_2_n_0
    SLICE_X82Y315        MUXF7 (Prop_F7MUX_CD_SLICEM_I0_O)
                                                      0.069     9.155 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]_i_1/O
                         net (fo=1, routed)           0.032     9.187    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]_i_1_n_0
    SLICE_X82Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     7.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     8.636    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.660 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.854    10.514    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]/C
                         clock pessimism             -0.288    10.226    
                         clock uncertainty           -0.068    10.157    
    SLICE_X82Y315        FDRE (Setup_DFF_SLICEM_C_D)
                                                      0.025    10.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]
  -------------------------------------------------------------------
                         required time                         10.182    
                         arrival time                          -9.187    
  -------------------------------------------------------------------
                         slack                                  0.995    

Slack (MET) :             1.000ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.868ns  (logic 0.647ns (13.291%)  route 4.221ns (86.709%))
  Logic Levels:           6  (LUT2=1 LUT5=1 LUT6=3 MUXF7=1)
  Clock Path Skew:        -0.090ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.509ns = ( 10.510 - 6.001 ) 
    Source Clock Delay      (SCD):    4.311ns
    Clock Pessimism Removal (CPR):    -0.288ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.084ns (routing 0.799ns, distribution 1.285ns)
  Clock Net Delay (Destination): 1.850ns (routing 0.726ns, distribution 1.124ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.084     4.311    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y350        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y350        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     4.391 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/Q
                         net (fo=38, routed)          0.622     5.013    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[8]
    SLICE_X81Y345        LUT2 (Prop_C5LUT_SLICEL_I1_O)
                                                      0.158     5.171 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_26/O
                         net (fo=7, routed)           0.350     5.521    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_26_n_0
    SLICE_X84Y347        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.097     5.618 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_11/O
                         net (fo=2, routed)           0.251     5.868    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_11_n_0
    SLICE_X81Y346        LUT5 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.124     5.992 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_9/O
                         net (fo=64, routed)          1.888     7.880    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_9_n_0
    SLICE_X81Y201        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.089     7.969 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[13]_i_4/O
                         net (fo=1, routed)           1.071     9.040    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[13]_i_4_n_0
    SLICE_X81Y316        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.036     9.076 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[13]_i_2/O
                         net (fo=1, routed)           0.009     9.085    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[13]_i_2_n_0
    SLICE_X81Y316        MUXF7 (Prop_F7MUX_CD_SLICEL_I0_O)
                                                      0.063     9.148 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[13]_i_1/O
                         net (fo=1, routed)           0.031     9.179    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[13]_i_1_n_0
    SLICE_X81Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     7.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     8.636    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.660 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.850    10.510    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[13]/C
                         clock pessimism             -0.288    10.222    
                         clock uncertainty           -0.068    10.153    
    SLICE_X81Y316        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025    10.178    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[13]
  -------------------------------------------------------------------
                         required time                         10.178    
                         arrival time                          -9.179    
  -------------------------------------------------------------------
                         slack                                  1.000    

Slack (MET) :             1.010ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.407ns  (logic 0.373ns (8.464%)  route 4.034ns (91.536%))
  Logic Levels:           4  (LUT2=3 LUT6=1)
  Clock Path Skew:        -0.173ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.446ns = ( 10.447 - 6.001 ) 
    Source Clock Delay      (SCD):    4.260ns
    Clock Pessimism Removal (CPR):    -0.359ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.033ns (routing 0.799ns, distribution 1.234ns)
  Clock Net Delay (Destination): 1.787ns (routing 0.726ns, distribution 1.061ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.033     4.260    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/LMB_Clk
    SLICE_X93Y345        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y345        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     4.340 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/Q
                         net (fo=1, routed)           0.131     4.471    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/Sl_Rdy
    SLICE_X93Y345        LUT2 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.039     4.510 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/Sl_Ready_INST_0/O
                         net (fo=33, routed)          0.927     5.437    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0/Sl_Ready[0]
    SLICE_X92Y314        LUT2 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.104     5.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0/LMB_Ready_INST_0/O
                         net (fo=80, routed)          0.694     6.236    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/IReady
    SLICE_X94Y349        LUT6 (Prop_A6LUT_SLICEM_I5_O)
                                                      0.100     6.336 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/I_AS_INST_0/O
                         net (fo=5, routed)           0.174     6.509    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/enb
    SLICE_X92Y349        LUT2 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.050     6.559 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram_i_2/O
                         net (fo=16, routed)          2.108     8.667    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/ENB_I
    RAMB36_X9Y47         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     7.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     8.636    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.660 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.787    10.447    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/clkb
    RAMB36_X9Y47         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.359    10.088    
                         clock uncertainty           -0.068    10.019    
    RAMB36_X9Y47         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ENBWREN)
                                                     -0.342     9.677    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                          9.677    
                         arrival time                          -8.667    
  -------------------------------------------------------------------
                         slack                                  1.010    

Slack (MET) :             1.062ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.807ns  (logic 0.711ns (14.792%)  route 4.096ns (85.208%))
  Logic Levels:           6  (LUT2=1 LUT5=1 LUT6=3 MUXF7=1)
  Clock Path Skew:        -0.089ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.510ns = ( 10.511 - 6.001 ) 
    Source Clock Delay      (SCD):    4.311ns
    Clock Pessimism Removal (CPR):    -0.288ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.084ns (routing 0.799ns, distribution 1.285ns)
  Clock Net Delay (Destination): 1.851ns (routing 0.726ns, distribution 1.125ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.084     4.311    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y350        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y350        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     4.391 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/Q
                         net (fo=38, routed)          0.622     5.013    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[8]
    SLICE_X81Y345        LUT2 (Prop_C5LUT_SLICEL_I1_O)
                                                      0.158     5.171 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_26/O
                         net (fo=7, routed)           0.350     5.521    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_26_n_0
    SLICE_X84Y347        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.097     5.618 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_11/O
                         net (fo=2, routed)           0.251     5.868    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_11_n_0
    SLICE_X81Y346        LUT5 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.124     5.992 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_9/O
                         net (fo=64, routed)          1.888     7.880    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_9_n_0
    SLICE_X81Y201        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.090     7.970 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[11]_i_4/O
                         net (fo=1, routed)           0.946     8.916    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[11]_i_4_n_0
    SLICE_X81Y314        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.099     9.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[11]_i_2/O
                         net (fo=1, routed)           0.009     9.024    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[11]_i_2_n_0
    SLICE_X81Y314        MUXF7 (Prop_F7MUX_CD_SLICEL_I0_O)
                                                      0.063     9.087 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[11]_i_1/O
                         net (fo=1, routed)           0.031     9.118    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[11]_i_1_n_0
    SLICE_X81Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     7.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     8.636    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.660 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.851    10.511    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[11]/C
                         clock pessimism             -0.288    10.223    
                         clock uncertainty           -0.068    10.154    
    SLICE_X81Y314        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025    10.179    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[11]
  -------------------------------------------------------------------
                         required time                         10.179    
                         arrival time                          -9.118    
  -------------------------------------------------------------------
                         slack                                  1.062    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.014ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/if_pc_reg[9]/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][9]_srl4/D
                            (rising edge-triggered cell SRL16E clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.173ns  (logic 0.060ns (34.601%)  route 0.113ns (65.399%))
  Logic Levels:           0  
  Clock Path Skew:        0.105ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.285ns
    Source Clock Delay      (SCD):    4.468ns
    Clock Pessimism Removal (CPR):    -0.288ns
  Clock Net Delay (Source):      1.809ns (routing 0.726ns, distribution 1.083ns)
  Clock Net Delay (Destination): 2.058ns (routing 0.799ns, distribution 1.259ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     2.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.809     4.468    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/Clk
    SLICE_X93Y350        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/if_pc_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y350        FDSE (Prop_GFF2_SLICEM_C_Q)
                                                      0.060     4.528 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/if_pc_reg[9]/Q
                         net (fo=4, routed)           0.113     4.641    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/S107_in
    SLICE_X94Y351        SRL16E                                       r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][9]_srl4/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.058     4.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/Clk
    SLICE_X94Y351        SRL16E                                       r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][9]_srl4/CLK
                         clock pessimism              0.288     4.572    
    SLICE_X94Y351        SRL16E (Hold_B5LUT_SLICEM_CLK_D)
                                                      0.055     4.627    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][9]_srl4
  -------------------------------------------------------------------
                         required time                         -4.627    
                         arrival time                           4.641    
  -------------------------------------------------------------------
                         slack                                  0.014    

Slack (MET) :             0.016ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.125ns  (logic 0.058ns (46.400%)  route 0.067ns (53.600%))
  Logic Levels:           0  
  Clock Path Skew:        0.047ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.285ns
    Source Clock Delay      (SCD):    4.478ns
    Clock Pessimism Removal (CPR):    -0.240ns
  Clock Net Delay (Source):      1.819ns (routing 0.726ns, distribution 1.093ns)
  Clock Net Delay (Destination): 2.058ns (routing 0.799ns, distribution 1.259ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     2.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.819     4.478    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Clk
    SLICE_X91Y344        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y344        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.058     4.536 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[15]/Q
                         net (fo=1, routed)           0.067     4.603    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_ub[15]
    SLICE_X91Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.058     4.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X91Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[15]/C
                         clock pessimism              0.240     4.525    
    SLICE_X91Y343        FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.062     4.587    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[15]
  -------------------------------------------------------------------
                         required time                         -4.587    
                         arrival time                           4.603    
  -------------------------------------------------------------------
                         slack                                  0.016    

Slack (MET) :             0.022ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Address_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.193ns  (logic 0.058ns (30.052%)  route 0.135ns (69.948%))
  Logic Levels:           0  
  Clock Path Skew:        0.109ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.311ns
    Source Clock Delay      (SCD):    4.490ns
    Clock Pessimism Removal (CPR):    -0.288ns
  Clock Net Delay (Source):      1.831ns (routing 0.726ns, distribution 1.105ns)
  Clock Net Delay (Destination): 2.084ns (routing 0.799ns, distribution 1.285ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     2.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.831     4.490    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Clk
    SLICE_X89Y350        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Address_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y350        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.058     4.548 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Address_reg[10]/Q
                         net (fo=1, routed)           0.135     4.683    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_ub[10]
    SLICE_X88Y350        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.084     4.311    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y350        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/C
                         clock pessimism              0.288     4.599    
    SLICE_X88Y350        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.062     4.661    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]
  -------------------------------------------------------------------
                         required time                         -4.661    
                         arrival time                           4.683    
  -------------------------------------------------------------------
                         slack                                  0.022    

Slack (MET) :             0.024ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[27]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[27]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.134ns  (logic 0.059ns (44.030%)  route 0.075ns (55.970%))
  Logic Levels:           0  
  Clock Path Skew:        0.048ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.285ns
    Source Clock Delay      (SCD):    4.479ns
    Clock Pessimism Removal (CPR):    -0.242ns
  Clock Net Delay (Source):      1.820ns (routing 0.726ns, distribution 1.094ns)
  Clock Net Delay (Destination): 2.058ns (routing 0.799ns, distribution 1.259ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     2.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.820     4.479    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Clk
    SLICE_X92Y348        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[27]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y348        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     4.538 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[27]/Q
                         net (fo=1, routed)           0.075     4.613    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_ub[27]
    SLICE_X92Y346        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[27]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.058     4.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X92Y346        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[27]/C
                         clock pessimism              0.242     4.527    
    SLICE_X92Y346        FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.062     4.589    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[27]
  -------------------------------------------------------------------
                         required time                         -4.589    
                         arrival time                           4.613    
  -------------------------------------------------------------------
                         slack                                  0.024    

Slack (MET) :             0.025ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Address_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.058ns (29.442%)  route 0.139ns (70.558%))
  Logic Levels:           0  
  Clock Path Skew:        0.110ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.311ns
    Source Clock Delay      (SCD):    4.489ns
    Clock Pessimism Removal (CPR):    -0.288ns
  Clock Net Delay (Source):      1.830ns (routing 0.726ns, distribution 1.104ns)
  Clock Net Delay (Destination): 2.084ns (routing 0.799ns, distribution 1.285ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     2.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.830     4.489    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Clk
    SLICE_X89Y349        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Address_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y349        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.058     4.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Address_reg[5]/Q
                         net (fo=1, routed)           0.139     4.686    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_ub[5]
    SLICE_X88Y350        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.084     4.311    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y350        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[3]/C
                         clock pessimism              0.288     4.599    
    SLICE_X88Y350        FDRE (Hold_FFF2_SLICEL_C_D)
                                                      0.062     4.661    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[3]
  -------------------------------------------------------------------
                         required time                         -4.661    
                         arrival time                           4.686    
  -------------------------------------------------------------------
                         slack                                  0.025    

Slack (MET) :             0.025ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.142ns  (logic 0.057ns (40.141%)  route 0.085ns (59.859%))
  Logic Levels:           0  
  Clock Path Skew:        0.055ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.310ns
    Source Clock Delay      (SCD):    4.495ns
    Clock Pessimism Removal (CPR):    -0.240ns
  Clock Net Delay (Source):      1.836ns (routing 0.726ns, distribution 1.110ns)
  Clock Net Delay (Destination): 2.083ns (routing 0.799ns, distribution 1.284ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     2.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.836     4.495    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Clk
    SLICE_X87Y346        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y346        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     4.552 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[1]/Q
                         net (fo=1, routed)           0.085     4.637    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_ub[1]
    SLICE_X87Y348        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.083     4.310    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X87Y348        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[1]/C
                         clock pessimism              0.240     4.550    
    SLICE_X87Y348        FDRE (Hold_FFF2_SLICEM_C_D)
                                                      0.062     4.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[1]
  -------------------------------------------------------------------
                         required time                         -4.612    
                         arrival time                           4.637    
  -------------------------------------------------------------------
                         slack                                  0.025    

Slack (MET) :             0.027ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.134ns  (logic 0.059ns (44.030%)  route 0.075ns (55.970%))
  Logic Levels:           0  
  Clock Path Skew:        0.047ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.285ns
    Source Clock Delay      (SCD):    4.478ns
    Clock Pessimism Removal (CPR):    -0.240ns
  Clock Net Delay (Source):      1.819ns (routing 0.726ns, distribution 1.093ns)
  Clock Net Delay (Destination): 2.058ns (routing 0.799ns, distribution 1.259ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     2.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.819     4.478    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Clk
    SLICE_X91Y344        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y344        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     4.537 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[7]/Q
                         net (fo=1, routed)           0.075     4.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_ub[7]
    SLICE_X91Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.058     4.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X91Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[7]/C
                         clock pessimism              0.240     4.525    
    SLICE_X91Y343        FDRE (Hold_HFF_SLICEL_C_D)
                                                      0.060     4.585    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[7]
  -------------------------------------------------------------------
                         required time                         -4.585    
                         arrival time                           4.612    
  -------------------------------------------------------------------
                         slack                                  0.027    

Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.187ns  (logic 0.059ns (31.551%)  route 0.128ns (68.449%))
  Logic Levels:           0  
  Clock Path Skew:        0.095ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.285ns
    Source Clock Delay      (SCD):    4.478ns
    Clock Pessimism Removal (CPR):    -0.288ns
  Clock Net Delay (Source):      1.819ns (routing 0.726ns, distribution 1.093ns)
  Clock Net Delay (Destination): 2.058ns (routing 0.799ns, distribution 1.259ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     2.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.819     4.478    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Clk
    SLICE_X91Y344        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y344        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     4.537 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[10]/Q
                         net (fo=1, routed)           0.128     4.665    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_ub[10]
    SLICE_X88Y344        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.058     4.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y344        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[10]/C
                         clock pessimism              0.288     4.573    
    SLICE_X88Y344        FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.062     4.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[10]
  -------------------------------------------------------------------
                         required time                         -4.635    
                         arrival time                           4.665    
  -------------------------------------------------------------------
                         slack                                  0.030    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[24]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.184ns  (logic 0.081ns (44.084%)  route 0.103ns (55.916%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.093ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.291ns
    Source Clock Delay      (SCD):    4.486ns
    Clock Pessimism Removal (CPR):    -0.288ns
  Clock Net Delay (Source):      1.827ns (routing 0.726ns, distribution 1.101ns)
  Clock Net Delay (Destination): 2.064ns (routing 0.799ns, distribution 1.265ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     2.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.827     4.486    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y344        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y344        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     4.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/Q
                         net (fo=41, routed)          0.073     4.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/out[21]
    SLICE_X89Y343        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.023     4.639 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub[24]_i_1/O
                         net (fo=1, routed)           0.030     4.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_mux[24]
    SLICE_X89Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[24]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.064     4.291    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X89Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[24]/C
                         clock pessimism              0.288     4.579    
    SLICE_X89Y343        FDRE (Hold_HFF_SLICEM_C_D)
                                                      0.060     4.639    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[24]
  -------------------------------------------------------------------
                         required time                         -4.639    
                         arrival time                           4.669    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.034ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op3_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.Gen_Bits[11].mem_Rd_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.134ns  (logic 0.058ns (43.153%)  route 0.076ns (56.847%))
  Logic Levels:           0  
  Clock Path Skew:        0.038ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.312ns
    Source Clock Delay      (SCD):    4.503ns
    Clock Pessimism Removal (CPR):    -0.229ns
  Clock Net Delay (Source):      1.844ns (routing 0.726ns, distribution 1.118ns)
  Clock Net Delay (Destination): 2.085ns (routing 0.799ns, distribution 1.286ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     2.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.844     4.503    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X88Y354        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op3_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y354        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.058     4.561 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op3_reg[11]/Q
                         net (fo=2, routed)           0.076     4.637    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Q[20]
    SLICE_X87Y354        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.Gen_Bits[11].mem_Rd_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.085     4.312    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Clk
    SLICE_X87Y354        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.Gen_Bits[11].mem_Rd_reg[11]/C
                         clock pessimism              0.229     4.541    
    SLICE_X87Y354        FDRE (Hold_HFF2_SLICEM_C_D)
                                                      0.062     4.603    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.Gen_Bits[11].mem_Rd_reg[11]
  -------------------------------------------------------------------
                         required time                         -4.603    
                         arrival time                           4.637    
  -------------------------------------------------------------------
                         slack                                  0.034    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mmcm_clkout6
Waveform(ns):       { 0.000 3.001 }
Period(ns):         6.001
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6 }

Check Type        Corner  Lib Pin                   Reference Pin             Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y29  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.846       0.972      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.846       0.972      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.845       0.973      BITSLICE_CONTROL_X0Y37  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.843       0.975      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.843       0.975      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.843       0.975      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.843       0.975      BITSLICE_CONTROL_X0Y39  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.841       0.977      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.840       0.978      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.840       0.978      BITSLICE_CONTROL_X0Y31  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout5
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Setup :            0  Failing Endpoints,  Worst Slack       11.489ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             11.489ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.538ns  (logic 0.076ns (14.126%)  route 0.462ns (85.874%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y295                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
    SLICE_X104Y295       FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.462     0.538    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[3]
    SLICE_X104Y295       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X104Y295       FDCE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.538    
  -------------------------------------------------------------------
                         slack                                 11.489    

Slack (MET) :             11.511ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.516ns  (logic 0.079ns (15.310%)  route 0.437ns (84.690%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y299                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
    SLICE_X102Y299       FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.437     0.516    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[2]
    SLICE_X101Y295       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X101Y295       FDCE (Setup_FFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.516    
  -------------------------------------------------------------------
                         slack                                 11.511    

Slack (MET) :             11.576ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.451ns  (logic 0.080ns (17.738%)  route 0.371ns (82.262%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y299                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
    SLICE_X102Y299       FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.371     0.451    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[1]
    SLICE_X101Y295       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X101Y295       FDCE (Setup_GFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.451    
  -------------------------------------------------------------------
                         slack                                 11.576    

Slack (MET) :             11.646ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.381ns  (logic 0.079ns (20.735%)  route 0.302ns (79.265%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y299                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
    SLICE_X102Y299       FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.302     0.381    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[0]
    SLICE_X101Y295       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X101Y295       FDCE (Setup_BFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.381    
  -------------------------------------------------------------------
                         slack                                 11.646    

Slack (MET) :             11.690ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.337ns  (logic 0.079ns (23.442%)  route 0.258ns (76.558%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y292                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
    SLICE_X101Y292       FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.258     0.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[3]
    SLICE_X101Y292       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X101Y292       FDCE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.337    
  -------------------------------------------------------------------
                         slack                                 11.690    

Slack (MET) :             11.700ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.327ns  (logic 0.080ns (24.465%)  route 0.247ns (75.535%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y293                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
    SLICE_X102Y293       FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.247     0.327    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[2]
    SLICE_X100Y293       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X100Y293       FDCE (Setup_GFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.327    
  -------------------------------------------------------------------
                         slack                                 11.700    

Slack (MET) :             11.783ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.244ns  (logic 0.081ns (33.197%)  route 0.163ns (66.803%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y293                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
    SLICE_X102Y293       FDCE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.163     0.244    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[1]
    SLICE_X100Y293       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X100Y293       FDCE (Setup_BFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.244    
  -------------------------------------------------------------------
                         slack                                 11.783    

Slack (MET) :             11.784ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.243ns  (logic 0.079ns (32.510%)  route 0.164ns (67.490%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y293                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
    SLICE_X102Y293       FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.164     0.243    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[0]
    SLICE_X100Y293       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X100Y293       FDCE (Setup_HFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.243    
  -------------------------------------------------------------------
                         slack                                 11.784    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        2.315ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.315ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_cptd_sclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_cptd_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.710ns  (logic 0.079ns (11.127%)  route 0.631ns (88.873%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y314                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_cptd_sclk_reg/C
    SLICE_X96Y314        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_cptd_sclk_reg/Q
                         net (fo=1, routed)           0.631     0.710    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_cptd_sync/SYNC[0].sync_reg_reg[0]_0[0]
    SLICE_X96Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_cptd_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X96Y314        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_cptd_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.710    
  -------------------------------------------------------------------
                         slack                                  2.315    

Slack (MET) :             2.435ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.590ns  (logic 0.079ns (13.390%)  route 0.511ns (86.610%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y312                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[5]/C
    SLICE_X93Y312        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[5]/Q
                         net (fo=1, routed)           0.511     0.590    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[5]
    SLICE_X90Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X90Y313        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[5].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.590    
  -------------------------------------------------------------------
                         slack                                  2.435    

Slack (MET) :             2.435ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_we_r_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_we_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.590ns  (logic 0.079ns (13.390%)  route 0.511ns (86.610%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y315                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_we_r_reg/C
    SLICE_X96Y315        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_we_r_reg/Q
                         net (fo=1, routed)           0.511     0.590    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_we_sync/D[0]
    SLICE_X96Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_we_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X96Y315        FDRE (Setup_BFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_we_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.590    
  -------------------------------------------------------------------
                         slack                                  2.435    

Slack (MET) :             2.460ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.565ns  (logic 0.078ns (13.805%)  route 0.487ns (86.195%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y312                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[3]/C
    SLICE_X96Y312        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[3]/Q
                         net (fo=1, routed)           0.487     0.565    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[3]
    SLICE_X93Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X93Y315        FDRE (Setup_GFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[3].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.565    
  -------------------------------------------------------------------
                         slack                                  2.460    

Slack (MET) :             2.464ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.561ns  (logic 0.080ns (14.260%)  route 0.481ns (85.740%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y308                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[1]/C
    SLICE_X95Y308        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[1]/Q
                         net (fo=1, routed)           0.481     0.561    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[1]
    SLICE_X94Y307        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X94Y307        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[1].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.561    
  -------------------------------------------------------------------
                         slack                                  2.464    

Slack (MET) :             2.510ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.515ns  (logic 0.079ns (15.340%)  route 0.436ns (84.660%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y313                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[6]/C
    SLICE_X96Y313        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[6]/Q
                         net (fo=1, routed)           0.436     0.515    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[6]
    SLICE_X94Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X94Y313        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[6].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.515    
  -------------------------------------------------------------------
                         slack                                  2.510    

Slack (MET) :             2.521ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.504ns  (logic 0.076ns (15.079%)  route 0.428ns (84.921%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y314                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[14]/C
    SLICE_X94Y314        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     0.076 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[14]/Q
                         net (fo=1, routed)           0.428     0.504    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[14]
    SLICE_X93Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X93Y315        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.504    
  -------------------------------------------------------------------
                         slack                                  2.521    

Slack (MET) :             2.549ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.476ns  (logic 0.079ns (16.597%)  route 0.397ns (83.403%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y311                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[4]/C
    SLICE_X95Y311        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[4]/Q
                         net (fo=1, routed)           0.397     0.476    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[4]
    SLICE_X93Y302        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X93Y302        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[4].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.476    
  -------------------------------------------------------------------
                         slack                                  2.549    

Slack (MET) :             2.560ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.465ns  (logic 0.080ns (17.204%)  route 0.385ns (82.796%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y305                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[2]/C
    SLICE_X96Y305        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[2]/Q
                         net (fo=1, routed)           0.385     0.465    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[2]
    SLICE_X94Y303        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X94Y303        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[2].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.465    
  -------------------------------------------------------------------
                         slack                                  2.560    

Slack (MET) :             2.569ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.456ns  (logic 0.079ns (17.325%)  route 0.377ns (82.675%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y312                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[7]/C
    SLICE_X93Y312        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[7]/Q
                         net (fo=1, routed)           0.377     0.456    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[7]
    SLICE_X93Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X93Y312        FDRE (Setup_BFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.456    
  -------------------------------------------------------------------
                         slack                                  2.569    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        0.803ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.803ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        2.222ns  (logic 0.079ns (3.555%)  route 2.143ns (96.445%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y350                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[2]/C
    SLICE_X88Y350        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[2]/Q
                         net (fo=34, routed)          2.143     2.222    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[2]
    SLICE_X87Y284        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X87Y284        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[2].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -2.222    
  -------------------------------------------------------------------
                         slack                                  0.803    

Slack (MET) :             1.509ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.516ns  (logic 0.080ns (5.276%)  route 1.436ns (94.724%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y350                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[2]/C
    SLICE_X87Y350        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[2]/Q
                         net (fo=2, routed)           1.436     1.516    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[31].sync_reg_reg[0]_0[2]
    SLICE_X81Y353        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X81Y353        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[2].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.516    
  -------------------------------------------------------------------
                         slack                                  1.509    

Slack (MET) :             1.576ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[23].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.449ns  (logic 0.081ns (5.589%)  route 1.368ns (94.411%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y350                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[23]/C
    SLICE_X88Y350        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[23]/Q
                         net (fo=46, routed)          1.368     1.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[23]
    SLICE_X85Y300        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[23].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X85Y300        FDRE (Setup_BFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[23].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.449    
  -------------------------------------------------------------------
                         slack                                  1.576    

Slack (MET) :             1.793ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.232ns  (logic 0.076ns (6.169%)  route 1.156ns (93.831%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y348                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[0]/C
    SLICE_X87Y348        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[0]/Q
                         net (fo=34, routed)          1.156     1.232    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[0]
    SLICE_X89Y295        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X89Y295        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.232    
  -------------------------------------------------------------------
                         slack                                  1.793    

Slack (MET) :             1.847ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[9].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.178ns  (logic 0.078ns (6.621%)  route 1.100ns (93.379%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y350                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[9]/C
    SLICE_X87Y350        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[9]/Q
                         net (fo=39, routed)          1.100     1.178    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[9]
    SLICE_X83Y302        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[9].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X83Y302        FDRE (Setup_FFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[9].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.178    
  -------------------------------------------------------------------
                         slack                                  1.847    

Slack (MET) :             1.848ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[12].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.177ns  (logic 0.081ns (6.882%)  route 1.096ns (93.118%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y347                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[12]/C
    SLICE_X85Y347        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[12]/Q
                         net (fo=2, routed)           1.096     1.177    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[31].sync_reg_reg[0]_0[12]
    SLICE_X84Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[12].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X84Y351        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[12].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.177    
  -------------------------------------------------------------------
                         slack                                  1.848    

Slack (MET) :             1.860ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[21].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.165ns  (logic 0.079ns (6.782%)  route 1.086ns (93.218%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y344                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
    SLICE_X88Y344        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/Q
                         net (fo=41, routed)          1.086     1.165    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[21]
    SLICE_X85Y306        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[21].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X85Y306        FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[21].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.165    
  -------------------------------------------------------------------
                         slack                                  1.860    

Slack (MET) :             1.881ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[16].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.144ns  (logic 0.076ns (6.643%)  route 1.068ns (93.357%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y351                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[16]/C
    SLICE_X87Y351        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[16]/Q
                         net (fo=44, routed)          1.068     1.144    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[16]
    SLICE_X86Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[16].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X86Y351        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[16].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.144    
  -------------------------------------------------------------------
                         slack                                  1.881    

Slack (MET) :             1.904ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[22]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[22].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.121ns  (logic 0.076ns (6.779%)  route 1.045ns (93.221%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y343                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[22]/C
    SLICE_X89Y343        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     0.076 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[22]/Q
                         net (fo=41, routed)          1.045     1.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[22]
    SLICE_X86Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[22].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X86Y305        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[22].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.121    
  -------------------------------------------------------------------
                         slack                                  1.904    

Slack (MET) :             1.922ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.103ns  (logic 0.079ns (7.161%)  route 1.024ns (92.839%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y349                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[1]/C
    SLICE_X88Y349        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[1]/Q
                         net (fo=33, routed)          1.024     1.103    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[1]
    SLICE_X87Y279        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X87Y279        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[1].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.103    
  -------------------------------------------------------------------
                         slack                                  1.922    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  pll_clk[0]_DIV

Setup :            0  Failing Endpoints,  Worst Slack        0.568ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.709ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.568ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.484ns  (logic 0.079ns (5.324%)  route 1.405ns (94.676%))
  Logic Levels:           0  
  Clock Path Skew:        -0.686ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.923ns = ( 6.924 - 3.001 ) 
    Source Clock Delay      (SCD):    4.239ns
    Clock Pessimism Removal (CPR):    -0.370ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.029ns (routing 0.788ns, distribution 1.241ns)
  Clock Net Delay (Destination): 1.629ns (routing 0.716ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.029     4.239    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X81Y259        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y259        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     4.318 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/Q
                         net (fo=8, routed)           1.405     5.723    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[3]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.629     7.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.647 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.096     6.743    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.849 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.924 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.370     6.554    
                         clock uncertainty           -0.170     6.384    
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[3])
                                                     -0.093     6.291    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.291    
                         arrival time                          -5.723    
  -------------------------------------------------------------------
                         slack                                  0.568    

Slack (MET) :             0.631ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.350ns  (logic 0.078ns (5.776%)  route 1.272ns (94.224%))
  Logic Levels:           0  
  Clock Path Skew:        -0.705ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.935ns = ( 6.936 - 3.001 ) 
    Source Clock Delay      (SCD):    4.270ns
    Clock Pessimism Removal (CPR):    -0.370ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.060ns (routing 0.788ns, distribution 1.272ns)
  Clock Net Delay (Destination): 1.629ns (routing 0.716ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.060     4.270    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X83Y250        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y250        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.348 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[1]/Q
                         net (fo=8, routed)           1.272     5.620    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_low[1]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.629     7.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.647 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.097     6.744    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.861 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.936 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.370     6.566    
                         clock uncertainty           -0.170     6.396    
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[1])
                                                     -0.144     6.252    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.252    
                         arrival time                          -5.620    
  -------------------------------------------------------------------
                         slack                                  0.631    

Slack (MET) :             0.653ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.666ns  (logic 0.077ns (4.622%)  route 1.589ns (95.378%))
  Logic Levels:           0  
  Clock Path Skew:        -0.458ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.055ns = ( 7.056 - 3.001 ) 
    Source Clock Delay      (SCD):    4.205ns
    Clock Pessimism Removal (CPR):    -0.308ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.995ns (routing 0.788ns, distribution 1.207ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.995     4.205    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X87Y194        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y194        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     4.282 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[5]/Q
                         net (fo=1, routed)           1.589     5.871    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[5]
    BITSLICE_RX_TX_X0Y177
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.629     7.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.091     6.738    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.844 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.919 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.124     7.043 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     7.056    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y177
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.308     6.748    
                         clock uncertainty           -0.170     6.578    
    BITSLICE_RX_TX_X0Y177
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                     -0.054     6.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.524    
                         arrival time                          -5.871    
  -------------------------------------------------------------------
                         slack                                  0.653    

Slack (MET) :             0.678ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.298ns  (logic 0.079ns (6.085%)  route 1.219ns (93.915%))
  Logic Levels:           0  
  Clock Path Skew:        -0.686ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.923ns = ( 6.924 - 3.001 ) 
    Source Clock Delay      (SCD):    4.239ns
    Clock Pessimism Removal (CPR):    -0.370ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.029ns (routing 0.788ns, distribution 1.241ns)
  Clock Net Delay (Destination): 1.629ns (routing 0.716ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.029     4.239    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X81Y259        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y259        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     4.318 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[2]/Q
                         net (fo=8, routed)           1.219     5.537    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[2]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.629     7.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.647 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.096     6.743    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.849 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.924 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.370     6.554    
                         clock uncertainty           -0.170     6.384    
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[2])
                                                     -0.168     6.216    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.216    
                         arrival time                          -5.537    
  -------------------------------------------------------------------
                         slack                                  0.678    

Slack (MET) :             0.708ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.688ns  (logic 0.079ns (4.680%)  route 1.609ns (95.320%))
  Logic Levels:           0  
  Clock Path Skew:        -0.414ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.060ns = ( 7.061 - 3.001 ) 
    Source Clock Delay      (SCD):    4.166ns
    Clock Pessimism Removal (CPR):    -0.308ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.956ns (routing 0.788ns, distribution 1.168ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.956     4.166    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X92Y188        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y188        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     4.245 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[2]/Q
                         net (fo=1, routed)           1.609     5.854    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[2]
    BITSLICE_RX_TX_X0Y164
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.629     7.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.647 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.096     6.743    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.849 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.924 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.124     7.048 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     7.061    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y164
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.308     6.753    
                         clock uncertainty           -0.170     6.583    
    BITSLICE_RX_TX_X0Y164
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                     -0.021     6.562    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.562    
                         arrival time                          -5.854    
  -------------------------------------------------------------------
                         slack                                  0.708    

Slack (MET) :             0.710ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.337ns  (logic 0.079ns (5.909%)  route 1.258ns (94.091%))
  Logic Levels:           0  
  Clock Path Skew:        -0.691ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.918ns = ( 6.919 - 3.001 ) 
    Source Clock Delay      (SCD):    4.239ns
    Clock Pessimism Removal (CPR):    -0.370ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.029ns (routing 0.788ns, distribution 1.241ns)
  Clock Net Delay (Destination): 1.629ns (routing 0.716ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.029     4.239    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X81Y259        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y259        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     4.318 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/Q
                         net (fo=8, routed)           1.258     5.576    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[3]
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.629     7.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.091     6.738    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.844 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.919 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.370     6.549    
                         clock uncertainty           -0.170     6.379    
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[3])
                                                     -0.093     6.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.286    
                         arrival time                          -5.576    
  -------------------------------------------------------------------
                         slack                                  0.710    

Slack (MET) :             0.714ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.616ns  (logic 0.079ns (4.889%)  route 1.537ns (95.111%))
  Logic Levels:           0  
  Clock Path Skew:        -0.419ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.072ns = ( 7.073 - 3.001 ) 
    Source Clock Delay      (SCD):    4.183ns
    Clock Pessimism Removal (CPR):    -0.308ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.973ns (routing 0.788ns, distribution 1.185ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.973     4.183    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X85Y195        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y195        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     4.262 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[3]/Q
                         net (fo=1, routed)           1.537     5.799    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[3]
    BITSLICE_RX_TX_X0Y173
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.629     7.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.647 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.094     6.741    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.858 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.933 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.127     7.060 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.013     7.073    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y173
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.308     6.765    
                         clock uncertainty           -0.170     6.595    
    BITSLICE_RX_TX_X0Y173
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                     -0.082     6.513    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.513    
                         arrival time                          -5.799    
  -------------------------------------------------------------------
                         slack                                  0.714    

Slack (MET) :             0.717ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.689ns  (logic 0.076ns (4.500%)  route 1.613ns (95.500%))
  Logic Levels:           0  
  Clock Path Skew:        -0.398ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.055ns = ( 7.056 - 3.001 ) 
    Source Clock Delay      (SCD):    4.146ns
    Clock Pessimism Removal (CPR):    -0.307ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.936ns (routing 0.788ns, distribution 1.148ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.936     4.146    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[10]_0
    SLICE_X93Y205        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y205        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.222 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[5]/Q
                         net (fo=1, routed)           1.613     5.835    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[5]
    BITSLICE_RX_TX_X0Y169
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.629     7.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.647 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.094     6.741    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.858 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.933 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.109     7.042 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.014     7.056    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y169
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.307     6.748    
                         clock uncertainty           -0.170     6.578    
    BITSLICE_RX_TX_X0Y169
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                     -0.026     6.552    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.552    
                         arrival time                          -5.835    
  -------------------------------------------------------------------
                         slack                                  0.717    

Slack (MET) :             0.718ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.640ns  (logic 0.079ns (4.817%)  route 1.561ns (95.183%))
  Logic Levels:           0  
  Clock Path Skew:        -0.428ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.064ns = ( 7.065 - 3.001 ) 
    Source Clock Delay      (SCD):    4.184ns
    Clock Pessimism Removal (CPR):    -0.308ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.974ns (routing 0.788ns, distribution 1.186ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.974     4.184    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X85Y225        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y225        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.263 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[7]/Q
                         net (fo=1, routed)           1.561     5.824    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[7]
    BITSLICE_RX_TX_X0Y205
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.629     7.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.647 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.099     6.746    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.852 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.927 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.125     7.052 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.013     7.065    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y205
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.308     6.757    
                         clock uncertainty           -0.170     6.587    
    BITSLICE_RX_TX_X0Y205
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                     -0.045     6.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.542    
                         arrival time                          -5.824    
  -------------------------------------------------------------------
                         slack                                  0.718    

Slack (MET) :             0.726ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.618ns  (logic 0.079ns (4.883%)  route 1.539ns (95.117%))
  Logic Levels:           0  
  Clock Path Skew:        -0.410ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.060ns = ( 7.061 - 3.001 ) 
    Source Clock Delay      (SCD):    4.163ns
    Clock Pessimism Removal (CPR):    -0.308ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.953ns (routing 0.788ns, distribution 1.165ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.953     4.163    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X91Y220        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y220        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     4.242 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[1]/Q
                         net (fo=1, routed)           1.539     5.781    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[1]
    BITSLICE_RX_TX_X0Y190
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.629     7.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.647 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.096     6.743    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y29
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.849 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y29
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.924 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y29
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.124     7.048 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     7.061    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y190
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.308     6.753    
                         clock uncertainty           -0.170     6.583    
    BITSLICE_RX_TX_X0Y190
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                     -0.076     6.507    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.507    
                         arrival time                          -5.781    
  -------------------------------------------------------------------
                         slack                                  0.726    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.709ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.461ns  (logic 0.058ns (12.581%)  route 0.403ns (87.419%))
  Logic Levels:           0  
  Clock Path Skew:        -0.492ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.606ns
    Source Clock Delay      (SCD):    4.406ns
    Clock Pessimism Removal (CPR):    -0.308ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.759ns (routing 0.716ns, distribution 1.043ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.759     4.406    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X85Y231        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y231        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     4.464 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[5]/Q
                         net (fo=1, routed)           0.403     4.867    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[5]
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.812     4.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.964 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.140     3.104    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.281 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.390 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     3.582 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     3.606    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.308     3.914    
                         clock uncertainty            0.170     4.084    
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                      0.074     4.158    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.158    
                         arrival time                           4.867    
  -------------------------------------------------------------------
                         slack                                  0.709    

Slack (MET) :             0.709ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.431ns  (logic 0.059ns (13.689%)  route 0.372ns (86.311%))
  Logic Levels:           0  
  Clock Path Skew:        -0.492ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.606ns
    Source Clock Delay      (SCD):    4.406ns
    Clock Pessimism Removal (CPR):    -0.308ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.759ns (routing 0.716ns, distribution 1.043ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.759     4.406    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X85Y231        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y231        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     4.465 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[7]/Q
                         net (fo=1, routed)           0.372     4.837    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[7]
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.812     4.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.964 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.140     3.104    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.281 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.390 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     3.582 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     3.606    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.308     3.914    
                         clock uncertainty            0.170     4.084    
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                      0.044     4.128    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.128    
                         arrival time                           4.837    
  -------------------------------------------------------------------
                         slack                                  0.709    

Slack (MET) :             0.718ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.456ns  (logic 0.057ns (12.500%)  route 0.399ns (87.500%))
  Logic Levels:           0  
  Clock Path Skew:        -0.485ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.590ns
    Source Clock Delay      (SCD):    4.383ns
    Clock Pessimism Removal (CPR):    -0.308ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.736ns (routing 0.716ns, distribution 1.020ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.736     4.383    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X90Y210        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y210        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     4.440 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[3]/Q
                         net (fo=1, routed)           0.399     4.839    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[3]
    BITSLICE_RX_TX_X0Y185
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.812     4.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.964 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.132     3.096    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.273 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.382 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.187     3.569 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     3.590    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y185
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.308     3.897    
                         clock uncertainty            0.170     4.068    
    BITSLICE_RX_TX_X0Y185
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                      0.053     4.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.121    
                         arrival time                           4.839    
  -------------------------------------------------------------------
                         slack                                  0.718    

Slack (MET) :             0.723ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.486ns  (logic 0.059ns (12.140%)  route 0.427ns (87.860%))
  Logic Levels:           0  
  Clock Path Skew:        -0.479ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.595ns
    Source Clock Delay      (SCD):    4.381ns
    Clock Pessimism Removal (CPR):    -0.308ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.734ns (routing 0.716ns, distribution 1.018ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.734     4.381    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[10]_0
    SLICE_X92Y226        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y226        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     4.440 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[6]/Q
                         net (fo=1, routed)           0.427     4.867    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[6]
    BITSLICE_RX_TX_X0Y195
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.812     4.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.964 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.140     3.104    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.281 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.390 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.162     3.552 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y195
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.308     3.902    
                         clock uncertainty            0.170     4.073    
    BITSLICE_RX_TX_X0Y195
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                      0.072     4.145    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.145    
                         arrival time                           4.867    
  -------------------------------------------------------------------
                         slack                                  0.723    

Slack (MET) :             0.727ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.450ns  (logic 0.060ns (13.333%)  route 0.390ns (86.667%))
  Logic Levels:           0  
  Clock Path Skew:        -0.499ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.598ns
    Source Clock Delay      (SCD):    4.405ns
    Clock Pessimism Removal (CPR):    -0.308ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.758ns (routing 0.716ns, distribution 1.042ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.758     4.405    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X85Y229        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y229        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.060     4.465 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[0]/Q
                         net (fo=1, routed)           0.390     4.855    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[0]
    BITSLICE_RX_TX_X0Y198
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.812     4.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.964 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.140     3.104    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.281 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.390 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.187     3.577 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     3.598    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y198
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.308     3.906    
                         clock uncertainty            0.170     4.076    
    BITSLICE_RX_TX_X0Y198
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.052     4.128    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.128    
                         arrival time                           4.855    
  -------------------------------------------------------------------
                         slack                                  0.727    

Slack (MET) :             0.730ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.430ns  (logic 0.059ns (13.721%)  route 0.371ns (86.279%))
  Logic Levels:           0  
  Clock Path Skew:        -0.511ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.598ns
    Source Clock Delay      (SCD):    4.416ns
    Clock Pessimism Removal (CPR):    -0.308ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.769ns (routing 0.716ns, distribution 1.053ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.769     4.416    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X84Y228        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y228        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.059     4.475 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[1]/Q
                         net (fo=1, routed)           0.371     4.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[1]
    BITSLICE_RX_TX_X0Y199
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.812     4.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.964 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.140     3.104    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.281 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.390 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.186     3.576 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.022     3.598    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y199
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.308     3.906    
                         clock uncertainty            0.170     4.076    
    BITSLICE_RX_TX_X0Y199
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                      0.041     4.117    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.117    
                         arrival time                           4.846    
  -------------------------------------------------------------------
                         slack                                  0.730    

Slack (MET) :             0.746ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.457ns  (logic 0.058ns (12.691%)  route 0.399ns (87.309%))
  Logic Levels:           0  
  Clock Path Skew:        -0.532ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.568ns
    Source Clock Delay      (SCD):    4.408ns
    Clock Pessimism Removal (CPR):    -0.308ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.761ns (routing 0.716ns, distribution 1.045ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.761     4.408    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X86Y237        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y237        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     4.466 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[6]/Q
                         net (fo=1, routed)           0.399     4.865    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[6]
    BITSLICE_RX_TX_X0Y205
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.812     4.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.964 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.142     3.106    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     3.257 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.366 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.180     3.546 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.022     3.568    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y205
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.308     3.876    
                         clock uncertainty            0.170     4.046    
    BITSLICE_RX_TX_X0Y205
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                      0.073     4.119    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.119    
                         arrival time                           4.865    
  -------------------------------------------------------------------
                         slack                                  0.746    

Slack (MET) :             0.756ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[4].u_ddr_mc_rd_en_upp/rdEn_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.443ns  (logic 0.059ns (13.318%)  route 0.384ns (86.682%))
  Logic Levels:           0  
  Clock Path Skew:        -0.699ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.386ns
    Source Clock Delay      (SCD):    4.455ns
    Clock Pessimism Removal (CPR):    -0.370ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.808ns (routing 0.716ns, distribution 1.092ns)
  Clock Net Delay (Destination): 1.812ns (routing 0.788ns, distribution 1.024ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.808     4.455    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[4].u_ddr_mc_rd_en_upp/rsMask_reg[7][9]_0
    SLICE_X85Y246        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[4].u_ddr_mc_rd_en_upp/rdEn_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y246        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     4.514 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[4].u_ddr_mc_rd_en_upp/rdEn_reg[3]/Q
                         net (fo=1, routed)           0.384     4.898    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_upp[3]
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.812     4.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.964 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.142     3.106    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.162     3.268 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.118     3.386 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.370     3.756    
                         clock uncertainty            0.170     3.926    
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[3])
                                                      0.216     4.142    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.142    
                         arrival time                           4.898    
  -------------------------------------------------------------------
                         slack                                  0.756    

Slack (MET) :             0.757ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[6].u_ddr_mc_rd_en_low/rdEn_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.528ns  (logic 0.058ns (10.985%)  route 0.470ns (89.015%))
  Logic Levels:           0  
  Clock Path Skew:        -0.667ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.410ns
    Source Clock Delay      (SCD):    4.385ns
    Clock Pessimism Removal (CPR):    -0.308ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.738ns (routing 0.716ns, distribution 1.022ns)
  Clock Net Delay (Destination): 1.812ns (routing 0.788ns, distribution 1.024ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.738     4.385    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[6].u_ddr_mc_rd_en_low/rsMask_reg[7][12]_0
    SLICE_X91Y220        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[6].u_ddr_mc_rd_en_low/rdEn_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y220        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     4.443 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[6].u_ddr_mc_rd_en_low/rdEn_reg[3]/Q
                         net (fo=1, routed)           0.470     4.913    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[3]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.812     4.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.964 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.134     3.098    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.291 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.308     3.717    
                         clock uncertainty            0.170     3.888    
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[3])
                                                      0.268     4.156    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.156    
                         arrival time                           4.913    
  -------------------------------------------------------------------
                         slack                                  0.757    

Slack (MET) :             0.760ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[6].u_ddr_mc_rd_en_upp/rdEn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.422ns  (logic 0.058ns (13.744%)  route 0.364ns (86.256%))
  Logic Levels:           0  
  Clock Path Skew:        -0.735ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.373ns
    Source Clock Delay      (SCD):    4.416ns
    Clock Pessimism Removal (CPR):    -0.308ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.769ns (routing 0.716ns, distribution 1.053ns)
  Clock Net Delay (Destination): 1.812ns (routing 0.788ns, distribution 1.024ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.769     4.416    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[6].u_ddr_mc_rd_en_upp/rsMask_reg[7][9]_0
    SLICE_X84Y221        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[6].u_ddr_mc_rd_en_upp/rdEn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y221        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     4.474 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[6].u_ddr_mc_rd_en_upp/rdEn_reg[0]/Q
                         net (fo=1, routed)           0.364     4.838    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_upp[0]
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.812     4.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.964 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.129     3.093    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.162     3.255 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.118     3.373 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.308     3.681    
                         clock uncertainty            0.170     3.851    
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[0])
                                                      0.227     4.078    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.078    
                         arrival time                           4.838    
  -------------------------------------------------------------------
                         slack                                  0.760    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  pll_clk[1]_DIV

Setup :            0  Failing Endpoints,  Worst Slack        0.323ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.517ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.323ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.976ns  (logic 0.078ns (3.947%)  route 1.898ns (96.053%))
  Logic Levels:           0  
  Clock Path Skew:        -0.450ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.114ns = ( 7.115 - 3.001 ) 
    Source Clock Delay      (SCD):    4.194ns
    Clock Pessimism Removal (CPR):    -0.370ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.984ns (routing 0.788ns, distribution 1.196ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.984     4.194    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X82Y202        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y202        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     4.272 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[3]/Q
                         net (fo=1, routed)           1.898     6.170    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[3]
    BITSLICE_RX_TX_X0Y238
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.672     7.320    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y9             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.690 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.093     6.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.900 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.975 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.127     7.102 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.013     7.115    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y238
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.370     6.745    
                         clock uncertainty           -0.170     6.574    
    BITSLICE_RX_TX_X0Y238
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                     -0.082     6.492    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.492    
                         arrival time                          -6.170    
  -------------------------------------------------------------------
                         slack                                  0.323    

Slack (MET) :             0.327ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.884ns  (logic 0.076ns (4.034%)  route 1.808ns (95.966%))
  Logic Levels:           0  
  Clock Path Skew:        -0.479ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.104ns = ( 7.105 - 3.001 ) 
    Source Clock Delay      (SCD):    4.213ns
    Clock Pessimism Removal (CPR):    -0.370ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.003ns (routing 0.788ns, distribution 1.215ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.003     4.213    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X83Y200        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y200        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     4.289 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[5]/Q
                         net (fo=1, routed)           1.808     6.097    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[5]
    BITSLICE_RX_TX_X0Y244
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.672     7.320    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y9             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.690 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.096     6.786    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y37
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.892 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y37
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.967 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y37
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.125     7.092 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.013     7.105    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y244
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.370     6.735    
                         clock uncertainty           -0.170     6.564    
    BITSLICE_RX_TX_X0Y244
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                     -0.141     6.423    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.423    
                         arrival time                          -6.097    
  -------------------------------------------------------------------
                         slack                                  0.327    

Slack (MET) :             0.457ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.886ns  (logic 0.079ns (4.189%)  route 1.807ns (95.811%))
  Logic Levels:           0  
  Clock Path Skew:        -0.424ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.120ns = ( 7.121 - 3.001 ) 
    Source Clock Delay      (SCD):    4.174ns
    Clock Pessimism Removal (CPR):    -0.370ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.964ns (routing 0.788ns, distribution 1.176ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.964     4.174    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X85Y207        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y207        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.253 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[4]/Q
                         net (fo=1, routed)           1.807     6.060    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[4]
    BITSLICE_RX_TX_X0Y239
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.672     7.320    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y9             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.690 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.093     6.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.900 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.975 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.131     7.106 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.015     7.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y239
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.370     6.751    
                         clock uncertainty           -0.170     6.580    
    BITSLICE_RX_TX_X0Y239
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[4])
                                                     -0.064     6.516    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.516    
                         arrival time                          -6.060    
  -------------------------------------------------------------------
                         slack                                  0.457    

Slack (MET) :             0.542ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.814ns  (logic 0.077ns (4.245%)  route 1.737ns (95.755%))
  Logic Levels:           0  
  Clock Path Skew:        -0.464ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.120ns = ( 7.121 - 3.001 ) 
    Source Clock Delay      (SCD):    4.214ns
    Clock Pessimism Removal (CPR):    -0.370ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.004ns (routing 0.788ns, distribution 1.216ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.004     4.214    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X83Y201        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y201        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     4.291 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[3]/Q
                         net (fo=1, routed)           1.737     6.028    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[3]
    BITSLICE_RX_TX_X0Y239
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.672     7.320    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y9             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.690 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.093     6.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.900 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.975 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.131     7.106 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.015     7.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y239
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.370     6.751    
                         clock uncertainty           -0.170     6.580    
    BITSLICE_RX_TX_X0Y239
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                     -0.011     6.569    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.569    
                         arrival time                          -6.028    
  -------------------------------------------------------------------
                         slack                                  0.542    

Slack (MET) :             0.639ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.722ns  (logic 0.077ns (4.472%)  route 1.645ns (95.528%))
  Logic Levels:           0  
  Clock Path Skew:        -0.447ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.107ns = ( 7.108 - 3.001 ) 
    Source Clock Delay      (SCD):    4.184ns
    Clock Pessimism Removal (CPR):    -0.370ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.974ns (routing 0.788ns, distribution 1.186ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.974     4.184    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X87Y211        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y211        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     4.261 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[6]/Q
                         net (fo=1, routed)           1.645     5.906    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[6]
    BITSLICE_RX_TX_X0Y245
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.672     7.320    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y9             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.690 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.096     6.786    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y37
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.892 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y37
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.967 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y37
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.126     7.093 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.015     7.108    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y245
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.370     6.738    
                         clock uncertainty           -0.170     6.567    
    BITSLICE_RX_TX_X0Y245
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                     -0.023     6.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.544    
                         arrival time                          -5.906    
  -------------------------------------------------------------------
                         slack                                  0.639    

Slack (MET) :             0.642ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.729ns  (logic 0.079ns (4.569%)  route 1.650ns (95.431%))
  Logic Levels:           0  
  Clock Path Skew:        -0.411ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.125ns = ( 7.126 - 3.001 ) 
    Source Clock Delay      (SCD):    4.166ns
    Clock Pessimism Removal (CPR):    -0.370ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.956ns (routing 0.788ns, distribution 1.168ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.956     4.166    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X85Y213        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y213        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     4.245 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[6]/Q
                         net (fo=1, routed)           1.650     5.895    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[6]
    BITSLICE_RX_TX_X0Y252
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.672     7.320    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y9             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.690 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.098     6.788    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.905 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.980 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.131     7.111 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.015     7.126    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y252
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.370     6.756    
                         clock uncertainty           -0.170     6.585    
    BITSLICE_RX_TX_X0Y252
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                     -0.049     6.536    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.536    
                         arrival time                          -5.895    
  -------------------------------------------------------------------
                         slack                                  0.642    

Slack (MET) :             0.675ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.701ns  (logic 0.078ns (4.586%)  route 1.623ns (95.414%))
  Logic Levels:           0  
  Clock Path Skew:        -0.442ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.121ns = ( 7.122 - 3.001 ) 
    Source Clock Delay      (SCD):    4.193ns
    Clock Pessimism Removal (CPR):    -0.370ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.983ns (routing 0.788ns, distribution 1.195ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.983     4.193    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X82Y220        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y220        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.271 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[5]/Q
                         net (fo=1, routed)           1.623     5.894    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[5]
    BITSLICE_RX_TX_X0Y249
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.672     7.320    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y9             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.690 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.098     6.788    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.905 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.980 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.129     7.109 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     7.122    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y249
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.370     6.752    
                         clock uncertainty           -0.170     6.581    
    BITSLICE_RX_TX_X0Y249
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                     -0.013     6.568    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.568    
                         arrival time                          -5.894    
  -------------------------------------------------------------------
                         slack                                  0.675    

Slack (MET) :             0.685ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.673ns  (logic 0.079ns (4.722%)  route 1.594ns (95.278%))
  Logic Levels:           0  
  Clock Path Skew:        -0.453ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.107ns = ( 7.108 - 3.001 ) 
    Source Clock Delay      (SCD):    4.190ns
    Clock Pessimism Removal (CPR):    -0.370ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.980ns (routing 0.788ns, distribution 1.192ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.980     4.190    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X81Y213        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y213        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.269 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[6]/Q
                         net (fo=1, routed)           1.594     5.863    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[6]
    BITSLICE_RX_TX_X0Y257
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.672     7.320    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y9             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.690 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.099     6.789    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.895 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.970 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.125     7.095 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.013     7.108    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y257
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.370     6.738    
                         clock uncertainty           -0.170     6.567    
    BITSLICE_RX_TX_X0Y257
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                     -0.020     6.547    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.547    
                         arrival time                          -5.863    
  -------------------------------------------------------------------
                         slack                                  0.685    

Slack (MET) :             0.696ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.648ns  (logic 0.079ns (4.794%)  route 1.569ns (95.206%))
  Logic Levels:           0  
  Clock Path Skew:        -0.454ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.118ns = ( 7.119 - 3.001 ) 
    Source Clock Delay      (SCD):    4.202ns
    Clock Pessimism Removal (CPR):    -0.370ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.992ns (routing 0.788ns, distribution 1.204ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.992     4.202    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X88Y231        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y231        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     4.281 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[2]/Q
                         net (fo=1, routed)           1.569     5.850    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[2]
    BITSLICE_RX_TX_X0Y212
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.672     7.320    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y9             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.097     6.787    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y32
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.904 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y32
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.979 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y32
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.127     7.106 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.013     7.119    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y212
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.370     6.749    
                         clock uncertainty           -0.170     6.578    
    BITSLICE_RX_TX_X0Y212
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                     -0.033     6.545    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.545    
                         arrival time                          -5.850    
  -------------------------------------------------------------------
                         slack                                  0.696    

Slack (MET) :             0.700ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.629ns  (logic 0.079ns (4.850%)  route 1.550ns (95.150%))
  Logic Levels:           0  
  Clock Path Skew:        -0.477ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.103ns = ( 7.104 - 3.001 ) 
    Source Clock Delay      (SCD):    4.210ns
    Clock Pessimism Removal (CPR):    -0.370ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.000ns (routing 0.788ns, distribution 1.212ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.000     4.210    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X84Y203        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y203        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.289 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[3]/Q
                         net (fo=1, routed)           1.550     5.839    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[3]
    BITSLICE_RX_TX_X0Y242
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.672     7.320    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y9             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.690 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.096     6.786    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y37
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.892 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y37
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.967 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y37
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.124     7.091 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     7.104    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y242
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.370     6.734    
                         clock uncertainty           -0.170     6.563    
    BITSLICE_RX_TX_X0Y242
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                     -0.025     6.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.538    
                         arrival time                          -5.839    
  -------------------------------------------------------------------
                         slack                                  0.700    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.517ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.259ns  (logic 0.058ns (22.394%)  route 0.201ns (77.606%))
  Logic Levels:           0  
  Clock Path Skew:        -0.698ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.463ns
    Source Clock Delay      (SCD):    4.464ns
    Clock Pessimism Removal (CPR):    -0.304ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.817ns (routing 0.716ns, distribution 1.101ns)
  Clock Net Delay (Destination): 1.859ns (routing 0.788ns, distribution 1.071ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.817     4.464    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X81Y290        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y290        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     4.522 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[2]/Q
                         net (fo=1, routed)           0.201     4.723    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[2]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.859     4.069    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y9             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.011 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.140     3.151    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.344 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.463 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.304     3.767    
                         clock uncertainty            0.170     3.937    
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[2])
                                                      0.270     4.207    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.207    
                         arrival time                           4.723    
  -------------------------------------------------------------------
                         slack                                  0.517    

Slack (MET) :             0.569ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.306ns  (logic 0.058ns (18.954%)  route 0.248ns (81.046%))
  Logic Levels:           0  
  Clock Path Skew:        -0.700ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.463ns
    Source Clock Delay      (SCD):    4.466ns
    Clock Pessimism Removal (CPR):    -0.304ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.819ns (routing 0.716ns, distribution 1.103ns)
  Clock Net Delay (Destination): 1.859ns (routing 0.788ns, distribution 1.071ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.819     4.466    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X83Y295        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y295        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.058     4.524 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[0]/Q
                         net (fo=1, routed)           0.248     4.772    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.859     4.069    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y9             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.011 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.140     3.151    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.344 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.463 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.304     3.767    
                         clock uncertainty            0.170     3.937    
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[0])
                                                      0.267     4.204    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.204    
                         arrival time                           4.772    
  -------------------------------------------------------------------
                         slack                                  0.569    

Slack (MET) :             0.603ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_upp/rdEn_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.316ns  (logic 0.058ns (18.354%)  route 0.258ns (81.646%))
  Logic Levels:           0  
  Clock Path Skew:        -0.679ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.433ns
    Source Clock Delay      (SCD):    4.478ns
    Clock Pessimism Removal (CPR):    -0.367ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.831ns (routing 0.716ns, distribution 1.115ns)
  Clock Net Delay (Destination): 1.859ns (routing 0.788ns, distribution 1.071ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.831     4.478    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_upp/rsMask_reg[6][9]_0
    SLICE_X82Y301        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_upp/rdEn_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y301        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.058     4.536 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_upp/rdEn_reg[2]/Q
                         net (fo=1, routed)           0.258     4.794    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_upp[2]
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.859     4.069    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y9             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.011 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.142     3.153    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.162     3.315 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.118     3.433 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.367     3.799    
                         clock uncertainty            0.170     3.969    
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[2])
                                                      0.222     4.191    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.191    
                         arrival time                           4.794    
  -------------------------------------------------------------------
                         slack                                  0.603    

Slack (MET) :             0.604ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.314ns  (logic 0.058ns (18.471%)  route 0.256ns (81.529%))
  Logic Levels:           0  
  Clock Path Skew:        -0.512ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.637ns
    Source Clock Delay      (SCD):    4.452ns
    Clock Pessimism Removal (CPR):    -0.304ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.805ns (routing 0.716ns, distribution 1.089ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.805     4.452    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X81Y274        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y274        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     4.510 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[0]/Q
                         net (fo=1, routed)           0.256     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[0]
    BITSLICE_RX_TX_X0Y237
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.859     4.069    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y9             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.011 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.132     3.143    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.320 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.429 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.187     3.616 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     3.637    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y237
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.304     3.941    
                         clock uncertainty            0.170     4.111    
    BITSLICE_RX_TX_X0Y237
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.052     4.163    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.163    
                         arrival time                           4.766    
  -------------------------------------------------------------------
                         slack                                  0.604    

Slack (MET) :             0.613ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.342ns  (logic 0.059ns (17.251%)  route 0.283ns (82.749%))
  Logic Levels:           0  
  Clock Path Skew:        -0.517ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.642ns
    Source Clock Delay      (SCD):    4.463ns
    Clock Pessimism Removal (CPR):    -0.304ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.816ns (routing 0.716ns, distribution 1.100ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.816     4.463    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[10]_0
    SLICE_X84Y286        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y286        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     4.522 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[0]/Q
                         net (fo=1, routed)           0.283     4.805    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[0]
    BITSLICE_RX_TX_X0Y247
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.859     4.069    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y9             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.011 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.140     3.151    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.328 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.437 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.162     3.599 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     3.642    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y247
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.304     3.946    
                         clock uncertainty            0.170     4.116    
    BITSLICE_RX_TX_X0Y247
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.076     4.192    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.192    
                         arrival time                           4.805    
  -------------------------------------------------------------------
                         slack                                  0.613    

Slack (MET) :             0.616ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.325ns  (logic 0.058ns (17.846%)  route 0.267ns (82.154%))
  Logic Levels:           0  
  Clock Path Skew:        -0.513ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.645ns
    Source Clock Delay      (SCD):    4.462ns
    Clock Pessimism Removal (CPR):    -0.304ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.815ns (routing 0.716ns, distribution 1.099ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.815     4.462    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X82Y289        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y289        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.058     4.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[0]/Q
                         net (fo=1, routed)           0.267     4.787    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[0]
    BITSLICE_RX_TX_X0Y250
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.859     4.069    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y9             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.011 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.140     3.151    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.328 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.437 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.187     3.624 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     3.645    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y250
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.304     3.949    
                         clock uncertainty            0.170     4.119    
    BITSLICE_RX_TX_X0Y250
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.052     4.171    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.171    
                         arrival time                           4.787    
  -------------------------------------------------------------------
                         slack                                  0.616    

Slack (MET) :             0.623ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.315ns  (logic 0.059ns (18.730%)  route 0.256ns (81.270%))
  Logic Levels:           0  
  Clock Path Skew:        -0.539ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.610ns
    Source Clock Delay      (SCD):    4.452ns
    Clock Pessimism Removal (CPR):    -0.304ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.805ns (routing 0.716ns, distribution 1.089ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.805     4.452    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X81Y282        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y282        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     4.511 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[0]/Q
                         net (fo=1, routed)           0.256     4.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[0]
    BITSLICE_RX_TX_X0Y244
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.859     4.069    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y9             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.011 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.137     3.148    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y37
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     3.299 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y37
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y37
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.180     3.588 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.022     3.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y244
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.304     3.914    
                         clock uncertainty            0.170     4.084    
    BITSLICE_RX_TX_X0Y244
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.060     4.144    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.144    
                         arrival time                           4.767    
  -------------------------------------------------------------------
                         slack                                  0.623    

Slack (MET) :             0.626ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.378ns  (logic 0.059ns (15.608%)  route 0.319ns (84.392%))
  Logic Levels:           0  
  Clock Path Skew:        -0.685ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.455ns
    Source Clock Delay      (SCD):    4.444ns
    Clock Pessimism Removal (CPR):    -0.304ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.797ns (routing 0.716ns, distribution 1.081ns)
  Clock Net Delay (Destination): 1.859ns (routing 0.788ns, distribution 1.071ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.797     4.444    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X85Y284        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y284        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     4.503 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[0]/Q
                         net (fo=1, routed)           0.319     4.822    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.859     4.069    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y9             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.011 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.132     3.143    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.336 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.455 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.304     3.759    
                         clock uncertainty            0.170     3.929    
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[0])
                                                      0.267     4.196    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.196    
                         arrival time                           4.822    
  -------------------------------------------------------------------
                         slack                                  0.626    

Slack (MET) :             0.635ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.344ns  (logic 0.059ns (17.151%)  route 0.285ns (82.849%))
  Logic Levels:           0  
  Clock Path Skew:        -0.512ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.637ns
    Source Clock Delay      (SCD):    4.452ns
    Clock Pessimism Removal (CPR):    -0.304ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.805ns (routing 0.716ns, distribution 1.089ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.805     4.452    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X81Y274        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y274        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     4.511 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[1]/Q
                         net (fo=1, routed)           0.285     4.796    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[1]
    BITSLICE_RX_TX_X0Y237
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.859     4.069    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y9             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.011 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.132     3.143    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.320 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.429 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.187     3.616 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     3.637    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y237
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.304     3.941    
                         clock uncertainty            0.170     4.111    
    BITSLICE_RX_TX_X0Y237
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                      0.051     4.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.162    
                         arrival time                           4.796    
  -------------------------------------------------------------------
                         slack                                  0.635    

Slack (MET) :             0.641ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.315ns  (logic 0.059ns (18.730%)  route 0.256ns (81.270%))
  Logic Levels:           0  
  Clock Path Skew:        -0.511ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.653ns
    Source Clock Delay      (SCD):    4.467ns
    Clock Pessimism Removal (CPR):    -0.304ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.820ns (routing 0.716ns, distribution 1.104ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.820     4.467    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X81Y291        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y291        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     4.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[0]/Q
                         net (fo=1, routed)           0.256     4.782    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[0]
    BITSLICE_RX_TX_X0Y252
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.859     4.069    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y9             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.011 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.140     3.151    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.328 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.437 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     3.629 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     3.653    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y252
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.304     3.957    
                         clock uncertainty            0.170     4.127    
    BITSLICE_RX_TX_X0Y252
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.015     4.142    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.142    
                         arrival time                           4.782    
  -------------------------------------------------------------------
                         slack                                  0.641    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  pll_clk[2]_DIV

Setup :            0  Failing Endpoints,  Worst Slack        0.712ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.573ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.712ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.411ns  (logic 0.080ns (5.668%)  route 1.331ns (94.332%))
  Logic Levels:           0  
  Clock Path Skew:        -0.550ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.988ns = ( 6.989 - 3.001 ) 
    Source Clock Delay      (SCD):    4.239ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.029ns (routing 0.788ns, distribution 1.241ns)
  Clock Net Delay (Destination): 1.688ns (routing 0.716ns, distribution 0.972ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.029     4.239    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/div_clk
    SLICE_X85Y333        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y333        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     4.319 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[0]/Q
                         net (fo=6, routed)           1.331     5.650    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/clb2phy_t_b_low[0]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.688     7.336    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.706 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.102     6.808    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.989 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.299     6.690    
                         clock uncertainty           -0.170     6.520    
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[0])
                                                     -0.158     6.362    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.362    
                         arrival time                          -5.650    
  -------------------------------------------------------------------
                         slack                                  0.712    

Slack (MET) :             0.819ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][7]/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.513ns  (logic 0.079ns (5.221%)  route 1.434ns (94.779%))
  Logic Levels:           0  
  Clock Path Skew:        -0.445ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.141ns = ( 7.142 - 3.001 ) 
    Source Clock Delay      (SCD):    4.229ns
    Clock Pessimism Removal (CPR):    -0.357ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.019ns (routing 0.788ns, distribution 1.231ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.019     4.229    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X90Y265        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y265        FDSE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     4.308 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][7]/Q
                         net (fo=1, routed)           1.434     5.742    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ACT_n[7]
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.688     7.336    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.706 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.104     6.810    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.927 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.002 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.128     7.130 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.012     7.142    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.357     6.784    
                         clock uncertainty           -0.170     6.614    
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                     -0.053     6.561    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.561    
                         arrival time                          -5.742    
  -------------------------------------------------------------------
                         slack                                  0.819    

Slack (MET) :             0.836ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.313ns  (logic 0.080ns (6.091%)  route 1.233ns (93.909%))
  Logic Levels:           0  
  Clock Path Skew:        -0.542ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.996ns = ( 6.997 - 3.001 ) 
    Source Clock Delay      (SCD):    4.239ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.029ns (routing 0.788ns, distribution 1.241ns)
  Clock Net Delay (Destination): 1.688ns (routing 0.716ns, distribution 0.972ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.029     4.239    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/div_clk
    SLICE_X85Y333        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y333        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     4.319 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[0]/Q
                         net (fo=6, routed)           1.233     5.552    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/clb2phy_t_b_low[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.688     7.336    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.706 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.099     6.805    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.922 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.997 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.299     6.698    
                         clock uncertainty           -0.170     6.528    
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[0])
                                                     -0.140     6.388    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.388    
                         arrival time                          -5.552    
  -------------------------------------------------------------------
                         slack                                  0.836    

Slack (MET) :             0.917ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][119]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.459ns  (logic 0.078ns (5.346%)  route 1.381ns (94.654%))
  Logic Levels:           0  
  Clock Path Skew:        -0.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.131ns = ( 7.132 - 3.001 ) 
    Source Clock Delay      (SCD):    4.255ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.045ns (routing 0.788ns, distribution 1.257ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.045     4.255    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X82Y346        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][119]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y346        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.333 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][119]/Q
                         net (fo=1, routed)           1.381     5.714    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_ADR[7]
    BITSLICE_RX_TX_X0Y306
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.688     7.336    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.706 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.105     6.811    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.992 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT1[26])
                                                      0.125     7.117 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT1[26]
                         net (fo=1, routed)           0.015     7.132    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT1[26]
    BITSLICE_RX_TX_X0Y306
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.299     6.833    
                         clock uncertainty           -0.170     6.663    
    BITSLICE_RX_TX_X0Y306
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                     -0.032     6.631    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.631    
                         arrival time                          -5.714    
  -------------------------------------------------------------------
                         slack                                  0.917    

Slack (MET) :             0.932ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][111]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.433ns  (logic 0.078ns (5.443%)  route 1.355ns (94.557%))
  Logic Levels:           0  
  Clock Path Skew:        -0.446ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.139ns = ( 7.140 - 3.001 ) 
    Source Clock Delay      (SCD):    4.286ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.076ns (routing 0.788ns, distribution 1.288ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.076     4.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X83Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][111]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y315        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     4.364 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][111]/Q
                         net (fo=1, routed)           1.355     5.719    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[7]
    BITSLICE_RX_TX_X0Y275
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.688     7.336    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.706 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.100     6.806    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.998 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.129     7.127 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     7.140    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y275
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.299     6.841    
                         clock uncertainty           -0.170     6.671    
    BITSLICE_RX_TX_X0Y275
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                     -0.020     6.651    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.651    
                         arrival time                          -5.719    
  -------------------------------------------------------------------
                         slack                                  0.932    

Slack (MET) :             0.945ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][88]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.377ns  (logic 0.080ns (5.810%)  route 1.297ns (94.190%))
  Logic Levels:           0  
  Clock Path Skew:        -0.430ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.138ns = ( 7.139 - 3.001 ) 
    Source Clock Delay      (SCD):    4.269ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.059ns (routing 0.788ns, distribution 1.271ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.059     4.269    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y325        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][88]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y325        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     4.349 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][88]/Q
                         net (fo=1, routed)           1.297     5.646    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[0]
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.688     7.336    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.706 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.099     6.805    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.922 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.997 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.129     7.126 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     7.139    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.299     6.840    
                         clock uncertainty           -0.170     6.670    
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                     -0.079     6.591    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.591    
                         arrival time                          -5.646    
  -------------------------------------------------------------------
                         slack                                  0.945    

Slack (MET) :             0.952ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.176ns  (logic 0.081ns (6.886%)  route 1.095ns (93.114%))
  Logic Levels:           0  
  Clock Path Skew:        -0.550ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.988ns = ( 6.989 - 3.001 ) 
    Source Clock Delay      (SCD):    4.239ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.029ns (routing 0.788ns, distribution 1.241ns)
  Clock Net Delay (Destination): 1.688ns (routing 0.716ns, distribution 0.972ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.029     4.239    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/div_clk
    SLICE_X85Y333        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y333        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     4.320 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[1]/Q
                         net (fo=6, routed)           1.095     5.415    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/clb2phy_t_b_low[1]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.688     7.336    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.706 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.102     6.808    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.989 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.299     6.690    
                         clock uncertainty           -0.170     6.520    
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[1])
                                                     -0.153     6.367    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.367    
                         arrival time                          -5.415    
  -------------------------------------------------------------------
                         slack                                  0.952    

Slack (MET) :             0.960ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.414ns  (logic 0.079ns (5.587%)  route 1.335ns (94.413%))
  Logic Levels:           0  
  Clock Path Skew:        -0.437ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.143ns = ( 7.144 - 3.001 ) 
    Source Clock Delay      (SCD):    4.281ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.071ns (routing 0.788ns, distribution 1.283ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.071     4.281    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y355        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y355        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.360 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][7]/Q
                         net (fo=1, routed)           1.335     5.695    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ODT[7]
    BITSLICE_RX_TX_X0Y301
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.688     7.336    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.706 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.104     6.810    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.927 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.002 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.129     7.131 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     7.144    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y301
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.299     6.845    
                         clock uncertainty           -0.170     6.675    
    BITSLICE_RX_TX_X0Y301
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                     -0.020     6.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.655    
                         arrival time                          -5.695    
  -------------------------------------------------------------------
                         slack                                  0.960    

Slack (MET) :             0.960ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][50]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.365ns  (logic 0.081ns (5.932%)  route 1.284ns (94.068%))
  Logic Levels:           0  
  Clock Path Skew:        -0.444ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.128ns = ( 7.129 - 3.001 ) 
    Source Clock Delay      (SCD):    4.273ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.063ns (routing 0.788ns, distribution 1.275ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.063     4.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y341        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][50]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y341        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     4.354 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][50]/Q
                         net (fo=2, routed)           1.284     5.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_ADR[2]
    BITSLICE_RX_TX_X0Y293
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.688     7.336    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.706 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.102     6.808    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.989 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT1[26])
                                                      0.125     7.114 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT1[26]
                         net (fo=1, routed)           0.015     7.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT1[26]
    BITSLICE_RX_TX_X0Y293
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.299     6.830    
                         clock uncertainty           -0.170     6.660    
    BITSLICE_RX_TX_X0Y293
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                     -0.061     6.599    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.599    
                         arrival time                          -5.638    
  -------------------------------------------------------------------
                         slack                                  0.960    

Slack (MET) :             0.979ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][22]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.371ns  (logic 0.081ns (5.907%)  route 1.290ns (94.093%))
  Logic Levels:           0  
  Clock Path Skew:        -0.438ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.129ns = ( 7.130 - 3.001 ) 
    Source Clock Delay      (SCD):    4.268ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.058ns (routing 0.788ns, distribution 1.270ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.058     4.268    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y341        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][22]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y341        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     4.349 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][22]/Q
                         net (fo=4, routed)           1.290     5.639    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_ADR[5]
    BITSLICE_RX_TX_X0Y297
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.409 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.648 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.688     7.336    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.706 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.102     6.808    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.989 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.126     7.115 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.015     7.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y297
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.299     6.831    
                         clock uncertainty           -0.170     6.661    
    BITSLICE_RX_TX_X0Y297
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                     -0.043     6.618    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.618    
                         arrival time                          -5.639    
  -------------------------------------------------------------------
                         slack                                  0.979    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.573ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][14]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.311ns  (logic 0.059ns (18.945%)  route 0.252ns (81.055%))
  Logic Levels:           0  
  Clock Path Skew:        -0.517ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.655ns
    Source Clock Delay      (SCD):    4.471ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.824ns (routing 0.716ns, distribution 1.108ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.824     4.471    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y323        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     4.530 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][14]/Q
                         net (fo=2, routed)           0.252     4.782    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/clb2phy_wr_dq6[6]
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.880     4.090    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.032 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.138     3.170    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     3.321 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.430 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.182     3.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     3.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.299     3.954    
                         clock uncertainty            0.170     4.124    
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                      0.085     4.209    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.209    
                         arrival time                           4.782    
  -------------------------------------------------------------------
                         slack                                  0.573    

Slack (MET) :             0.583ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][92]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.305ns  (logic 0.058ns (18.991%)  route 0.247ns (81.009%))
  Logic Levels:           0  
  Clock Path Skew:        -0.502ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.664ns
    Source Clock Delay      (SCD):    4.464ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.817ns (routing 0.716ns, distribution 1.101ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.817     4.464    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y333        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][92]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y333        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     4.522 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][92]/Q
                         net (fo=2, routed)           0.247     4.770    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[3]
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.880     4.090    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.032 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.141     3.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.350 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.459 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.187     3.646 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.018     3.664    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.299     3.963    
                         clock uncertainty            0.170     4.133    
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                      0.054     4.187    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.187    
                         arrival time                           4.770    
  -------------------------------------------------------------------
                         slack                                  0.583    

Slack (MET) :             0.587ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][84]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.313ns  (logic 0.060ns (19.150%)  route 0.253ns (80.850%))
  Logic Levels:           0  
  Clock Path Skew:        -0.497ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.667ns
    Source Clock Delay      (SCD):    4.462ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.815ns (routing 0.716ns, distribution 1.099ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.815     4.462    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X82Y334        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][84]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y334        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.060     4.522 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][84]/Q
                         net (fo=2, routed)           0.253     4.775    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[3]
    BITSLICE_RX_TX_X0Y289
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.880     4.090    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.032 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.141     3.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.350 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.459 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.187     3.646 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     3.667    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y289
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.299     3.966    
                         clock uncertainty            0.170     4.136    
    BITSLICE_RX_TX_X0Y289
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                      0.053     4.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.189    
                         arrival time                           4.775    
  -------------------------------------------------------------------
                         slack                                  0.587    

Slack (MET) :             0.594ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][14]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.316ns  (logic 0.059ns (18.646%)  route 0.257ns (81.354%))
  Logic Levels:           0  
  Clock Path Skew:        -0.517ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.655ns
    Source Clock Delay      (SCD):    4.471ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.824ns (routing 0.716ns, distribution 1.108ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.824     4.471    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y323        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     4.530 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][14]/Q
                         net (fo=2, routed)           0.257     4.787    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/clb2phy_wr_dq6[5]
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.880     4.090    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.032 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.138     3.170    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     3.321 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.430 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.182     3.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     3.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.299     3.954    
                         clock uncertainty            0.170     4.124    
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                      0.069     4.193    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.193    
                         arrival time                           4.787    
  -------------------------------------------------------------------
                         slack                                  0.594    

Slack (MET) :             0.602ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.310ns  (logic 0.059ns (19.023%)  route 0.251ns (80.977%))
  Logic Levels:           0  
  Clock Path Skew:        -0.515ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.655ns
    Source Clock Delay      (SCD):    4.469ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.822ns (routing 0.716ns, distribution 1.106ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.822     4.469    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y323        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.059     4.528 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][10]/Q
                         net (fo=2, routed)           0.251     4.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/clb2phy_wr_dq6[2]
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.880     4.090    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.032 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.138     3.170    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     3.321 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.430 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.182     3.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     3.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.299     3.954    
                         clock uncertainty            0.170     4.124    
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                      0.053     4.177    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.177    
                         arrival time                           4.779    
  -------------------------------------------------------------------
                         slack                                  0.602    

Slack (MET) :             0.604ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][39]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.318ns  (logic 0.059ns (18.553%)  route 0.259ns (81.447%))
  Logic Levels:           0  
  Clock Path Skew:        -0.540ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.636ns
    Source Clock Delay      (SCD):    4.474ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.827ns (routing 0.716ns, distribution 1.111ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.827     4.474    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y341        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][39]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y341        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.059     4.533 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][39]/Q
                         net (fo=1, routed)           0.259     4.792    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_ADR[7]
    BITSLICE_RX_TX_X0Y295
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.880     4.090    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.032 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.146     3.178    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     3.329 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.438 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.177     3.615 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     3.636    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y295
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.299     3.935    
                         clock uncertainty            0.170     4.105    
    BITSLICE_RX_TX_X0Y295
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                      0.084     4.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.189    
                         arrival time                           4.792    
  -------------------------------------------------------------------
                         slack                                  0.604    

Slack (MET) :             0.604ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][84]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.321ns  (logic 0.060ns (18.674%)  route 0.261ns (81.326%))
  Logic Levels:           0  
  Clock Path Skew:        -0.497ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.667ns
    Source Clock Delay      (SCD):    4.462ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.815ns (routing 0.716ns, distribution 1.099ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.815     4.462    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X82Y334        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][84]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y334        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.060     4.522 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][84]/Q
                         net (fo=2, routed)           0.261     4.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[4]
    BITSLICE_RX_TX_X0Y289
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.880     4.090    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.032 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.141     3.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.350 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.459 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.187     3.646 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     3.667    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y289
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.299     3.966    
                         clock uncertainty            0.170     4.136    
    BITSLICE_RX_TX_X0Y289
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[4])
                                                      0.044     4.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.180    
                         arrival time                           4.783    
  -------------------------------------------------------------------
                         slack                                  0.604    

Slack (MET) :             0.607ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][34]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.306ns  (logic 0.060ns (19.588%)  route 0.246ns (80.412%))
  Logic Levels:           0  
  Clock Path Skew:        -0.540ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.636ns
    Source Clock Delay      (SCD):    4.474ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.827ns (routing 0.716ns, distribution 1.111ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.827     4.474    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y341        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][34]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y341        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.060     4.534 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][34]/Q
                         net (fo=2, routed)           0.246     4.781    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_ADR[2]
    BITSLICE_RX_TX_X0Y295
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.880     4.090    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.032 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.146     3.178    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     3.329 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.438 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.177     3.615 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     3.636    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y295
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.299     3.935    
                         clock uncertainty            0.170     4.105    
    BITSLICE_RX_TX_X0Y295
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                      0.069     4.174    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.174    
                         arrival time                           4.781    
  -------------------------------------------------------------------
                         slack                                  0.607    

Slack (MET) :             0.607ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[4]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.312ns  (logic 0.058ns (18.581%)  route 0.254ns (81.419%))
  Logic Levels:           0  
  Clock Path Skew:        -0.517ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.655ns
    Source Clock Delay      (SCD):    4.471ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.824ns (routing 0.716ns, distribution 1.108ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.824     4.471    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y323        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     4.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][12]/Q
                         net (fo=2, routed)           0.254     4.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/clb2phy_wr_dq6[4]
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[4]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.880     4.090    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.032 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.138     3.170    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     3.321 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.430 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.182     3.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     3.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.299     3.954    
                         clock uncertainty            0.170     4.124    
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[4])
                                                      0.052     4.176    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.176    
                         arrival time                           4.783    
  -------------------------------------------------------------------
                         slack                                  0.607    

Slack (MET) :             0.607ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][78]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.357ns  (logic 0.059ns (16.546%)  route 0.298ns (83.454%))
  Logic Levels:           0  
  Clock Path Skew:        -0.499ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.667ns
    Source Clock Delay      (SCD):    4.464ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.817ns (routing 0.716ns, distribution 1.101ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.817     4.464    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y333        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][78]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y333        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.059     4.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][78]/Q
                         net (fo=2, routed)           0.298     4.821    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[5]
    BITSLICE_RX_TX_X0Y290
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41406, routed)       1.880     4.090    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.032 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.141     3.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.350 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.459 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.186     3.645 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.022     3.667    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y290
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.299     3.966    
                         clock uncertainty            0.170     4.136    
    BITSLICE_RX_TX_X0Y290
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                      0.078     4.214    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.214    
                         arrival time                           4.821    
  -------------------------------------------------------------------
                         slack                                  0.607    





---------------------------------------------------------------------------------------------------
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack       49.569ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             49.569ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.456ns  (logic 0.081ns (17.763%)  route 0.375ns (82.237%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y295                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
    SLICE_X101Y295       FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.375     0.456    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[1]
    SLICE_X103Y294       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X103Y294       FDCE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.456    
  -------------------------------------------------------------------
                         slack                                 49.569    

Slack (MET) :             49.611ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.414ns  (logic 0.079ns (19.082%)  route 0.335ns (80.918%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y292                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
    SLICE_X101Y292       FDCE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.335     0.414    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[3]
    SLICE_X101Y292       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X101Y292       FDCE (Setup_HFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.414    
  -------------------------------------------------------------------
                         slack                                 49.611    

Slack (MET) :             49.665ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.360ns  (logic 0.080ns (22.222%)  route 0.280ns (77.778%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y295                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
    SLICE_X101Y295       FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.280     0.360    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[0]
    SLICE_X103Y294       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X103Y294       FDCE (Setup_GFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.360    
  -------------------------------------------------------------------
                         slack                                 49.665    

Slack (MET) :             49.707ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.318ns  (logic 0.079ns (24.843%)  route 0.239ns (75.157%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y292                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
    SLICE_X101Y292       FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.239     0.318    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[2]
    SLICE_X102Y292       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X102Y292       FDCE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.318    
  -------------------------------------------------------------------
                         slack                                 49.707    

Slack (MET) :             49.709ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.316ns  (logic 0.079ns (25.000%)  route 0.237ns (75.000%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y292                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
    SLICE_X101Y292       FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.237     0.316    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[0]
    SLICE_X102Y292       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X102Y292       FDCE (Setup_DFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.316    
  -------------------------------------------------------------------
                         slack                                 49.709    

Slack (MET) :             49.731ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.294ns  (logic 0.078ns (26.531%)  route 0.216ns (73.469%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y295                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
    SLICE_X104Y295       FDCE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     0.078 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.216     0.294    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[3]
    SLICE_X104Y295       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X104Y295       FDCE (Setup_GFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.294    
  -------------------------------------------------------------------
                         slack                                 49.731    

Slack (MET) :             49.734ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.291ns  (logic 0.081ns (27.835%)  route 0.210ns (72.165%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y292                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
    SLICE_X101Y292       FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.210     0.291    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[1]
    SLICE_X102Y292       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X102Y292       FDCE (Setup_GFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.291    
  -------------------------------------------------------------------
                         slack                                 49.734    

Slack (MET) :             49.743ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.282ns  (logic 0.077ns (27.305%)  route 0.205ns (72.695%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y295                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
    SLICE_X104Y295       FDCE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     0.077 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.205     0.282    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[2]
    SLICE_X104Y295       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X104Y295       FDCE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.282    
  -------------------------------------------------------------------
                         slack                                 49.743    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack       11.546ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             11.546ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.479ns  (logic 0.079ns (16.493%)  route 0.400ns (83.507%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y306                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
    SLICE_X94Y306        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/Q
                         net (fo=1, routed)           0.400     0.479    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[6]
    SLICE_X96Y308        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X96Y308        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.479    
  -------------------------------------------------------------------
                         slack                                 11.546    

Slack (MET) :             11.614ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.411ns  (logic 0.079ns (19.221%)  route 0.332ns (80.779%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y306                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
    SLICE_X94Y306        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/Q
                         net (fo=1, routed)           0.332     0.411    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[5]
    SLICE_X95Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X95Y311        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.411    
  -------------------------------------------------------------------
                         slack                                 11.614    

Slack (MET) :             11.664ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.361ns  (logic 0.078ns (21.607%)  route 0.283ns (78.393%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y311                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
    SLICE_X94Y311        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/Q
                         net (fo=1, routed)           0.283     0.361    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[0]
    SLICE_X96Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X96Y311        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.361    
  -------------------------------------------------------------------
                         slack                                 11.664    

Slack (MET) :             11.690ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.335ns  (logic 0.079ns (23.582%)  route 0.256ns (76.418%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y301                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
    SLICE_X96Y301        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/Q
                         net (fo=1, routed)           0.256     0.335    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[7]
    SLICE_X96Y301        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X96Y301        FDRE (Setup_BFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.335    
  -------------------------------------------------------------------
                         slack                                 11.690    

Slack (MET) :             11.698ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.327ns  (logic 0.078ns (23.853%)  route 0.249ns (76.147%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y311                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
    SLICE_X94Y311        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/Q
                         net (fo=1, routed)           0.249     0.327    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[1]
    SLICE_X95Y310        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X95Y310        FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.327    
  -------------------------------------------------------------------
                         slack                                 11.698    

Slack (MET) :             11.705ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.320ns  (logic 0.078ns (24.375%)  route 0.242ns (75.625%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y302                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
    SLICE_X96Y302        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/Q
                         net (fo=1, routed)           0.242     0.320    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[8]
    SLICE_X96Y302        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X96Y302        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.320    
  -------------------------------------------------------------------
                         slack                                 11.705    

Slack (MET) :             11.735ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.290ns  (logic 0.078ns (26.897%)  route 0.212ns (73.103%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y301                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
    SLICE_X96Y301        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/Q
                         net (fo=1, routed)           0.212     0.290    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[3]
    SLICE_X95Y303        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X95Y303        FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.290    
  -------------------------------------------------------------------
                         slack                                 11.735    

Slack (MET) :             11.736ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.289ns  (logic 0.078ns (26.990%)  route 0.211ns (73.010%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y311                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
    SLICE_X94Y311        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/Q
                         net (fo=1, routed)           0.211     0.289    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[4]
    SLICE_X94Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X94Y311        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.289    
  -------------------------------------------------------------------
                         slack                                 11.736    

Slack (MET) :             11.744ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.281ns  (logic 0.078ns (27.758%)  route 0.203ns (72.242%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y306                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
    SLICE_X94Y306        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/Q
                         net (fo=1, routed)           0.203     0.281    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[2]
    SLICE_X95Y308        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X95Y308        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.281    
  -------------------------------------------------------------------
                         slack                                 11.744    

Slack (MET) :             11.785ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.240ns  (logic 0.081ns (33.745%)  route 0.159ns (66.255%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y314                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
    SLICE_X95Y314        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/Q
                         net (fo=2, routed)           0.159     0.240    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/D[0]
    SLICE_X94Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X94Y314        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.240    
  -------------------------------------------------------------------
                         slack                                 11.785    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout6

Setup :            0  Failing Endpoints,  Worst Slack        1.456ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.139ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.456ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout0 rise@3.001ns)
  Data Path Delay:        1.132ns  (logic 0.078ns (6.890%)  route 1.054ns (93.110%))
  Logic Levels:           0  
  Clock Path Skew:        -0.249ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.500ns = ( 10.501 - 6.001 ) 
    Source Clock Delay      (SCD):    4.278ns = ( 7.278 - 3.001 ) 
    Clock Pessimism Removal (CPR):    -0.471ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      2.068ns (routing 0.788ns, distribution 1.280ns)
  Clock Net Delay (Destination): 1.841ns (routing 0.726ns, distribution 1.115ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     3.101    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     3.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     3.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     4.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     5.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     4.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     5.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.068     7.278    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X83Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y324        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     7.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/Q
                         net (fo=1, routed)           1.054     8.410    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts
    SLICE_X83Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     7.779    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     8.636    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.660 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.841    10.501    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X83Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/C
                         clock pessimism             -0.471    10.030    
                         clock uncertainty           -0.188     9.842    
    SLICE_X83Y343        FDRE (Setup_AFF2_SLICEM_C_D)
                                                      0.025     9.867    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg
  -------------------------------------------------------------------
                         required time                          9.867    
                         arrival time                          -8.410    
  -------------------------------------------------------------------
                         slack                                  1.456    

Slack (MET) :             4.341ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[18]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[18].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.684ns  (logic 0.079ns (11.550%)  route 0.605ns (88.450%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y311                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[18]/C
    SLICE_X87Y311        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[18]/Q
                         net (fo=1, routed)           0.605     0.684    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[18]
    SLICE_X87Y320        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[18].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X87Y320        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[18].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.684    
  -------------------------------------------------------------------
                         slack                                  4.341    

Slack (MET) :             4.345ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[21].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.680ns  (logic 0.080ns (11.765%)  route 0.600ns (88.235%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y325                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[21]/C
    SLICE_X89Y325        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[21]/Q
                         net (fo=1, routed)           0.600     0.680    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[21]
    SLICE_X89Y329        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[21].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X89Y329        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[21].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.680    
  -------------------------------------------------------------------
                         slack                                  4.345    

Slack (MET) :             4.462ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.563ns  (logic 0.081ns (14.387%)  route 0.482ns (85.613%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y317                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[6]/C
    SLICE_X88Y317        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[6]/Q
                         net (fo=1, routed)           0.482     0.563    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[6]
    SLICE_X88Y317        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X88Y317        FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[6].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.563    
  -------------------------------------------------------------------
                         slack                                  4.462    

Slack (MET) :             4.487ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.538ns  (logic 0.079ns (14.684%)  route 0.459ns (85.316%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y333                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[0]/C
    SLICE_X85Y333        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[0]/Q
                         net (fo=1, routed)           0.459     0.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[0]
    SLICE_X89Y335        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X89Y335        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.538    
  -------------------------------------------------------------------
                         slack                                  4.487    

Slack (MET) :             4.558ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[26]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[26].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.467ns  (logic 0.078ns (16.702%)  route 0.389ns (83.298%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y335                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[26]/C
    SLICE_X87Y335        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[26]/Q
                         net (fo=1, routed)           0.389     0.467    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[26]
    SLICE_X86Y341        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[26].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X86Y341        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[26].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.467    
  -------------------------------------------------------------------
                         slack                                  4.558    

Slack (MET) :             4.565ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[12].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.460ns  (logic 0.080ns (17.391%)  route 0.380ns (82.609%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y315                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[12]/C
    SLICE_X88Y315        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[12]/Q
                         net (fo=1, routed)           0.380     0.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[12]
    SLICE_X88Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[12].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X88Y315        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[12].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.460    
  -------------------------------------------------------------------
                         slack                                  4.565    

Slack (MET) :             4.572ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.453ns  (logic 0.080ns (17.660%)  route 0.373ns (82.340%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y325                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[4]/C
    SLICE_X85Y325        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[4]/Q
                         net (fo=1, routed)           0.373     0.453    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[4]
    SLICE_X85Y325        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X85Y325        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[4].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.453    
  -------------------------------------------------------------------
                         slack                                  4.572    

Slack (MET) :             4.614ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[24]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[24].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.411ns  (logic 0.079ns (19.221%)  route 0.332ns (80.779%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y335                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[24]/C
    SLICE_X89Y335        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[24]/Q
                         net (fo=1, routed)           0.332     0.411    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[24]
    SLICE_X89Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[24].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X89Y343        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[24].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.411    
  -------------------------------------------------------------------
                         slack                                  4.614    

Slack (MET) :             4.616ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[19]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[19].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.409ns  (logic 0.078ns (19.071%)  route 0.331ns (80.929%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y323                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[19]/C
    SLICE_X90Y323        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[19]/Q
                         net (fo=1, routed)           0.331     0.409    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[19]
    SLICE_X90Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[19].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X90Y323        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[19].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.409    
  -------------------------------------------------------------------
                         slack                                  4.616    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.139ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.558ns  (logic 0.039ns (6.989%)  route 0.519ns (93.011%))
  Logic Levels:           0  
  Clock Path Skew:        0.183ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.589ns
    Source Clock Delay      (SCD):    2.691ns
    Clock Pessimism Removal (CPR):    -0.285ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.136ns (routing 0.435ns, distribution 0.701ns)
  Clock Net Delay (Destination): 1.286ns (routing 0.492ns, distribution 0.794ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.136     2.691    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X83Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y324        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.730 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/Q
                         net (fo=1, routed)           0.519     3.249    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts
    SLICE_X83Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.286     2.589    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X83Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/C
                         clock pessimism              0.285     2.874    
                         clock uncertainty            0.188     3.062    
    SLICE_X83Y343        FDRE (Hold_AFF2_SLICEM_C_D)
                                                      0.047     3.109    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg
  -------------------------------------------------------------------
                         required time                         -3.109    
                         arrival time                           3.249    
  -------------------------------------------------------------------
                         slack                                  0.139    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Setup :            0  Failing Endpoints,  Worst Slack        0.406ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.180ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.406ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_13/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.223ns  (logic 0.079ns (6.462%)  route 1.144ns (93.538%))
  Logic Levels:           0  
  Clock Path Skew:        -0.207ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.066ns = ( 7.019 - 1.953 ) 
    Source Clock Delay      (SCD):    4.983ns
    Clock Pessimism Removal (CPR):    -0.290ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.424ns (routing 0.878ns, distribution 1.546ns)
  Clock Net Delay (Destination): 2.116ns (routing 0.798ns, distribution 1.318ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.424     4.983    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X85Y108        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_13/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y108        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     5.062 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_13/Q
                         net (fo=242, routed)         1.144     6.206    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/peripheral_aresetn[0]_repN_13_alias
    SLICE_X81Y120        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     4.034    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.664 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.879    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.903 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.116     7.019    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X81Y120        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/C
                         clock pessimism             -0.290     6.729    
                         clock uncertainty           -0.051     6.677    
    SLICE_X81Y120        FDCE (Recov_AFF_SLICEL_C_CLR)
                                                     -0.066     6.611    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]
  -------------------------------------------------------------------
                         required time                          6.611    
                         arrival time                          -6.206    
  -------------------------------------------------------------------
                         slack                                  0.406    

Slack (MET) :             0.952ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_33/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.747ns  (logic 0.076ns (10.169%)  route 0.671ns (89.831%))
  Logic Levels:           0  
  Clock Path Skew:        -0.136ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.981ns = ( 6.934 - 1.953 ) 
    Source Clock Delay      (SCD):    4.827ns
    Clock Pessimism Removal (CPR):    -0.290ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.268ns (routing 0.878ns, distribution 1.390ns)
  Clock Net Delay (Destination): 2.031ns (routing 0.798ns, distribution 1.233ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.268     4.827    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X78Y120        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_33/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y120        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.903 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_33/Q
                         net (fo=130, routed)         0.671     5.574    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/peripheral_aresetn[0]_repN_33_alias
    SLICE_X75Y111        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     4.034    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.664 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.879    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.903 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.031     6.934    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X75Y111        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/C
                         clock pessimism             -0.290     6.644    
                         clock uncertainty           -0.051     6.593    
    SLICE_X75Y111        FDCE (Recov_EFF_SLICEM_C_CLR)
                                                     -0.066     6.527    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          6.527    
                         arrival time                          -5.574    
  -------------------------------------------------------------------
                         slack                                  0.952    

Slack (MET) :             1.276ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_33/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.465ns  (logic 0.076ns (16.351%)  route 0.389ns (83.649%))
  Logic Levels:           0  
  Clock Path Skew:        -0.095ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.964ns = ( 6.917 - 1.953 ) 
    Source Clock Delay      (SCD):    4.827ns
    Clock Pessimism Removal (CPR):    -0.232ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.268ns (routing 0.878ns, distribution 1.390ns)
  Clock Net Delay (Destination): 2.014ns (routing 0.798ns, distribution 1.216ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.268     4.827    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X78Y120        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_33/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y120        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.903 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_33/Q
                         net (fo=130, routed)         0.389     5.292    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/peripheral_aresetn[0]_repN_33_alias
    SLICE_X74Y120        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     4.034    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.664 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.879    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.903 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.014     6.917    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X74Y120        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C
                         clock pessimism             -0.232     6.685    
                         clock uncertainty           -0.051     6.634    
    SLICE_X74Y120        FDCE (Recov_AFF_SLICEL_C_CLR)
                                                     -0.066     6.568    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          6.568    
                         arrival time                          -5.292    
  -------------------------------------------------------------------
                         slack                                  1.276    

Slack (MET) :             1.390ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_13/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.402ns  (logic 0.079ns (19.632%)  route 0.323ns (80.368%))
  Logic Levels:           0  
  Clock Path Skew:        -0.043ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.109ns = ( 7.062 - 1.953 ) 
    Source Clock Delay      (SCD):    4.983ns
    Clock Pessimism Removal (CPR):    -0.169ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.424ns (routing 0.878ns, distribution 1.546ns)
  Clock Net Delay (Destination): 2.159ns (routing 0.798ns, distribution 1.361ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.424     4.983    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X85Y108        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_13/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y108        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     5.062 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_13/Q
                         net (fo=242, routed)         0.323     5.385    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/peripheral_aresetn[0]_repN_13_alias
    SLICE_X85Y113        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     4.034    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.664 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.879    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.903 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.159     7.062    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X85Y113        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/C
                         clock pessimism             -0.169     6.893    
                         clock uncertainty           -0.051     6.842    
    SLICE_X85Y113        FDCE (Recov_EFF_SLICEL_C_CLR)
                                                     -0.066     6.776    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]
  -------------------------------------------------------------------
                         required time                          6.776    
                         arrival time                          -5.385    
  -------------------------------------------------------------------
                         slack                                  1.390    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.180ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_13/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.186ns  (logic 0.039ns (20.972%)  route 0.147ns (79.029%))
  Logic Levels:           0  
  Clock Path Skew:        0.026ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.894ns
    Source Clock Delay      (SCD):    3.018ns
    Clock Pessimism Removal (CPR):    -0.150ns
  Clock Net Delay (Source):      1.333ns (routing 0.484ns, distribution 0.849ns)
  Clock Net Delay (Destination): 1.505ns (routing 0.537ns, distribution 0.968ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.333     3.018    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X85Y108        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_13/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y108        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.057 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_13/Q
                         net (fo=242, routed)         0.147     3.204    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/peripheral_aresetn[0]_repN_13_alias
    SLICE_X85Y113        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.505     2.894    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X85Y113        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/C
                         clock pessimism              0.150     3.043    
    SLICE_X85Y113        FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     3.023    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.023    
                         arrival time                           3.204    
  -------------------------------------------------------------------
                         slack                                  0.180    

Slack (MET) :             0.194ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_33/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.210ns  (logic 0.038ns (18.080%)  route 0.172ns (81.920%))
  Logic Levels:           0  
  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.781ns
    Source Clock Delay      (SCD):    2.936ns
    Clock Pessimism Removal (CPR):    -0.191ns
  Clock Net Delay (Source):      1.251ns (routing 0.484ns, distribution 0.767ns)
  Clock Net Delay (Destination): 1.392ns (routing 0.537ns, distribution 0.855ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.251     2.936    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X78Y120        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_33/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y120        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.974 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_33/Q
                         net (fo=130, routed)         0.172     3.146    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/peripheral_aresetn[0]_repN_33_alias
    SLICE_X74Y120        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.392     2.781    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X74Y120        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C
                         clock pessimism              0.191     2.972    
    SLICE_X74Y120        FDCE (Remov_AFF_SLICEL_C_CLR)
                                                     -0.020     2.952    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.952    
                         arrival time                           3.146    
  -------------------------------------------------------------------
                         slack                                  0.194    

Slack (MET) :             0.285ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_33/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.357ns  (logic 0.038ns (10.647%)  route 0.319ns (89.353%))
  Logic Levels:           0  
  Clock Path Skew:        0.092ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.801ns
    Source Clock Delay      (SCD):    2.936ns
    Clock Pessimism Removal (CPR):    -0.227ns
  Clock Net Delay (Source):      1.251ns (routing 0.484ns, distribution 0.767ns)
  Clock Net Delay (Destination): 1.412ns (routing 0.537ns, distribution 0.875ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.251     2.936    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X78Y120        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_33/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y120        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.974 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_33/Q
                         net (fo=130, routed)         0.319     3.293    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/peripheral_aresetn[0]_repN_33_alias
    SLICE_X75Y111        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.412     2.801    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X75Y111        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/C
                         clock pessimism              0.227     3.028    
    SLICE_X75Y111        FDCE (Remov_EFF_SLICEM_C_CLR)
                                                     -0.020     3.008    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.008    
                         arrival time                           3.293    
  -------------------------------------------------------------------
                         slack                                  0.285    

Slack (MET) :             0.579ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_13/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.621ns  (logic 0.039ns (6.278%)  route 0.582ns (93.722%))
  Logic Levels:           0  
  Clock Path Skew:        0.063ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.853ns
    Source Clock Delay      (SCD):    3.018ns
    Clock Pessimism Removal (CPR):    -0.227ns
  Clock Net Delay (Source):      1.333ns (routing 0.484ns, distribution 0.849ns)
  Clock Net Delay (Destination): 1.464ns (routing 0.537ns, distribution 0.927ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.333     3.018    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X85Y108        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_13/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y108        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.057 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_13/Q
                         net (fo=242, routed)         0.582     3.639    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/peripheral_aresetn[0]_repN_13_alias
    SLICE_X81Y120        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.464     2.853    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X81Y120        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/C
                         clock pessimism              0.227     3.080    
    SLICE_X81Y120        FDCE (Remov_AFF_SLICEL_C_CLR)
                                                     -0.020     3.060    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.060    
                         arrival time                           3.639    
  -------------------------------------------------------------------
                         slack                                  0.579    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  clk_out1_d_1_clk_core_0

Setup :            0  Failing Endpoints,  Worst Slack        1.308ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.098ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.308ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        3.500ns  (logic 0.079ns (2.257%)  route 3.421ns (97.743%))
  Logic Levels:           0  
  Clock Path Skew:        -0.064ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.960ns = ( 9.960 - 5.000 ) 
    Source Clock Delay      (SCD):    4.716ns
    Clock Pessimism Removal (CPR):    -0.308ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.202ns (routing 1.037ns, distribution 1.165ns)
  Clock Net Delay (Destination): 1.978ns (routing 0.940ns, distribution 1.038ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.202     4.716    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X74Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y222        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.795 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/Q
                         net (fo=201, routed)         3.421     8.216    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_14_alias
    SLICE_X74Y182        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.978     9.960    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X74Y182        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/C
                         clock pessimism             -0.308     9.652    
                         clock uncertainty           -0.062     9.589    
    SLICE_X74Y182        FDCE (Recov_HFF_SLICEL_C_CLR)
                                                     -0.066     9.523    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]
  -------------------------------------------------------------------
                         required time                          9.523    
                         arrival time                          -8.216    
  -------------------------------------------------------------------
                         slack                                  1.308    

Slack (MET) :             1.308ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        3.500ns  (logic 0.079ns (2.257%)  route 3.421ns (97.743%))
  Logic Levels:           0  
  Clock Path Skew:        -0.064ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.960ns = ( 9.960 - 5.000 ) 
    Source Clock Delay      (SCD):    4.716ns
    Clock Pessimism Removal (CPR):    -0.308ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.202ns (routing 1.037ns, distribution 1.165ns)
  Clock Net Delay (Destination): 1.978ns (routing 0.940ns, distribution 1.038ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.202     4.716    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X74Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y222        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.795 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/Q
                         net (fo=201, routed)         3.421     8.216    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_14_alias
    SLICE_X74Y182        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.978     9.960    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X74Y182        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/C
                         clock pessimism             -0.308     9.652    
                         clock uncertainty           -0.062     9.589    
    SLICE_X74Y182        FDCE (Recov_GFF_SLICEL_C_CLR)
                                                     -0.066     9.523    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]
  -------------------------------------------------------------------
                         required time                          9.523    
                         arrival time                          -8.216    
  -------------------------------------------------------------------
                         slack                                  1.308    

Slack (MET) :             1.308ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[2]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        3.500ns  (logic 0.079ns (2.257%)  route 3.421ns (97.743%))
  Logic Levels:           0  
  Clock Path Skew:        -0.064ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.960ns = ( 9.960 - 5.000 ) 
    Source Clock Delay      (SCD):    4.716ns
    Clock Pessimism Removal (CPR):    -0.308ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.202ns (routing 1.037ns, distribution 1.165ns)
  Clock Net Delay (Destination): 1.978ns (routing 0.940ns, distribution 1.038ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.202     4.716    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X74Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y222        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.795 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/Q
                         net (fo=201, routed)         3.421     8.216    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_14_alias
    SLICE_X74Y182        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.978     9.960    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X74Y182        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[2]/C
                         clock pessimism             -0.308     9.652    
                         clock uncertainty           -0.062     9.589    
    SLICE_X74Y182        FDCE (Recov_FFF_SLICEL_C_CLR)
                                                     -0.066     9.523    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[2]
  -------------------------------------------------------------------
                         required time                          9.523    
                         arrival time                          -8.216    
  -------------------------------------------------------------------
                         slack                                  1.308    

Slack (MET) :             1.994ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/clr_fifo_ack_reg/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.888ns  (logic 0.078ns (2.701%)  route 2.810ns (97.299%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.068ns = ( 10.068 - 5.000 ) 
    Source Clock Delay      (SCD):    4.758ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.244ns (routing 1.037ns, distribution 1.207ns)
  Clock Net Delay (Destination): 2.086ns (routing 0.940ns, distribution 1.146ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.244     4.758    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X72Y171        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y171        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     4.836 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/Q
                         net (fo=224, routed)         2.810     7.646    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/peripheral_aresetn[0]_repN_3_alias
    SLICE_X82Y128        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/clr_fifo_ack_reg/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.086    10.068    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/c_clk_i
    SLICE_X82Y128        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/clr_fifo_ack_reg/C
                         clock pessimism             -0.299     9.769    
                         clock uncertainty           -0.062     9.706    
    SLICE_X82Y128        FDCE (Recov_HFF_SLICEM_C_CLR)
                                                     -0.066     9.640    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/clr_fifo_ack_reg
  -------------------------------------------------------------------
                         required time                          9.640    
                         arrival time                          -7.646    
  -------------------------------------------------------------------
                         slack                                  1.994    

Slack (MET) :             1.994ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/clr_fifo_req_reg/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.888ns  (logic 0.078ns (2.701%)  route 2.810ns (97.299%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.068ns = ( 10.068 - 5.000 ) 
    Source Clock Delay      (SCD):    4.758ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.244ns (routing 1.037ns, distribution 1.207ns)
  Clock Net Delay (Destination): 2.086ns (routing 0.940ns, distribution 1.146ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.244     4.758    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X72Y171        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y171        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     4.836 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/Q
                         net (fo=224, routed)         2.810     7.646    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/peripheral_aresetn[0]_repN_3_alias
    SLICE_X82Y128        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/clr_fifo_req_reg/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.086    10.068    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/c_clk_i
    SLICE_X82Y128        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/clr_fifo_req_reg/C
                         clock pessimism             -0.299     9.769    
                         clock uncertainty           -0.062     9.706    
    SLICE_X82Y128        FDCE (Recov_EFF_SLICEM_C_CLR)
                                                     -0.066     9.640    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/clr_fifo_req_reg
  -------------------------------------------------------------------
                         required time                          9.640    
                         arrival time                          -7.646    
  -------------------------------------------------------------------
                         slack                                  1.994    

Slack (MET) :             1.994ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/clear_cdc_reg/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.888ns  (logic 0.078ns (2.701%)  route 2.810ns (97.299%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.068ns = ( 10.068 - 5.000 ) 
    Source Clock Delay      (SCD):    4.758ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.244ns (routing 1.037ns, distribution 1.207ns)
  Clock Net Delay (Destination): 2.086ns (routing 0.940ns, distribution 1.146ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.244     4.758    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X72Y171        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y171        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     4.836 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/Q
                         net (fo=224, routed)         2.810     7.646    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_3_alias
    SLICE_X82Y128        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/clear_cdc_reg/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.086    10.068    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X82Y128        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/clear_cdc_reg/C
                         clock pessimism             -0.299     9.769    
                         clock uncertainty           -0.062     9.706    
    SLICE_X82Y128        FDCE (Recov_HFF2_SLICEM_C_CLR)
                                                     -0.066     9.640    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/clear_cdc_reg
  -------------------------------------------------------------------
                         required time                          9.640    
                         arrival time                          -7.646    
  -------------------------------------------------------------------
                         slack                                  1.994    

Slack (MET) :             1.994ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/clear_r_reg/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.888ns  (logic 0.078ns (2.701%)  route 2.810ns (97.299%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.068ns = ( 10.068 - 5.000 ) 
    Source Clock Delay      (SCD):    4.758ns
    Clock Pessimism Removal (CPR):    -0.299ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.244ns (routing 1.037ns, distribution 1.207ns)
  Clock Net Delay (Destination): 2.086ns (routing 0.940ns, distribution 1.146ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.244     4.758    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X72Y171        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y171        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     4.836 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/Q
                         net (fo=224, routed)         2.810     7.646    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_3_alias
    SLICE_X82Y128        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/clear_r_reg/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.086    10.068    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X82Y128        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/clear_r_reg/C
                         clock pessimism             -0.299     9.769    
                         clock uncertainty           -0.062     9.706    
    SLICE_X82Y128        FDCE (Recov_EFF2_SLICEM_C_CLR)
                                                     -0.066     9.640    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/clear_r_reg
  -------------------------------------------------------------------
                         required time                          9.640    
                         arrival time                          -7.646    
  -------------------------------------------------------------------
                         slack                                  1.994    

Slack (MET) :             2.227ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.588ns  (logic 0.079ns (3.053%)  route 2.509ns (96.947%))
  Logic Levels:           0  
  Clock Path Skew:        -0.057ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.968ns = ( 9.968 - 5.000 ) 
    Source Clock Delay      (SCD):    4.716ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.202ns (routing 1.037ns, distribution 1.165ns)
  Clock Net Delay (Destination): 1.986ns (routing 0.940ns, distribution 1.046ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.202     4.716    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X74Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y222        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.795 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/Q
                         net (fo=201, routed)         2.509     7.304    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_14_alias
    SLICE_X73Y182        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.986     9.968    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X73Y182        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
                         clock pessimism             -0.309     9.659    
                         clock uncertainty           -0.062     9.597    
    SLICE_X73Y182        FDCE (Recov_DFF2_SLICEL_C_CLR)
                                                     -0.066     9.531    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]
  -------------------------------------------------------------------
                         required time                          9.531    
                         arrival time                          -7.304    
  -------------------------------------------------------------------
                         slack                                  2.227    

Slack (MET) :             2.227ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.588ns  (logic 0.079ns (3.053%)  route 2.509ns (96.947%))
  Logic Levels:           0  
  Clock Path Skew:        -0.057ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.968ns = ( 9.968 - 5.000 ) 
    Source Clock Delay      (SCD):    4.716ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.202ns (routing 1.037ns, distribution 1.165ns)
  Clock Net Delay (Destination): 1.986ns (routing 0.940ns, distribution 1.046ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.202     4.716    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X74Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y222        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.795 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/Q
                         net (fo=201, routed)         2.509     7.304    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_14_alias
    SLICE_X73Y182        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.986     9.968    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X73Y182        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/C
                         clock pessimism             -0.309     9.659    
                         clock uncertainty           -0.062     9.597    
    SLICE_X73Y182        FDCE (Recov_DFF_SLICEL_C_CLR)
                                                     -0.066     9.531    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]
  -------------------------------------------------------------------
                         required time                          9.531    
                         arrival time                          -7.304    
  -------------------------------------------------------------------
                         slack                                  2.227    

Slack (MET) :             2.227ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[3]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.588ns  (logic 0.079ns (3.053%)  route 2.509ns (96.947%))
  Logic Levels:           0  
  Clock Path Skew:        -0.057ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.968ns = ( 9.968 - 5.000 ) 
    Source Clock Delay      (SCD):    4.716ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.202ns (routing 1.037ns, distribution 1.165ns)
  Clock Net Delay (Destination): 1.986ns (routing 0.940ns, distribution 1.046ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.202     4.716    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X74Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y222        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.795 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/Q
                         net (fo=201, routed)         2.509     7.304    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_14_alias
    SLICE_X73Y182        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[3]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.986     9.968    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X73Y182        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[3]/C
                         clock pessimism             -0.309     9.659    
                         clock uncertainty           -0.062     9.597    
    SLICE_X73Y182        FDCE (Recov_CFF_SLICEL_C_CLR)
                                                     -0.066     9.531    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[3]
  -------------------------------------------------------------------
                         required time                          9.531    
                         arrival time                          -7.304    
  -------------------------------------------------------------------
                         slack                                  2.227    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.098ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_cfg_dt_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.134ns  (logic 0.039ns (29.162%)  route 0.095ns (70.838%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.799ns
    Source Clock Delay      (SCD):    2.968ns
    Clock Pessimism Removal (CPR):    -0.225ns
  Clock Net Delay (Source):      1.282ns (routing 0.571ns, distribution 0.711ns)
  Clock Net Delay (Destination): 1.451ns (routing 0.639ns, distribution 0.812ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.282     2.968    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X58Y156        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y156        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     3.007 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/Q
                         net (fo=157, routed)         0.095     3.101    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/peripheral_aresetn[0]_repN_10_alias
    SLICE_X55Y156        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_cfg_dt_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.451     2.799    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X55Y156        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_cfg_dt_reg[1]/C
                         clock pessimism              0.225     3.024    
    SLICE_X55Y156        FDCE (Remov_EFF2_SLICEL_C_CLR)
                                                     -0.020     3.004    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_cfg_dt_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.004    
                         arrival time                           3.101    
  -------------------------------------------------------------------
                         slack                                  0.098    

Slack (MET) :             0.104ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/LFSR_YES.lfsr/reg_lfsr_reg[19]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.141ns  (logic 0.039ns (27.712%)  route 0.102ns (72.288%))
  Logic Levels:           0  
  Clock Path Skew:        0.057ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.800ns
    Source Clock Delay      (SCD):    2.968ns
    Clock Pessimism Removal (CPR):    -0.225ns
  Clock Net Delay (Source):      1.282ns (routing 0.571ns, distribution 0.711ns)
  Clock Net Delay (Destination): 1.452ns (routing 0.639ns, distribution 0.813ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.282     2.968    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X58Y156        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y156        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     3.007 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/Q
                         net (fo=157, routed)         0.102     3.108    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/LFSR_YES.lfsr/peripheral_aresetn[0]_repN_10_alias
    SLICE_X54Y156        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/LFSR_YES.lfsr/reg_lfsr_reg[19]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.452     2.800    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/LFSR_YES.lfsr/c_clk_i
    SLICE_X54Y156        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/LFSR_YES.lfsr/reg_lfsr_reg[19]/C
                         clock pessimism              0.225     3.025    
    SLICE_X54Y156        FDCE (Remov_BFF_SLICEM_C_CLR)
                                                     -0.020     3.005    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/LFSR_YES.lfsr/reg_lfsr_reg[19]
  -------------------------------------------------------------------
                         required time                         -3.005    
                         arrival time                           3.108    
  -------------------------------------------------------------------
                         slack                                  0.104    

Slack (MET) :             0.104ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/LFSR_YES.lfsr/reg_lfsr_reg[20]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.141ns  (logic 0.039ns (27.712%)  route 0.102ns (72.288%))
  Logic Levels:           0  
  Clock Path Skew:        0.057ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.800ns
    Source Clock Delay      (SCD):    2.968ns
    Clock Pessimism Removal (CPR):    -0.225ns
  Clock Net Delay (Source):      1.282ns (routing 0.571ns, distribution 0.711ns)
  Clock Net Delay (Destination): 1.452ns (routing 0.639ns, distribution 0.813ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.282     2.968    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X58Y156        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y156        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     3.007 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/Q
                         net (fo=157, routed)         0.102     3.108    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/LFSR_YES.lfsr/peripheral_aresetn[0]_repN_10_alias
    SLICE_X54Y156        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/LFSR_YES.lfsr/reg_lfsr_reg[20]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.452     2.800    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/LFSR_YES.lfsr/c_clk_i
    SLICE_X54Y156        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/LFSR_YES.lfsr/reg_lfsr_reg[20]/C
                         clock pessimism              0.225     3.025    
    SLICE_X54Y156        FDCE (Remov_BFF2_SLICEM_C_CLR)
                                                     -0.020     3.005    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/LFSR_YES.lfsr/reg_lfsr_reg[20]
  -------------------------------------------------------------------
                         required time                         -3.005    
                         arrival time                           3.108    
  -------------------------------------------------------------------
                         slack                                  0.104    

Slack (MET) :             0.125ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/reg_A_reg[0][4]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.154ns  (logic 0.041ns (26.551%)  route 0.113ns (73.449%))
  Logic Levels:           0  
  Clock Path Skew:        0.050ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.747ns
    Source Clock Delay      (SCD):    2.927ns
    Clock Pessimism Removal (CPR):    -0.229ns
  Clock Net Delay (Source):      1.241ns (routing 0.571ns, distribution 0.670ns)
  Clock Net Delay (Destination): 1.399ns (routing 0.639ns, distribution 0.760ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.241     2.927    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y170        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y170        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     2.968 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/Q
                         net (fo=212, routed)         0.113     3.081    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/peripheral_aresetn[0]_repN_5_alias
    SLICE_X66Y170        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/reg_A_reg[0][4]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.399     2.747    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_clk_i
    SLICE_X66Y170        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/reg_A_reg[0][4]/C
                         clock pessimism              0.229     2.976    
    SLICE_X66Y170        FDCE (Remov_BFF_SLICEM_C_CLR)
                                                     -0.020     2.956    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/reg_A_reg[0][4]
  -------------------------------------------------------------------
                         required time                         -2.956    
                         arrival time                           3.081    
  -------------------------------------------------------------------
                         slack                                  0.125    

Slack (MET) :             0.125ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/reg_A_reg[1][4]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.154ns  (logic 0.041ns (26.551%)  route 0.113ns (73.449%))
  Logic Levels:           0  
  Clock Path Skew:        0.050ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.747ns
    Source Clock Delay      (SCD):    2.927ns
    Clock Pessimism Removal (CPR):    -0.229ns
  Clock Net Delay (Source):      1.241ns (routing 0.571ns, distribution 0.670ns)
  Clock Net Delay (Destination): 1.399ns (routing 0.639ns, distribution 0.760ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.241     2.927    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y170        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y170        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     2.968 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/Q
                         net (fo=212, routed)         0.113     3.081    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/peripheral_aresetn[0]_repN_5_alias
    SLICE_X66Y170        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/reg_A_reg[1][4]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.399     2.747    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_clk_i
    SLICE_X66Y170        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/reg_A_reg[1][4]/C
                         clock pessimism              0.229     2.976    
    SLICE_X66Y170        FDCE (Remov_AFF_SLICEM_C_CLR)
                                                     -0.020     2.956    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/reg_A_reg[1][4]
  -------------------------------------------------------------------
                         required time                         -2.956    
                         arrival time                           3.081    
  -------------------------------------------------------------------
                         slack                                  0.125    

Slack (MET) :             0.130ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.125ns  (logic 0.038ns (30.296%)  route 0.087ns (69.704%))
  Logic Levels:           0  
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.748ns
    Source Clock Delay      (SCD):    2.927ns
    Clock Pessimism Removal (CPR):    -0.194ns
  Clock Net Delay (Source):      1.241ns (routing 0.571ns, distribution 0.670ns)
  Clock Net Delay (Destination): 1.400ns (routing 0.639ns, distribution 0.761ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.241     2.927    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X70Y161        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y161        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.965 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/Q
                         net (fo=217, routed)         0.087     3.052    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_1_alias
    SLICE_X71Y161        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.400     2.748    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X71Y161        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
                         clock pessimism              0.194     2.942    
    SLICE_X71Y161        FDCE (Remov_HFF_SLICEL_C_CLR)
                                                     -0.020     2.922    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.922    
                         arrival time                           3.052    
  -------------------------------------------------------------------
                         slack                                  0.130    

Slack (MET) :             0.130ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/clr_fifo_req_reg/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.125ns  (logic 0.038ns (30.296%)  route 0.087ns (69.704%))
  Logic Levels:           0  
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.748ns
    Source Clock Delay      (SCD):    2.927ns
    Clock Pessimism Removal (CPR):    -0.194ns
  Clock Net Delay (Source):      1.241ns (routing 0.571ns, distribution 0.670ns)
  Clock Net Delay (Destination): 1.400ns (routing 0.639ns, distribution 0.761ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.241     2.927    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X70Y161        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y161        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.965 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/Q
                         net (fo=217, routed)         0.087     3.052    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/peripheral_aresetn[0]_repN_1_alias
    SLICE_X71Y161        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/clr_fifo_req_reg/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.400     2.748    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/c_clk_i
    SLICE_X71Y161        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/clr_fifo_req_reg/C
                         clock pessimism              0.194     2.942    
    SLICE_X71Y161        FDCE (Remov_HFF2_SLICEL_C_CLR)
                                                     -0.020     2.922    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/clr_fifo_req_reg
  -------------------------------------------------------------------
                         required time                         -2.922    
                         arrival time                           3.052    
  -------------------------------------------------------------------
                         slack                                  0.130    

Slack (MET) :             0.134ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/clr_fifo_ack_reg/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.125ns  (logic 0.038ns (30.296%)  route 0.087ns (69.704%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.744ns
    Source Clock Delay      (SCD):    2.927ns
    Clock Pessimism Removal (CPR):    -0.194ns
  Clock Net Delay (Source):      1.241ns (routing 0.571ns, distribution 0.670ns)
  Clock Net Delay (Destination): 1.396ns (routing 0.639ns, distribution 0.757ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.241     2.927    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X70Y161        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y161        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.965 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/Q
                         net (fo=217, routed)         0.087     3.052    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/peripheral_aresetn[0]_repN_1_alias
    SLICE_X71Y161        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/clr_fifo_ack_reg/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.396     2.744    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/c_clk_i
    SLICE_X71Y161        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/clr_fifo_ack_reg/C
                         clock pessimism              0.194     2.938    
    SLICE_X71Y161        FDCE (Remov_CFF_SLICEL_C_CLR)
                                                     -0.020     2.918    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/clr_fifo_ack_reg
  -------------------------------------------------------------------
                         required time                         -2.918    
                         arrival time                           3.052    
  -------------------------------------------------------------------
                         slack                                  0.134    

Slack (MET) :             0.134ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/clear_cdc_reg/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.125ns  (logic 0.038ns (30.296%)  route 0.087ns (69.704%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.744ns
    Source Clock Delay      (SCD):    2.927ns
    Clock Pessimism Removal (CPR):    -0.194ns
  Clock Net Delay (Source):      1.241ns (routing 0.571ns, distribution 0.670ns)
  Clock Net Delay (Destination): 1.396ns (routing 0.639ns, distribution 0.757ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.241     2.927    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X70Y161        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y161        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.965 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/Q
                         net (fo=217, routed)         0.087     3.052    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_1_alias
    SLICE_X71Y161        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/clear_cdc_reg/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.396     2.744    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X71Y161        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/clear_cdc_reg/C
                         clock pessimism              0.194     2.938    
    SLICE_X71Y161        FDCE (Remov_DFF2_SLICEL_C_CLR)
                                                     -0.020     2.918    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/clear_cdc_reg
  -------------------------------------------------------------------
                         required time                         -2.918    
                         arrival time                           3.052    
  -------------------------------------------------------------------
                         slack                                  0.134    

Slack (MET) :             0.134ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/clear_r_reg/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.125ns  (logic 0.038ns (30.296%)  route 0.087ns (69.704%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.744ns
    Source Clock Delay      (SCD):    2.927ns
    Clock Pessimism Removal (CPR):    -0.194ns
  Clock Net Delay (Source):      1.241ns (routing 0.571ns, distribution 0.670ns)
  Clock Net Delay (Destination): 1.396ns (routing 0.639ns, distribution 0.757ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.241     2.927    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X70Y161        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y161        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.965 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/Q
                         net (fo=217, routed)         0.087     3.052    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_1_alias
    SLICE_X71Y161        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/clear_r_reg/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.396     2.744    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X71Y161        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/clear_r_reg/C
                         clock pessimism              0.194     2.938    
    SLICE_X71Y161        FDCE (Remov_AFF2_SLICEL_C_CLR)
                                                     -0.020     2.918    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/clear_r_reg
  -------------------------------------------------------------------
                         required time                         -2.918    
                         arrival time                           3.052    
  -------------------------------------------------------------------
                         slack                                  0.134    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Setup :            0  Failing Endpoints,  Worst Slack        6.316ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.151ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             6.316ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][25]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        3.126ns  (logic 0.105ns (3.359%)  route 3.021ns (96.641%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.362ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.002ns = ( 12.002 - 10.000 ) 
    Source Clock Delay      (SCD):    2.471ns
    Clock Pessimism Removal (CPR):    0.107ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.245ns (routing 0.662ns, distribution 1.583ns)
  Clock Net Delay (Destination): 1.820ns (routing 0.599ns, distribution 1.221ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.245     2.471    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X76Y335        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y335        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.548 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.184     3.732    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y146        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.760 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14833, routed)       1.837     5.597    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X42Y159        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][25]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.820    12.002    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X42Y159        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][25]/C
                         clock pessimism              0.107    12.109    
                         clock uncertainty           -0.130    11.979    
    SLICE_X42Y159        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    11.913    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][25]
  -------------------------------------------------------------------
                         required time                         11.913    
                         arrival time                          -5.597    
  -------------------------------------------------------------------
                         slack                                  6.316    

Slack (MET) :             6.316ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][29]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        3.126ns  (logic 0.105ns (3.359%)  route 3.021ns (96.641%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.362ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.002ns = ( 12.002 - 10.000 ) 
    Source Clock Delay      (SCD):    2.471ns
    Clock Pessimism Removal (CPR):    0.107ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.245ns (routing 0.662ns, distribution 1.583ns)
  Clock Net Delay (Destination): 1.820ns (routing 0.599ns, distribution 1.221ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.245     2.471    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X76Y335        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y335        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.548 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.184     3.732    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y146        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.760 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14833, routed)       1.837     5.597    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X42Y159        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][29]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.820    12.002    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X42Y159        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][29]/C
                         clock pessimism              0.107    12.109    
                         clock uncertainty           -0.130    11.979    
    SLICE_X42Y159        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066    11.913    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][29]
  -------------------------------------------------------------------
                         required time                         11.913    
                         arrival time                          -5.597    
  -------------------------------------------------------------------
                         slack                                  6.316    

Slack (MET) :             6.316ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][28]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        3.127ns  (logic 0.105ns (3.358%)  route 3.022ns (96.642%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.361ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.003ns = ( 12.003 - 10.000 ) 
    Source Clock Delay      (SCD):    2.471ns
    Clock Pessimism Removal (CPR):    0.107ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.245ns (routing 0.662ns, distribution 1.583ns)
  Clock Net Delay (Destination): 1.821ns (routing 0.599ns, distribution 1.222ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.245     2.471    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X76Y335        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y335        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.548 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.184     3.732    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y146        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.760 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14833, routed)       1.838     5.598    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X42Y160        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][28]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.821    12.003    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X42Y160        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][28]/C
                         clock pessimism              0.107    12.110    
                         clock uncertainty           -0.130    11.980    
    SLICE_X42Y160        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    11.914    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][28]
  -------------------------------------------------------------------
                         required time                         11.914    
                         arrival time                          -5.598    
  -------------------------------------------------------------------
                         slack                                  6.316    

Slack (MET) :             6.316ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][30]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        3.127ns  (logic 0.105ns (3.358%)  route 3.022ns (96.642%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.361ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.003ns = ( 12.003 - 10.000 ) 
    Source Clock Delay      (SCD):    2.471ns
    Clock Pessimism Removal (CPR):    0.107ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.245ns (routing 0.662ns, distribution 1.583ns)
  Clock Net Delay (Destination): 1.821ns (routing 0.599ns, distribution 1.222ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.245     2.471    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X76Y335        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y335        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.548 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.184     3.732    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y146        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.760 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14833, routed)       1.838     5.598    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X42Y160        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][30]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.821    12.003    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X42Y160        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][30]/C
                         clock pessimism              0.107    12.110    
                         clock uncertainty           -0.130    11.980    
    SLICE_X42Y160        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066    11.914    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][30]
  -------------------------------------------------------------------
                         required time                         11.914    
                         arrival time                          -5.598    
  -------------------------------------------------------------------
                         slack                                  6.316    

Slack (MET) :             6.325ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][30]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        3.109ns  (logic 0.105ns (3.377%)  route 3.004ns (96.623%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.370ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.994ns = ( 11.994 - 10.000 ) 
    Source Clock Delay      (SCD):    2.471ns
    Clock Pessimism Removal (CPR):    0.107ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.245ns (routing 0.662ns, distribution 1.583ns)
  Clock Net Delay (Destination): 1.812ns (routing 0.599ns, distribution 1.213ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.245     2.471    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X76Y335        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y335        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.548 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.184     3.732    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y146        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.760 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14833, routed)       1.820     5.580    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X41Y160        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][30]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.812    11.994    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X41Y160        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][30]/C
                         clock pessimism              0.107    12.101    
                         clock uncertainty           -0.130    11.971    
    SLICE_X41Y160        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    11.905    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][30]
  -------------------------------------------------------------------
                         required time                         11.905    
                         arrival time                          -5.580    
  -------------------------------------------------------------------
                         slack                                  6.325    

Slack (MET) :             6.328ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][26]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        3.109ns  (logic 0.105ns (3.377%)  route 3.004ns (96.623%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.367ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.997ns = ( 11.997 - 10.000 ) 
    Source Clock Delay      (SCD):    2.471ns
    Clock Pessimism Removal (CPR):    0.107ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.245ns (routing 0.662ns, distribution 1.583ns)
  Clock Net Delay (Destination): 1.815ns (routing 0.599ns, distribution 1.216ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.245     2.471    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X76Y335        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y335        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.548 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.184     3.732    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y146        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.760 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14833, routed)       1.820     5.580    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X43Y158        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][26]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.815    11.997    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X43Y158        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][26]/C
                         clock pessimism              0.107    12.104    
                         clock uncertainty           -0.130    11.974    
    SLICE_X43Y158        FDCE (Recov_DFF_SLICEL_C_CLR)
                                                     -0.066    11.908    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][26]
  -------------------------------------------------------------------
                         required time                         11.908    
                         arrival time                          -5.580    
  -------------------------------------------------------------------
                         slack                                  6.328    

Slack (MET) :             6.328ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][27]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        3.109ns  (logic 0.105ns (3.377%)  route 3.004ns (96.623%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.367ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.997ns = ( 11.997 - 10.000 ) 
    Source Clock Delay      (SCD):    2.471ns
    Clock Pessimism Removal (CPR):    0.107ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.245ns (routing 0.662ns, distribution 1.583ns)
  Clock Net Delay (Destination): 1.815ns (routing 0.599ns, distribution 1.216ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.245     2.471    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X76Y335        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y335        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.548 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.184     3.732    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y146        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.760 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14833, routed)       1.820     5.580    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X43Y158        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][27]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.815    11.997    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X43Y158        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][27]/C
                         clock pessimism              0.107    12.104    
                         clock uncertainty           -0.130    11.974    
    SLICE_X43Y158        FDCE (Recov_CFF_SLICEL_C_CLR)
                                                     -0.066    11.908    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][27]
  -------------------------------------------------------------------
                         required time                         11.908    
                         arrival time                          -5.580    
  -------------------------------------------------------------------
                         slack                                  6.328    

Slack (MET) :             6.328ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][31]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        3.109ns  (logic 0.105ns (3.377%)  route 3.004ns (96.623%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.367ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.997ns = ( 11.997 - 10.000 ) 
    Source Clock Delay      (SCD):    2.471ns
    Clock Pessimism Removal (CPR):    0.107ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.245ns (routing 0.662ns, distribution 1.583ns)
  Clock Net Delay (Destination): 1.815ns (routing 0.599ns, distribution 1.216ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.245     2.471    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X76Y335        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y335        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.548 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.184     3.732    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y146        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.760 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14833, routed)       1.820     5.580    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X43Y158        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][31]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.815    11.997    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X43Y158        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][31]/C
                         clock pessimism              0.107    12.104    
                         clock uncertainty           -0.130    11.974    
    SLICE_X43Y158        FDCE (Recov_BFF_SLICEL_C_CLR)
                                                     -0.066    11.908    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][31]
  -------------------------------------------------------------------
                         required time                         11.908    
                         arrival time                          -5.580    
  -------------------------------------------------------------------
                         slack                                  6.328    

Slack (MET) :             6.335ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][27]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        3.097ns  (logic 0.105ns (3.390%)  route 2.992ns (96.610%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.372ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.992ns = ( 11.992 - 10.000 ) 
    Source Clock Delay      (SCD):    2.471ns
    Clock Pessimism Removal (CPR):    0.107ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.245ns (routing 0.662ns, distribution 1.583ns)
  Clock Net Delay (Destination): 1.810ns (routing 0.599ns, distribution 1.211ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.245     2.471    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X76Y335        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y335        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.548 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.184     3.732    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y146        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.760 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14833, routed)       1.808     5.568    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X42Y163        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][27]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.810    11.992    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X42Y163        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][27]/C
                         clock pessimism              0.107    12.099    
                         clock uncertainty           -0.130    11.969    
    SLICE_X42Y163        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    11.903    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][27]
  -------------------------------------------------------------------
                         required time                         11.903    
                         arrival time                          -5.568    
  -------------------------------------------------------------------
                         slack                                  6.335    

Slack (MET) :             6.335ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][28]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        3.097ns  (logic 0.105ns (3.390%)  route 2.992ns (96.610%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.372ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.992ns = ( 11.992 - 10.000 ) 
    Source Clock Delay      (SCD):    2.471ns
    Clock Pessimism Removal (CPR):    0.107ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.245ns (routing 0.662ns, distribution 1.583ns)
  Clock Net Delay (Destination): 1.810ns (routing 0.599ns, distribution 1.211ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.245     2.471    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X76Y335        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y335        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.548 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.184     3.732    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y146        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.760 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14833, routed)       1.808     5.568    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X42Y163        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][28]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.810    11.992    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X42Y163        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][28]/C
                         clock pessimism              0.107    12.099    
                         clock uncertainty           -0.130    11.969    
    SLICE_X42Y163        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066    11.903    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][28]
  -------------------------------------------------------------------
                         required time                         11.903    
                         arrival time                          -5.568    
  -------------------------------------------------------------------
                         slack                                  6.335    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.151ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.185ns  (logic 0.061ns (33.022%)  route 0.124ns (66.978%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.053ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.472ns
    Source Clock Delay      (SCD):    1.284ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      1.164ns (routing 0.359ns, distribution 0.805ns)
  Clock Net Delay (Destination): 1.325ns (routing 0.405ns, distribution 0.920ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.164     1.284    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X59Y23         FDRE                                         r  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y23         FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.323 f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.026     1.348    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X59Y23         LUT3 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.022     1.370 f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.098     1.468    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/AR[0]
    SLICE_X57Y23         FDCE                                         f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.325     1.472    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/clk
    SLICE_X57Y23         FDCE                                         r  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg/C
                         clock pessimism             -0.135     1.337    
    SLICE_X57Y23         FDCE (Remov_HFF2_SLICEL_C_CLR)
                                                     -0.020     1.317    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg
  -------------------------------------------------------------------
                         required time                         -1.317    
                         arrival time                           1.468    
  -------------------------------------------------------------------
                         slack                                  0.151    

Slack (MET) :             0.151ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.185ns  (logic 0.061ns (33.022%)  route 0.124ns (66.978%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.053ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.472ns
    Source Clock Delay      (SCD):    1.284ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      1.164ns (routing 0.359ns, distribution 0.805ns)
  Clock Net Delay (Destination): 1.325ns (routing 0.405ns, distribution 0.920ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.164     1.284    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X59Y23         FDRE                                         r  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y23         FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.323 f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.026     1.348    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X59Y23         LUT3 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.022     1.370 f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.098     1.468    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X57Y23         FDCE                                         f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.325     1.472    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X57Y23         FDCE                                         r  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]/C
                         clock pessimism             -0.135     1.337    
    SLICE_X57Y23         FDCE (Remov_HFF_SLICEL_C_CLR)
                                                     -0.020     1.317    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.317    
                         arrival time                           1.468    
  -------------------------------------------------------------------
                         slack                                  0.151    

Slack (MET) :             0.151ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[3]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.185ns  (logic 0.061ns (33.022%)  route 0.124ns (66.978%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.053ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.472ns
    Source Clock Delay      (SCD):    1.284ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      1.164ns (routing 0.359ns, distribution 0.805ns)
  Clock Net Delay (Destination): 1.325ns (routing 0.405ns, distribution 0.920ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.164     1.284    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X59Y23         FDRE                                         r  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y23         FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.323 f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.026     1.348    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X59Y23         LUT3 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.022     1.370 f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.098     1.468    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X57Y23         FDCE                                         f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.325     1.472    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X57Y23         FDCE                                         r  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[3]/C
                         clock pessimism             -0.135     1.337    
    SLICE_X57Y23         FDCE (Remov_GFF_SLICEL_C_CLR)
                                                     -0.020     1.317    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.317    
                         arrival time                           1.468    
  -------------------------------------------------------------------
                         slack                                  0.151    

Slack (MET) :             0.151ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[4]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.185ns  (logic 0.061ns (33.022%)  route 0.124ns (66.978%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.053ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.472ns
    Source Clock Delay      (SCD):    1.284ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      1.164ns (routing 0.359ns, distribution 0.805ns)
  Clock Net Delay (Destination): 1.325ns (routing 0.405ns, distribution 0.920ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.164     1.284    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X59Y23         FDRE                                         r  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y23         FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.323 f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.026     1.348    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X59Y23         LUT3 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.022     1.370 f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.098     1.468    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X57Y23         FDCE                                         f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.325     1.472    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X57Y23         FDCE                                         r  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[4]/C
                         clock pessimism             -0.135     1.337    
    SLICE_X57Y23         FDCE (Remov_FFF_SLICEL_C_CLR)
                                                     -0.020     1.317    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.317    
                         arrival time                           1.468    
  -------------------------------------------------------------------
                         slack                                  0.151    

Slack (MET) :             0.155ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.185ns  (logic 0.061ns (33.022%)  route 0.124ns (66.978%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.049ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.468ns
    Source Clock Delay      (SCD):    1.284ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      1.164ns (routing 0.359ns, distribution 0.805ns)
  Clock Net Delay (Destination): 1.321ns (routing 0.405ns, distribution 0.916ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.164     1.284    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X59Y23         FDRE                                         r  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y23         FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.323 f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.026     1.348    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X59Y23         LUT3 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.022     1.370 f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.098     1.468    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X57Y23         FDCE                                         f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.321     1.468    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X57Y23         FDCE                                         r  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
                         clock pessimism             -0.135     1.333    
    SLICE_X57Y23         FDCE (Remov_AFF_SLICEL_C_CLR)
                                                     -0.020     1.313    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.313    
                         arrival time                           1.468    
  -------------------------------------------------------------------
                         slack                                  0.155    

Slack (MET) :             0.155ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.185ns  (logic 0.061ns (33.022%)  route 0.124ns (66.978%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.049ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.468ns
    Source Clock Delay      (SCD):    1.284ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      1.164ns (routing 0.359ns, distribution 0.805ns)
  Clock Net Delay (Destination): 1.321ns (routing 0.405ns, distribution 0.916ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.164     1.284    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X59Y23         FDRE                                         r  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y23         FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.323 f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.026     1.348    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X59Y23         LUT3 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.022     1.370 f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.098     1.468    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X57Y23         FDCE                                         f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.321     1.468    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X57Y23         FDCE                                         r  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]/C
                         clock pessimism             -0.135     1.333    
    SLICE_X57Y23         FDCE (Remov_CFF2_SLICEL_C_CLR)
                                                     -0.020     1.313    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.313    
                         arrival time                           1.468    
  -------------------------------------------------------------------
                         slack                                  0.155    

Slack (MET) :             0.155ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.185ns  (logic 0.061ns (33.022%)  route 0.124ns (66.978%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.049ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.468ns
    Source Clock Delay      (SCD):    1.284ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      1.164ns (routing 0.359ns, distribution 0.805ns)
  Clock Net Delay (Destination): 1.321ns (routing 0.405ns, distribution 0.916ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.164     1.284    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X59Y23         FDRE                                         r  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y23         FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.323 f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.026     1.348    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X59Y23         LUT3 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.022     1.370 f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.098     1.468    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X57Y23         FDCE                                         f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.321     1.468    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X57Y23         FDCE                                         r  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/C
                         clock pessimism             -0.135     1.333    
    SLICE_X57Y23         FDCE (Remov_DFF_SLICEL_C_CLR)
                                                     -0.020     1.313    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.313    
                         arrival time                           1.468    
  -------------------------------------------------------------------
                         slack                                  0.155    

Slack (MET) :             0.155ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[4]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.185ns  (logic 0.061ns (33.022%)  route 0.124ns (66.978%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.049ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.468ns
    Source Clock Delay      (SCD):    1.284ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      1.164ns (routing 0.359ns, distribution 0.805ns)
  Clock Net Delay (Destination): 1.321ns (routing 0.405ns, distribution 0.916ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.164     1.284    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X59Y23         FDRE                                         r  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y23         FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.323 f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.026     1.348    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X59Y23         LUT3 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.022     1.370 f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.098     1.468    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X57Y23         FDCE                                         f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.321     1.468    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X57Y23         FDCE                                         r  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[4]/C
                         clock pessimism             -0.135     1.333    
    SLICE_X57Y23         FDCE (Remov_DFF2_SLICEL_C_CLR)
                                                     -0.020     1.313    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.313    
                         arrival time                           1.468    
  -------------------------------------------------------------------
                         slack                                  0.155    

Slack (MET) :             0.176ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.216ns  (logic 0.053ns (24.565%)  route 0.163ns (75.435%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.461ns
    Source Clock Delay      (SCD):    1.266ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      1.146ns (routing 0.359ns, distribution 0.787ns)
  Clock Net Delay (Destination): 1.314ns (routing 0.405ns, distribution 0.909ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.146     1.266    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X41Y49         FDRE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y49         FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.305 f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.056     1.360    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X40Y49         LUT3 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.014     1.374 f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.107     1.481    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    SLICE_X42Y49         FDPE                                         f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.314     1.461    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
    SLICE_X42Y49         FDPE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/C
                         clock pessimism             -0.135     1.326    
    SLICE_X42Y49         FDPE (Remov_DFF2_SLICEM_C_PRE)
                                                     -0.020     1.306    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg
  -------------------------------------------------------------------
                         required time                         -1.306    
                         arrival time                           1.481    
  -------------------------------------------------------------------
                         slack                                  0.176    

Slack (MET) :             0.176ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.216ns  (logic 0.053ns (24.565%)  route 0.163ns (75.435%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.461ns
    Source Clock Delay      (SCD):    1.266ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      1.146ns (routing 0.359ns, distribution 0.787ns)
  Clock Net Delay (Destination): 1.314ns (routing 0.405ns, distribution 0.909ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.146     1.266    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X41Y49         FDRE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y49         FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.305 f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.056     1.360    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X40Y49         LUT3 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.014     1.374 f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.107     1.481    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    SLICE_X42Y49         FDCE                                         f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.314     1.461    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
    SLICE_X42Y49         FDCE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/C
                         clock pessimism             -0.135     1.326    
    SLICE_X42Y49         FDCE (Remov_CFF_SLICEM_C_CLR)
                                                     -0.020     1.306    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.306    
                         arrival time                           1.481    
  -------------------------------------------------------------------
                         slack                                  0.176    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Setup :            0  Failing Endpoints,  Worst Slack       46.379ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.097ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             46.379ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.406ns  (logic 0.237ns (6.959%)  route 3.169ns (93.041%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.113ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.456ns = ( 55.456 - 50.000 ) 
    Source Clock Delay      (SCD):    10.823ns
    Clock Pessimism Removal (CPR):    5.254ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.888ns (routing 1.680ns, distribution 1.208ns)
  Clock Net Delay (Destination): 2.620ns (routing 1.525ns, distribution 1.095ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.888    10.823    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y98        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y98        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079    10.902 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/Q
                         net (fo=1, routed)           0.482    11.384    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[3]
    SLICE_X108Y98        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.090    11.474 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.159    11.633    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X109Y98        LUT4 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.068    11.701 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.528    14.229    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X104Y287       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347    52.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.620    55.456    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X104Y287       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/C
                         clock pessimism              5.254    60.710    
                         clock uncertainty           -0.035    60.674    
    SLICE_X104Y287       FDCE (Recov_AFF_SLICEM_C_CLR)
                                                     -0.066    60.608    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]
  -------------------------------------------------------------------
                         required time                         60.608    
                         arrival time                         -14.229    
  -------------------------------------------------------------------
                         slack                                 46.379    

Slack (MET) :             46.379ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.406ns  (logic 0.237ns (6.959%)  route 3.169ns (93.041%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.113ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.456ns = ( 55.456 - 50.000 ) 
    Source Clock Delay      (SCD):    10.823ns
    Clock Pessimism Removal (CPR):    5.254ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.888ns (routing 1.680ns, distribution 1.208ns)
  Clock Net Delay (Destination): 2.620ns (routing 1.525ns, distribution 1.095ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.888    10.823    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y98        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y98        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079    10.902 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/Q
                         net (fo=1, routed)           0.482    11.384    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[3]
    SLICE_X108Y98        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.090    11.474 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.159    11.633    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X109Y98        LUT4 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.068    11.701 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.528    14.229    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X104Y287       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347    52.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.620    55.456    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X104Y287       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/C
                         clock pessimism              5.254    60.710    
                         clock uncertainty           -0.035    60.674    
    SLICE_X104Y287       FDCE (Recov_AFF2_SLICEM_C_CLR)
                                                     -0.066    60.608    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]
  -------------------------------------------------------------------
                         required time                         60.608    
                         arrival time                         -14.229    
  -------------------------------------------------------------------
                         slack                                 46.379    

Slack (MET) :             46.381ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.403ns  (logic 0.237ns (6.965%)  route 3.166ns (93.035%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.114ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.455ns = ( 55.455 - 50.000 ) 
    Source Clock Delay      (SCD):    10.823ns
    Clock Pessimism Removal (CPR):    5.254ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.888ns (routing 1.680ns, distribution 1.208ns)
  Clock Net Delay (Destination): 2.619ns (routing 1.525ns, distribution 1.094ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.888    10.823    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y98        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y98        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079    10.902 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/Q
                         net (fo=1, routed)           0.482    11.384    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[3]
    SLICE_X108Y98        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.090    11.474 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.159    11.633    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X109Y98        LUT4 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.068    11.701 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.525    14.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X104Y287       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347    52.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.619    55.455    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X104Y287       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/C
                         clock pessimism              5.254    60.709    
                         clock uncertainty           -0.035    60.673    
    SLICE_X104Y287       FDCE (Recov_EFF_SLICEM_C_CLR)
                                                     -0.066    60.607    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]
  -------------------------------------------------------------------
                         required time                         60.607    
                         arrival time                         -14.226    
  -------------------------------------------------------------------
                         slack                                 46.381    

Slack (MET) :             46.381ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.403ns  (logic 0.237ns (6.965%)  route 3.166ns (93.035%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.114ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.455ns = ( 55.455 - 50.000 ) 
    Source Clock Delay      (SCD):    10.823ns
    Clock Pessimism Removal (CPR):    5.254ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.888ns (routing 1.680ns, distribution 1.208ns)
  Clock Net Delay (Destination): 2.619ns (routing 1.525ns, distribution 1.094ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.888    10.823    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y98        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y98        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079    10.902 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/Q
                         net (fo=1, routed)           0.482    11.384    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[3]
    SLICE_X108Y98        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.090    11.474 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.159    11.633    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X109Y98        LUT4 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.068    11.701 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.525    14.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X104Y287       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347    52.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.619    55.455    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X104Y287       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/C
                         clock pessimism              5.254    60.709    
                         clock uncertainty           -0.035    60.673    
    SLICE_X104Y287       FDCE (Recov_EFF2_SLICEM_C_CLR)
                                                     -0.066    60.607    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]
  -------------------------------------------------------------------
                         required time                         60.607    
                         arrival time                         -14.226    
  -------------------------------------------------------------------
                         slack                                 46.381    

Slack (MET) :             46.381ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.403ns  (logic 0.237ns (6.965%)  route 3.166ns (93.035%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.114ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.455ns = ( 55.455 - 50.000 ) 
    Source Clock Delay      (SCD):    10.823ns
    Clock Pessimism Removal (CPR):    5.254ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.888ns (routing 1.680ns, distribution 1.208ns)
  Clock Net Delay (Destination): 2.619ns (routing 1.525ns, distribution 1.094ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.888    10.823    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y98        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y98        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079    10.902 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/Q
                         net (fo=1, routed)           0.482    11.384    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[3]
    SLICE_X108Y98        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.090    11.474 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.159    11.633    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X109Y98        LUT4 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.068    11.701 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.525    14.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X104Y287       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347    52.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.619    55.455    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X104Y287       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/C
                         clock pessimism              5.254    60.709    
                         clock uncertainty           -0.035    60.673    
    SLICE_X104Y287       FDCE (Recov_FFF_SLICEM_C_CLR)
                                                     -0.066    60.607    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]
  -------------------------------------------------------------------
                         required time                         60.607    
                         arrival time                         -14.226    
  -------------------------------------------------------------------
                         slack                                 46.381    

Slack (MET) :             46.381ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.403ns  (logic 0.237ns (6.965%)  route 3.166ns (93.035%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.114ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.455ns = ( 55.455 - 50.000 ) 
    Source Clock Delay      (SCD):    10.823ns
    Clock Pessimism Removal (CPR):    5.254ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.888ns (routing 1.680ns, distribution 1.208ns)
  Clock Net Delay (Destination): 2.619ns (routing 1.525ns, distribution 1.094ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.888    10.823    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y98        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y98        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079    10.902 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/Q
                         net (fo=1, routed)           0.482    11.384    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[3]
    SLICE_X108Y98        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.090    11.474 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.159    11.633    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X109Y98        LUT4 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.068    11.701 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.525    14.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X104Y287       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347    52.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.619    55.455    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X104Y287       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/C
                         clock pessimism              5.254    60.709    
                         clock uncertainty           -0.035    60.673    
    SLICE_X104Y287       FDCE (Recov_FFF2_SLICEM_C_CLR)
                                                     -0.066    60.607    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]
  -------------------------------------------------------------------
                         required time                         60.607    
                         arrival time                         -14.226    
  -------------------------------------------------------------------
                         slack                                 46.381    

Slack (MET) :             46.381ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.403ns  (logic 0.237ns (6.965%)  route 3.166ns (93.035%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.114ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.455ns = ( 55.455 - 50.000 ) 
    Source Clock Delay      (SCD):    10.823ns
    Clock Pessimism Removal (CPR):    5.254ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.888ns (routing 1.680ns, distribution 1.208ns)
  Clock Net Delay (Destination): 2.619ns (routing 1.525ns, distribution 1.094ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.888    10.823    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y98        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y98        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079    10.902 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/Q
                         net (fo=1, routed)           0.482    11.384    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[3]
    SLICE_X108Y98        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.090    11.474 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.159    11.633    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X109Y98        LUT4 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.068    11.701 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.525    14.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X104Y287       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347    52.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.619    55.455    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X104Y287       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/C
                         clock pessimism              5.254    60.709    
                         clock uncertainty           -0.035    60.673    
    SLICE_X104Y287       FDCE (Recov_GFF_SLICEM_C_CLR)
                                                     -0.066    60.607    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]
  -------------------------------------------------------------------
                         required time                         60.607    
                         arrival time                         -14.226    
  -------------------------------------------------------------------
                         slack                                 46.381    

Slack (MET) :             46.381ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.403ns  (logic 0.237ns (6.965%)  route 3.166ns (93.035%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.114ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.455ns = ( 55.455 - 50.000 ) 
    Source Clock Delay      (SCD):    10.823ns
    Clock Pessimism Removal (CPR):    5.254ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.888ns (routing 1.680ns, distribution 1.208ns)
  Clock Net Delay (Destination): 2.619ns (routing 1.525ns, distribution 1.094ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.888    10.823    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y98        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y98        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079    10.902 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/Q
                         net (fo=1, routed)           0.482    11.384    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[3]
    SLICE_X108Y98        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.090    11.474 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.159    11.633    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X109Y98        LUT4 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.068    11.701 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.525    14.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X104Y287       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347    52.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.619    55.455    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X104Y287       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/C
                         clock pessimism              5.254    60.709    
                         clock uncertainty           -0.035    60.673    
    SLICE_X104Y287       FDCE (Recov_GFF2_SLICEM_C_CLR)
                                                     -0.066    60.607    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]
  -------------------------------------------------------------------
                         required time                         60.607    
                         arrival time                         -14.226    
  -------------------------------------------------------------------
                         slack                                 46.381    

Slack (MET) :             46.381ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.403ns  (logic 0.237ns (6.965%)  route 3.166ns (93.035%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.114ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.455ns = ( 55.455 - 50.000 ) 
    Source Clock Delay      (SCD):    10.823ns
    Clock Pessimism Removal (CPR):    5.254ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.888ns (routing 1.680ns, distribution 1.208ns)
  Clock Net Delay (Destination): 2.619ns (routing 1.525ns, distribution 1.094ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.888    10.823    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y98        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y98        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079    10.902 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/Q
                         net (fo=1, routed)           0.482    11.384    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[3]
    SLICE_X108Y98        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.090    11.474 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.159    11.633    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X109Y98        LUT4 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.068    11.701 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.525    14.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X104Y287       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347    52.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.619    55.455    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X104Y287       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/C
                         clock pessimism              5.254    60.709    
                         clock uncertainty           -0.035    60.673    
    SLICE_X104Y287       FDCE (Recov_HFF_SLICEM_C_CLR)
                                                     -0.066    60.607    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]
  -------------------------------------------------------------------
                         required time                         60.607    
                         arrival time                         -14.226    
  -------------------------------------------------------------------
                         slack                                 46.381    

Slack (MET) :             46.381ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.403ns  (logic 0.237ns (6.965%)  route 3.166ns (93.035%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.114ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.455ns = ( 55.455 - 50.000 ) 
    Source Clock Delay      (SCD):    10.823ns
    Clock Pessimism Removal (CPR):    5.254ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.888ns (routing 1.680ns, distribution 1.208ns)
  Clock Net Delay (Destination): 2.619ns (routing 1.525ns, distribution 1.094ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.888    10.823    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y98        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y98        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079    10.902 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/Q
                         net (fo=1, routed)           0.482    11.384    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[3]
    SLICE_X108Y98        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.090    11.474 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.159    11.633    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X109Y98        LUT4 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.068    11.701 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.525    14.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X104Y287       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347    52.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.619    55.455    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X104Y287       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/C
                         clock pessimism              5.254    60.709    
                         clock uncertainty           -0.035    60.673    
    SLICE_X104Y287       FDCE (Recov_HFF2_SLICEM_C_CLR)
                                                     -0.066    60.607    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]
  -------------------------------------------------------------------
                         required time                         60.607    
                         arrival time                         -14.226    
  -------------------------------------------------------------------
                         slack                                 46.381    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.097ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.133ns  (logic 0.039ns (29.323%)  route 0.094ns (70.677%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.578ns
    Source Clock Delay      (SCD):    3.950ns
    Clock Pessimism Removal (CPR):    4.573ns
  Clock Net Delay (Source):      1.600ns (routing 0.916ns, distribution 0.684ns)
  Clock Net Delay (Destination): 1.807ns (routing 1.028ns, distribution 0.779ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.600     3.950    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X103Y291       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y291       FDPE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     3.989 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/Q
                         net (fo=1, routed)           0.094     4.083    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.rst_wr_reg2
    SLICE_X102Y291       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.807     8.578    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X102Y291       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/C
                         clock pessimism             -4.573     4.006    
    SLICE_X102Y291       FDPE (Remov_HFF2_SLICEL_C_PRE)
                                                     -0.020     3.986    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
  -------------------------------------------------------------------
                         required time                         -3.986    
                         arrival time                           4.083    
  -------------------------------------------------------------------
                         slack                                  0.097    

Slack (MET) :             0.115ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.139ns  (logic 0.040ns (28.749%)  route 0.099ns (71.251%))
  Logic Levels:           0  
  Clock Path Skew:        0.044ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.574ns
    Source Clock Delay      (SCD):    3.957ns
    Clock Pessimism Removal (CPR):    4.573ns
  Clock Net Delay (Source):      1.607ns (routing 0.916ns, distribution 0.691ns)
  Clock Net Delay (Destination): 1.803ns (routing 1.028ns, distribution 0.775ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.607     3.957    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X101Y291       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y291       FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     3.997 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.099     4.096    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X100Y291       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.803     8.574    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X100Y291       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/C
                         clock pessimism             -4.573     4.001    
    SLICE_X100Y291       FDPE (Remov_EFF_SLICEL_C_PRE)
                                                     -0.020     3.981    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.981    
                         arrival time                           4.096    
  -------------------------------------------------------------------
                         slack                                  0.115    

Slack (MET) :             0.115ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.139ns  (logic 0.040ns (28.749%)  route 0.099ns (71.251%))
  Logic Levels:           0  
  Clock Path Skew:        0.044ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.574ns
    Source Clock Delay      (SCD):    3.957ns
    Clock Pessimism Removal (CPR):    4.573ns
  Clock Net Delay (Source):      1.607ns (routing 0.916ns, distribution 0.691ns)
  Clock Net Delay (Destination): 1.803ns (routing 1.028ns, distribution 0.775ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.607     3.957    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X101Y291       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y291       FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     3.997 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.099     4.096    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X100Y291       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.803     8.574    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X100Y291       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/C
                         clock pessimism             -4.573     4.001    
    SLICE_X100Y291       FDCE (Remov_EFF2_SLICEL_C_CLR)
                                                     -0.020     3.981    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.981    
                         arrival time                           4.096    
  -------------------------------------------------------------------
                         slack                                  0.115    

Slack (MET) :             0.119ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.139ns  (logic 0.040ns (28.749%)  route 0.099ns (71.251%))
  Logic Levels:           0  
  Clock Path Skew:        0.040ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.570ns
    Source Clock Delay      (SCD):    3.957ns
    Clock Pessimism Removal (CPR):    4.573ns
  Clock Net Delay (Source):      1.607ns (routing 0.916ns, distribution 0.691ns)
  Clock Net Delay (Destination): 1.799ns (routing 1.028ns, distribution 0.771ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.607     3.957    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X101Y291       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y291       FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     3.997 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.099     4.096    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X100Y291       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.799     8.570    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X100Y291       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/C
                         clock pessimism             -4.573     3.997    
    SLICE_X100Y291       FDCE (Remov_DFF2_SLICEL_C_CLR)
                                                     -0.020     3.977    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.977    
                         arrival time                           4.096    
  -------------------------------------------------------------------
                         slack                                  0.119    

Slack (MET) :             0.119ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.139ns  (logic 0.040ns (28.749%)  route 0.099ns (71.251%))
  Logic Levels:           0  
  Clock Path Skew:        0.040ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.570ns
    Source Clock Delay      (SCD):    3.957ns
    Clock Pessimism Removal (CPR):    4.573ns
  Clock Net Delay (Source):      1.607ns (routing 0.916ns, distribution 0.691ns)
  Clock Net Delay (Destination): 1.799ns (routing 1.028ns, distribution 0.771ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.607     3.957    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X101Y291       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y291       FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     3.997 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.099     4.096    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X100Y291       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.799     8.570    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X100Y291       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/C
                         clock pessimism             -4.573     3.997    
    SLICE_X100Y291       FDPE (Remov_CFF2_SLICEL_C_PRE)
                                                     -0.020     3.977    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.977    
                         arrival time                           4.096    
  -------------------------------------------------------------------
                         slack                                  0.119    

Slack (MET) :             0.122ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.112ns  (logic 0.039ns (34.822%)  route 0.073ns (65.178%))
  Logic Levels:           0  
  Clock Path Skew:        0.010ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.580ns
    Source Clock Delay      (SCD):    3.962ns
    Clock Pessimism Removal (CPR):    4.608ns
  Clock Net Delay (Source):      1.612ns (routing 0.916ns, distribution 0.696ns)
  Clock Net Delay (Destination): 1.809ns (routing 1.028ns, distribution 0.781ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.612     3.962    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X102Y294       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y294       FDPE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     4.001 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=18, routed)          0.073     4.074    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/out[1]
    SLICE_X102Y294       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.809     8.580    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/rd_clk
    SLICE_X102Y294       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/C
                         clock pessimism             -4.608     3.972    
    SLICE_X102Y294       FDPE (Remov_AFF_SLICEL_C_PRE)
                                                     -0.020     3.952    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg
  -------------------------------------------------------------------
                         required time                         -3.952    
                         arrival time                           4.074    
  -------------------------------------------------------------------
                         slack                                  0.122    

Slack (MET) :             0.122ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.112ns  (logic 0.039ns (34.822%)  route 0.073ns (65.178%))
  Logic Levels:           0  
  Clock Path Skew:        0.010ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.580ns
    Source Clock Delay      (SCD):    3.962ns
    Clock Pessimism Removal (CPR):    4.608ns
  Clock Net Delay (Source):      1.612ns (routing 0.916ns, distribution 0.696ns)
  Clock Net Delay (Destination): 1.809ns (routing 1.028ns, distribution 0.781ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.612     3.962    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X102Y294       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y294       FDPE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     4.001 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=18, routed)          0.073     4.074    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/out[1]
    SLICE_X102Y294       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.809     8.580    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/rd_clk
    SLICE_X102Y294       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/C
                         clock pessimism             -4.608     3.972    
    SLICE_X102Y294       FDPE (Remov_DFF2_SLICEL_C_PRE)
                                                     -0.020     3.952    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg
  -------------------------------------------------------------------
                         required time                         -3.952    
                         arrival time                           4.074    
  -------------------------------------------------------------------
                         slack                                  0.122    

Slack (MET) :             0.122ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.112ns  (logic 0.039ns (34.822%)  route 0.073ns (65.178%))
  Logic Levels:           0  
  Clock Path Skew:        0.010ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.580ns
    Source Clock Delay      (SCD):    3.962ns
    Clock Pessimism Removal (CPR):    4.608ns
  Clock Net Delay (Source):      1.612ns (routing 0.916ns, distribution 0.696ns)
  Clock Net Delay (Destination): 1.809ns (routing 1.028ns, distribution 0.781ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.612     3.962    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X102Y294       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y294       FDPE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     4.001 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=18, routed)          0.073     4.074    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/out[1]
    SLICE_X102Y294       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.809     8.580    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/rd_clk
    SLICE_X102Y294       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/C
                         clock pessimism             -4.608     3.972    
    SLICE_X102Y294       FDPE (Remov_AFF2_SLICEL_C_PRE)
                                                     -0.020     3.952    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg
  -------------------------------------------------------------------
                         required time                         -3.952    
                         arrival time                           4.074    
  -------------------------------------------------------------------
                         slack                                  0.122    

Slack (MET) :             0.122ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.112ns  (logic 0.039ns (34.822%)  route 0.073ns (65.178%))
  Logic Levels:           0  
  Clock Path Skew:        0.010ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.580ns
    Source Clock Delay      (SCD):    3.962ns
    Clock Pessimism Removal (CPR):    4.608ns
  Clock Net Delay (Source):      1.612ns (routing 0.916ns, distribution 0.696ns)
  Clock Net Delay (Destination): 1.809ns (routing 1.028ns, distribution 0.781ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.612     3.962    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X102Y294       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y294       FDPE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     4.001 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=18, routed)          0.073     4.074    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/out[1]
    SLICE_X102Y294       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.809     8.580    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/rd_clk
    SLICE_X102Y294       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/C
                         clock pessimism             -4.608     3.972    
    SLICE_X102Y294       FDCE (Remov_CFF_SLICEL_C_CLR)
                                                     -0.020     3.952    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.952    
                         arrival time                           4.074    
  -------------------------------------------------------------------
                         slack                                  0.122    

Slack (MET) :             0.122ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.112ns  (logic 0.039ns (34.822%)  route 0.073ns (65.178%))
  Logic Levels:           0  
  Clock Path Skew:        0.010ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.580ns
    Source Clock Delay      (SCD):    3.962ns
    Clock Pessimism Removal (CPR):    4.608ns
  Clock Net Delay (Source):      1.612ns (routing 0.916ns, distribution 0.696ns)
  Clock Net Delay (Destination): 1.809ns (routing 1.028ns, distribution 0.781ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.612     3.962    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X102Y294       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y294       FDPE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     4.001 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=18, routed)          0.073     4.074    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/out[1]
    SLICE_X102Y294       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.809     8.580    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/rd_clk
    SLICE_X102Y294       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/C
                         clock pessimism             -4.608     3.972    
    SLICE_X102Y294       FDCE (Remov_CFF2_SLICEL_C_CLR)
                                                     -0.020     3.952    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.952    
                         arrival time                           4.074    
  -------------------------------------------------------------------
                         slack                                  0.122    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack       10.483ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.098ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             10.483ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[15]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.282ns  (logic 0.076ns (5.929%)  route 1.206ns (94.071%))
  Logic Levels:           0  
  Clock Path Skew:        -0.096ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.663ns = ( 15.665 - 12.002 ) 
    Source Clock Delay      (SCD):    3.337ns
    Clock Pessimism Removal (CPR):    -0.422ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 1.024ns (routing 0.155ns, distribution 0.869ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.136     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.413 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.206     4.619    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X102Y301       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[15]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863    13.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.024    15.665    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X102Y301       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[15]/C
                         clock pessimism             -0.422    15.243    
                         clock uncertainty           -0.076    15.168    
    SLICE_X102Y301       FDCE (Recov_EFF_SLICEL_C_CLR)
                                                     -0.066    15.102    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[15]
  -------------------------------------------------------------------
                         required time                         15.102    
                         arrival time                          -4.619    
  -------------------------------------------------------------------
                         slack                                 10.483    

Slack (MET) :             10.483ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[16]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.282ns  (logic 0.076ns (5.929%)  route 1.206ns (94.071%))
  Logic Levels:           0  
  Clock Path Skew:        -0.096ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.663ns = ( 15.665 - 12.002 ) 
    Source Clock Delay      (SCD):    3.337ns
    Clock Pessimism Removal (CPR):    -0.422ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 1.024ns (routing 0.155ns, distribution 0.869ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.136     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.413 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.206     4.619    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X102Y301       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[16]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863    13.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.024    15.665    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X102Y301       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[16]/C
                         clock pessimism             -0.422    15.243    
                         clock uncertainty           -0.076    15.168    
    SLICE_X102Y301       FDCE (Recov_HFF_SLICEL_C_CLR)
                                                     -0.066    15.102    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[16]
  -------------------------------------------------------------------
                         required time                         15.102    
                         arrival time                          -4.619    
  -------------------------------------------------------------------
                         slack                                 10.483    

Slack (MET) :             10.483ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[17]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.282ns  (logic 0.076ns (5.929%)  route 1.206ns (94.071%))
  Logic Levels:           0  
  Clock Path Skew:        -0.096ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.663ns = ( 15.665 - 12.002 ) 
    Source Clock Delay      (SCD):    3.337ns
    Clock Pessimism Removal (CPR):    -0.422ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 1.024ns (routing 0.155ns, distribution 0.869ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.136     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.413 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.206     4.619    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X102Y301       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[17]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863    13.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.024    15.665    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X102Y301       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[17]/C
                         clock pessimism             -0.422    15.243    
                         clock uncertainty           -0.076    15.168    
    SLICE_X102Y301       FDCE (Recov_EFF2_SLICEL_C_CLR)
                                                     -0.066    15.102    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[17]
  -------------------------------------------------------------------
                         required time                         15.102    
                         arrival time                          -4.619    
  -------------------------------------------------------------------
                         slack                                 10.483    

Slack (MET) :             10.483ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.282ns  (logic 0.076ns (5.929%)  route 1.206ns (94.071%))
  Logic Levels:           0  
  Clock Path Skew:        -0.096ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.663ns = ( 15.665 - 12.002 ) 
    Source Clock Delay      (SCD):    3.337ns
    Clock Pessimism Removal (CPR):    -0.422ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 1.024ns (routing 0.155ns, distribution 0.869ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.136     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.413 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.206     4.619    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X102Y301       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863    13.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.024    15.665    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X102Y301       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[2]/C
                         clock pessimism             -0.422    15.243    
                         clock uncertainty           -0.076    15.168    
    SLICE_X102Y301       FDCE (Recov_FFF_SLICEL_C_CLR)
                                                     -0.066    15.102    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[2]
  -------------------------------------------------------------------
                         required time                         15.102    
                         arrival time                          -4.619    
  -------------------------------------------------------------------
                         slack                                 10.483    

Slack (MET) :             10.483ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[4]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.282ns  (logic 0.076ns (5.929%)  route 1.206ns (94.071%))
  Logic Levels:           0  
  Clock Path Skew:        -0.096ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.663ns = ( 15.665 - 12.002 ) 
    Source Clock Delay      (SCD):    3.337ns
    Clock Pessimism Removal (CPR):    -0.422ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 1.024ns (routing 0.155ns, distribution 0.869ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.136     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.413 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.206     4.619    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X102Y301       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863    13.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.024    15.665    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X102Y301       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[4]/C
                         clock pessimism             -0.422    15.243    
                         clock uncertainty           -0.076    15.168    
    SLICE_X102Y301       FDCE (Recov_FFF2_SLICEL_C_CLR)
                                                     -0.066    15.102    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[4]
  -------------------------------------------------------------------
                         required time                         15.102    
                         arrival time                          -4.619    
  -------------------------------------------------------------------
                         slack                                 10.483    

Slack (MET) :             10.618ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clr_abort_rd_reg/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.147ns  (logic 0.076ns (6.625%)  route 1.071ns (93.375%))
  Logic Levels:           0  
  Clock Path Skew:        -0.095ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.664ns = ( 15.666 - 12.002 ) 
    Source Clock Delay      (SCD):    3.337ns
    Clock Pessimism Removal (CPR):    -0.422ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 1.025ns (routing 0.155ns, distribution 0.870ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.136     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.413 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.071     4.484    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X100Y300       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clr_abort_rd_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863    13.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.025    15.666    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X100Y300       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clr_abort_rd_reg/C
                         clock pessimism             -0.422    15.244    
                         clock uncertainty           -0.076    15.168    
    SLICE_X100Y300       FDCE (Recov_DFF_SLICEL_C_CLR)
                                                     -0.066    15.102    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clr_abort_rd_reg
  -------------------------------------------------------------------
                         required time                         15.102    
                         arrival time                          -4.484    
  -------------------------------------------------------------------
                         slack                                 10.618    

Slack (MET) :             10.618ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_read_mode_reg/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.147ns  (logic 0.076ns (6.625%)  route 1.071ns (93.375%))
  Logic Levels:           0  
  Clock Path Skew:        -0.095ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.664ns = ( 15.666 - 12.002 ) 
    Source Clock Delay      (SCD):    3.337ns
    Clock Pessimism Removal (CPR):    -0.422ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 1.025ns (routing 0.155ns, distribution 0.870ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.136     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.413 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.071     4.484    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X100Y300       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_read_mode_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863    13.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.025    15.666    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X100Y300       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_read_mode_reg/C
                         clock pessimism             -0.422    15.244    
                         clock uncertainty           -0.076    15.168    
    SLICE_X100Y300       FDCE (Recov_CFF_SLICEL_C_CLR)
                                                     -0.066    15.102    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_read_mode_reg
  -------------------------------------------------------------------
                         required time                         15.102    
                         arrival time                          -4.484    
  -------------------------------------------------------------------
                         slack                                 10.618    

Slack (MET) :             10.754ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.014ns  (logic 0.076ns (7.497%)  route 0.938ns (92.503%))
  Logic Levels:           0  
  Clock Path Skew:        -0.093ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.666ns = ( 15.668 - 12.002 ) 
    Source Clock Delay      (SCD):    3.337ns
    Clock Pessimism Removal (CPR):    -0.422ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 1.027ns (routing 0.155ns, distribution 0.872ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.136     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.413 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.938     4.351    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X101Y304       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863    13.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.027    15.668    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X101Y304       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]/C
                         clock pessimism             -0.422    15.246    
                         clock uncertainty           -0.076    15.170    
    SLICE_X101Y304       FDCE (Recov_CFF_SLICEL_C_CLR)
                                                     -0.066    15.104    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]
  -------------------------------------------------------------------
                         required time                         15.104    
                         arrival time                          -4.351    
  -------------------------------------------------------------------
                         slack                                 10.754    

Slack (MET) :             10.754ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.014ns  (logic 0.076ns (7.497%)  route 0.938ns (92.503%))
  Logic Levels:           0  
  Clock Path Skew:        -0.093ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.666ns = ( 15.668 - 12.002 ) 
    Source Clock Delay      (SCD):    3.337ns
    Clock Pessimism Removal (CPR):    -0.422ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 1.027ns (routing 0.155ns, distribution 0.872ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.136     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.413 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.938     4.351    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X101Y304       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863    13.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.027    15.668    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X101Y304       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]/C
                         clock pessimism             -0.422    15.246    
                         clock uncertainty           -0.076    15.170    
    SLICE_X101Y304       FDCE (Recov_AFF_SLICEL_C_CLR)
                                                     -0.066    15.104    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]
  -------------------------------------------------------------------
                         required time                         15.104    
                         arrival time                          -4.351    
  -------------------------------------------------------------------
                         slack                                 10.754    

Slack (MET) :             10.757ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.013ns  (logic 0.076ns (7.504%)  route 0.937ns (92.496%))
  Logic Levels:           0  
  Clock Path Skew:        -0.091ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.668ns = ( 15.670 - 12.002 ) 
    Source Clock Delay      (SCD):    3.337ns
    Clock Pessimism Removal (CPR):    -0.422ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 1.029ns (routing 0.155ns, distribution 0.874ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.136     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.413 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.937     4.350    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X101Y304       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863    13.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.029    15.670    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X101Y304       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[0]/C
                         clock pessimism             -0.422    15.248    
                         clock uncertainty           -0.076    15.172    
    SLICE_X101Y304       FDCE (Recov_HFF_SLICEL_C_CLR)
                                                     -0.066    15.106    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[0]
  -------------------------------------------------------------------
                         required time                         15.106    
                         arrival time                          -4.350    
  -------------------------------------------------------------------
                         slack                                 10.757    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.098ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.137ns  (logic 0.037ns (26.932%)  route 0.100ns (73.068%))
  Logic Levels:           0  
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.024ns
    Source Clock Delay      (SCD):    2.186ns
    Clock Pessimism Removal (CPR):    -0.221ns
  Clock Net Delay (Source):      0.637ns (routing 0.096ns, distribution 0.541ns)
  Clock Net Delay (Destination): 0.740ns (routing 0.108ns, distribution 0.632ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.637     2.186    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X103Y293       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y293       FDPE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.223 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.100     2.323    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/AR[0]
    SLICE_X101Y293       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.740     2.024    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X101Y293       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/C
                         clock pessimism              0.221     2.246    
    SLICE_X101Y293       FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     2.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.226    
                         arrival time                           2.323    
  -------------------------------------------------------------------
                         slack                                  0.098    

Slack (MET) :             0.098ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.137ns  (logic 0.037ns (26.932%)  route 0.100ns (73.068%))
  Logic Levels:           0  
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.024ns
    Source Clock Delay      (SCD):    2.186ns
    Clock Pessimism Removal (CPR):    -0.221ns
  Clock Net Delay (Source):      0.637ns (routing 0.096ns, distribution 0.541ns)
  Clock Net Delay (Destination): 0.740ns (routing 0.108ns, distribution 0.632ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.637     2.186    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X103Y293       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y293       FDPE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.223 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.100     2.323    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/AR[0]
    SLICE_X101Y293       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.740     2.024    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X101Y293       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/C
                         clock pessimism              0.221     2.246    
    SLICE_X101Y293       FDCE (Remov_EFF2_SLICEL_C_CLR)
                                                     -0.020     2.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.226    
                         arrival time                           2.323    
  -------------------------------------------------------------------
                         slack                                  0.098    

Slack (MET) :             0.098ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.137ns  (logic 0.037ns (26.932%)  route 0.100ns (73.068%))
  Logic Levels:           0  
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.024ns
    Source Clock Delay      (SCD):    2.186ns
    Clock Pessimism Removal (CPR):    -0.221ns
  Clock Net Delay (Source):      0.637ns (routing 0.096ns, distribution 0.541ns)
  Clock Net Delay (Destination): 0.740ns (routing 0.108ns, distribution 0.632ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.637     2.186    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X103Y293       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y293       FDPE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.223 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.100     2.323    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/AR[0]
    SLICE_X101Y293       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.740     2.024    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X101Y293       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/C
                         clock pessimism              0.221     2.246    
    SLICE_X101Y293       FDCE (Remov_FFF_SLICEL_C_CLR)
                                                     -0.020     2.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.226    
                         arrival time                           2.323    
  -------------------------------------------------------------------
                         slack                                  0.098    

Slack (MET) :             0.102ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/PRE
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.137ns  (logic 0.037ns (26.932%)  route 0.100ns (73.068%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.020ns
    Source Clock Delay      (SCD):    2.186ns
    Clock Pessimism Removal (CPR):    -0.221ns
  Clock Net Delay (Source):      0.637ns (routing 0.096ns, distribution 0.541ns)
  Clock Net Delay (Destination): 0.736ns (routing 0.108ns, distribution 0.628ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.637     2.186    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X103Y293       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y293       FDPE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.223 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.100     2.323    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/AR[0]
    SLICE_X102Y293       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.736     2.020    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X102Y293       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/C
                         clock pessimism              0.221     2.242    
    SLICE_X102Y293       FDPE (Remov_DFF_SLICEL_C_PRE)
                                                     -0.020     2.222    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg
  -------------------------------------------------------------------
                         required time                         -2.222    
                         arrival time                           2.323    
  -------------------------------------------------------------------
                         slack                                  0.102    

Slack (MET) :             0.102ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/PRE
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.137ns  (logic 0.037ns (26.932%)  route 0.100ns (73.068%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.020ns
    Source Clock Delay      (SCD):    2.186ns
    Clock Pessimism Removal (CPR):    -0.221ns
  Clock Net Delay (Source):      0.637ns (routing 0.096ns, distribution 0.541ns)
  Clock Net Delay (Destination): 0.736ns (routing 0.108ns, distribution 0.628ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.637     2.186    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X103Y293       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y293       FDPE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.223 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.100     2.323    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/AR[0]
    SLICE_X102Y293       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.736     2.020    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X102Y293       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
                         clock pessimism              0.221     2.242    
    SLICE_X102Y293       FDPE (Remov_CFF_SLICEL_C_PRE)
                                                     -0.020     2.222    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg
  -------------------------------------------------------------------
                         required time                         -2.222    
                         arrival time                           2.323    
  -------------------------------------------------------------------
                         slack                                  0.102    

Slack (MET) :             0.102ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.137ns  (logic 0.037ns (26.932%)  route 0.100ns (73.068%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.020ns
    Source Clock Delay      (SCD):    2.186ns
    Clock Pessimism Removal (CPR):    -0.221ns
  Clock Net Delay (Source):      0.637ns (routing 0.096ns, distribution 0.541ns)
  Clock Net Delay (Destination): 0.736ns (routing 0.108ns, distribution 0.628ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.637     2.186    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X103Y293       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y293       FDPE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.223 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.100     2.323    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/AR[0]
    SLICE_X102Y293       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.736     2.020    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X102Y293       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/C
                         clock pessimism              0.221     2.242    
    SLICE_X102Y293       FDCE (Remov_DFF2_SLICEL_C_CLR)
                                                     -0.020     2.222    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.222    
                         arrival time                           2.323    
  -------------------------------------------------------------------
                         slack                                  0.102    

Slack (MET) :             0.102ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]/PRE
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.137ns  (logic 0.037ns (26.932%)  route 0.100ns (73.068%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.020ns
    Source Clock Delay      (SCD):    2.186ns
    Clock Pessimism Removal (CPR):    -0.221ns
  Clock Net Delay (Source):      0.637ns (routing 0.096ns, distribution 0.541ns)
  Clock Net Delay (Destination): 0.736ns (routing 0.108ns, distribution 0.628ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.637     2.186    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X103Y293       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y293       FDPE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.223 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.100     2.323    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/AR[0]
    SLICE_X101Y293       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.736     2.020    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X101Y293       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]/C
                         clock pessimism              0.221     2.242    
    SLICE_X101Y293       FDPE (Remov_CFF2_SLICEL_C_PRE)
                                                     -0.020     2.222    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.222    
                         arrival time                           2.323    
  -------------------------------------------------------------------
                         slack                                  0.102    

Slack (MET) :             0.102ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.137ns  (logic 0.037ns (26.932%)  route 0.100ns (73.068%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.020ns
    Source Clock Delay      (SCD):    2.186ns
    Clock Pessimism Removal (CPR):    -0.221ns
  Clock Net Delay (Source):      0.637ns (routing 0.096ns, distribution 0.541ns)
  Clock Net Delay (Destination): 0.736ns (routing 0.108ns, distribution 0.628ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.637     2.186    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X103Y293       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y293       FDPE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.223 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.100     2.323    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/AR[0]
    SLICE_X101Y293       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.736     2.020    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X101Y293       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/C
                         clock pessimism              0.221     2.242    
    SLICE_X101Y293       FDCE (Remov_DFF_SLICEL_C_CLR)
                                                     -0.020     2.222    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.222    
                         arrival time                           2.323    
  -------------------------------------------------------------------
                         slack                                  0.102    

Slack (MET) :             0.102ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.137ns  (logic 0.037ns (26.932%)  route 0.100ns (73.068%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.020ns
    Source Clock Delay      (SCD):    2.186ns
    Clock Pessimism Removal (CPR):    -0.221ns
  Clock Net Delay (Source):      0.637ns (routing 0.096ns, distribution 0.541ns)
  Clock Net Delay (Destination): 0.736ns (routing 0.108ns, distribution 0.628ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.637     2.186    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X103Y293       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y293       FDPE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.223 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.100     2.323    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/AR[0]
    SLICE_X102Y293       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.736     2.020    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X102Y293       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/C
                         clock pessimism              0.221     2.242    
    SLICE_X102Y293       FDCE (Remov_CFF2_SLICEL_C_CLR)
                                                     -0.020     2.222    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.222    
                         arrival time                           2.323    
  -------------------------------------------------------------------
                         slack                                  0.102    

Slack (MET) :             0.102ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.137ns  (logic 0.037ns (26.932%)  route 0.100ns (73.068%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.020ns
    Source Clock Delay      (SCD):    2.186ns
    Clock Pessimism Removal (CPR):    -0.221ns
  Clock Net Delay (Source):      0.637ns (routing 0.096ns, distribution 0.541ns)
  Clock Net Delay (Destination): 0.736ns (routing 0.108ns, distribution 0.628ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.637     2.186    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X103Y293       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y293       FDPE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.223 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.100     2.323    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/AR[0]
    SLICE_X101Y293       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.736     2.020    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X101Y293       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/C
                         clock pessimism              0.221     2.242    
    SLICE_X101Y293       FDCE (Remov_DFF2_SLICEL_C_CLR)
                                                     -0.020     2.222    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.222    
                         arrival time                           2.323    
  -------------------------------------------------------------------
                         slack                                  0.102    





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_4_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.722ns  (logic 0.948ns (25.459%)  route 2.774ns (74.541%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.901ns (routing 1.381ns, distribution 1.520ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.901     3.574    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y171        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y171        FDCE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     3.652 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/Q
                         net (fo=2, routed)           2.774     6.426    PMOD0_4_LS_OBUF
    J16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.870     7.295 r  PMOD0_4_LS_OBUF_inst/O
                         net (fo=0)                   0.000     7.295    PMOD0_4_LS
    J16                                                               r  PMOD0_4_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_1_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.596ns  (logic 0.938ns (26.086%)  route 2.658ns (73.914%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.889ns (routing 1.381ns, distribution 1.508ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.889     3.562    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y175        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y175        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     3.641 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/Q
                         net (fo=2, routed)           2.658     6.300    PMOD0_1_LS_OBUF
    M18                  OBUF (Prop_OUTBUF_HPIOB_SNGL_I_O)
                                                      0.859     7.159 r  PMOD0_1_LS_OBUF_inst/O
                         net (fo=0)                   0.000     7.159    PMOD0_1_LS
    M18                                                               r  PMOD0_1_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_2_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.273ns  (logic 0.945ns (28.867%)  route 2.328ns (71.133%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.863ns (routing 1.381ns, distribution 1.482ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.863     3.536    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y224        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y224        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     3.615 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/Q
                         net (fo=2, routed)           2.328     5.944    PMOD0_2_LS_OBUF
    H16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.866     6.809 r  PMOD0_2_LS_OBUF_inst/O
                         net (fo=0)                   0.000     6.809    PMOD0_2_LS
    H16                                                               r  PMOD0_2_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_0_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.239ns  (logic 0.926ns (28.598%)  route 2.313ns (71.402%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.845ns (routing 1.381ns, distribution 1.464ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.845     3.518    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X74Y237        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y237        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.597 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/Q
                         net (fo=2, routed)           2.313     5.910    PMOD0_0_LS_OBUF
    C17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.847     6.757 r  PMOD0_0_LS_OBUF_inst/O
                         net (fo=0)                   0.000     6.757    PMOD0_0_LS
    C17                                                               r  PMOD0_0_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_3_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.155ns  (logic 0.943ns (29.885%)  route 2.212ns (70.115%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.848ns (routing 1.381ns, distribution 1.467ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.848     3.521    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y219        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y219        FDCE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     3.599 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/Q
                         net (fo=2, routed)           2.212     5.811    PMOD0_3_LS_OBUF
    H17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.865     6.676 r  PMOD0_3_LS_OBUF_inst/O
                         net (fo=0)                   0.000     6.676    PMOD0_3_LS
    H17                                                               r  PMOD0_3_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_7_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.151ns  (logic 0.937ns (29.737%)  route 2.214ns (70.263%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.827ns (routing 1.381ns, distribution 1.446ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.827     3.500    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X67Y196        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y196        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     3.578 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/Q
                         net (fo=2, routed)           2.214     5.792    PMOD0_7_LS_OBUF
    J15                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.859     6.651 r  PMOD0_7_LS_OBUF_inst/O
                         net (fo=0)                   0.000     6.651    PMOD0_7_LS
    J15                                                               r  PMOD0_7_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_6_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.084ns  (logic 0.938ns (30.428%)  route 2.145ns (69.572%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.845ns (routing 1.381ns, distribution 1.464ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.845     3.518    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X74Y237        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y237        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     3.597 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/Q
                         net (fo=2, routed)           2.145     5.742    PMOD0_6_LS_OBUF
    H15                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.859     6.602 r  PMOD0_6_LS_OBUF_inst/O
                         net (fo=0)                   0.000     6.602    PMOD0_6_LS
    H15                                                               r  PMOD0_6_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_5_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.915ns  (logic 0.948ns (32.515%)  route 1.967ns (67.485%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.896ns (routing 1.381ns, distribution 1.515ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.896     3.569    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X74Y240        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y240        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     3.648 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/Q
                         net (fo=2, routed)           1.967     5.615    PMOD0_5_LS_OBUF
    K16                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.869     6.484 r  PMOD0_5_LS_OBUF_inst/O
                         net (fo=0)                   0.000     6.484    PMOD0_5_LS
    K16                                                               r  PMOD0_5_LS (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_5_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.417ns  (logic 0.481ns (33.955%)  route 0.936ns (66.045%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.583ns (routing 0.748ns, distribution 0.835ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.583     1.932    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X74Y240        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y240        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.971 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/Q
                         net (fo=2, routed)           0.936     2.907    PMOD0_5_LS_OBUF
    K16                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.442     3.349 r  PMOD0_5_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.349    PMOD0_5_LS
    K16                                                               r  PMOD0_5_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_6_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.501ns  (logic 0.472ns (31.432%)  route 1.029ns (68.568%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.556ns (routing 0.748ns, distribution 0.808ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.556     1.905    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X74Y237        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y237        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.944 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/Q
                         net (fo=2, routed)           1.029     2.973    PMOD0_6_LS_OBUF
    H15                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.433     3.406 r  PMOD0_6_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.406    PMOD0_6_LS
    H15                                                               r  PMOD0_6_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_3_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.531ns  (logic 0.476ns (31.106%)  route 1.055ns (68.894%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.558ns (routing 0.748ns, distribution 0.810ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.558     1.907    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y219        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y219        FDCE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     1.945 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/Q
                         net (fo=2, routed)           1.055     3.000    PMOD0_3_LS_OBUF
    H17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.438     3.438 r  PMOD0_3_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.438    PMOD0_3_LS
    H17                                                               r  PMOD0_3_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_7_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.552ns  (logic 0.472ns (30.393%)  route 1.080ns (69.607%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.547ns (routing 0.748ns, distribution 0.799ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.547     1.896    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X67Y196        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y196        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.935 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/Q
                         net (fo=2, routed)           1.080     3.015    PMOD0_7_LS_OBUF
    J15                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.433     3.448 r  PMOD0_7_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.448    PMOD0_7_LS
    J15                                                               r  PMOD0_7_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_0_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.580ns  (logic 0.460ns (29.121%)  route 1.120ns (70.879%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.556ns (routing 0.748ns, distribution 0.808ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.556     1.905    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X74Y237        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y237        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.944 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/Q
                         net (fo=2, routed)           1.120     3.064    PMOD0_0_LS_OBUF
    C17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.421     3.485 r  PMOD0_0_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.485    PMOD0_0_LS
    C17                                                               r  PMOD0_0_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_2_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.593ns  (logic 0.478ns (30.017%)  route 1.115ns (69.983%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.564ns (routing 0.748ns, distribution 0.816ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.564     1.913    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y224        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y224        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.952 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/Q
                         net (fo=2, routed)           1.115     3.067    PMOD0_2_LS_OBUF
    H16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.439     3.506 r  PMOD0_2_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.506    PMOD0_2_LS
    H16                                                               r  PMOD0_2_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_1_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.758ns  (logic 0.472ns (26.834%)  route 1.286ns (73.166%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.580ns (routing 0.748ns, distribution 0.832ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.580     1.929    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y175        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y175        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.968 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/Q
                         net (fo=2, routed)           1.286     3.254    PMOD0_1_LS_OBUF
    M18                  OBUF (Prop_OUTBUF_HPIOB_SNGL_I_O)
                                                      0.433     3.686 r  PMOD0_1_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.686    PMOD0_1_LS
    M18                                                               r  PMOD0_1_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_4_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.835ns  (logic 0.481ns (26.208%)  route 1.354ns (73.792%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.583ns (routing 0.748ns, distribution 0.835ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.583     1.932    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y171        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y171        FDCE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     1.970 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/Q
                         net (fo=2, routed)           1.354     3.324    PMOD0_4_LS_OBUF
    J16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.443     3.767 r  PMOD0_4_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.767    PMOD0_4_LS
    J16                                                               r  PMOD0_4_LS (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  RFADC0_CLK

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.902ns  (logic 0.112ns (2.870%)  route 3.790ns (97.130%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.749ns (routing 1.020ns, distribution 0.729ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           2.033     2.033    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X72Y284        LUT1 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.112     2.145 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           1.757     3.902    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X75Y105        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.749     2.135    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X75Y105        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.923ns  (logic 0.039ns (2.028%)  route 1.884ns (97.972%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.213ns (routing 0.670ns, distribution 0.543ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           0.999     0.999    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X72Y284        LUT1 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.039     1.038 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.885     1.923    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X75Y105        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y1 (CLOCK_ROOT)    net (fo=35, routed)          1.213     1.565    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X75Y105        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  RFDAC0_CLK

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.632ns  (logic 0.090ns (3.420%)  route 2.542ns (96.580%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.619ns (routing 1.256ns, distribution 1.363ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           2.031     2.031    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X72Y288        LUT1 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.090     2.121 r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.511     2.632    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X72Y311        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.619     3.140    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X72Y311        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.264ns  (logic 0.035ns (2.769%)  route 1.229ns (97.231%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.783ns (routing 0.827ns, distribution 0.956ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           0.994     0.994    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X72Y288        LUT1 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.035     1.029 r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.235     1.264    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X72Y311        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.783     2.231    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X72Y311        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  RFDAC0_CLK

Max Delay         30197 Endpoints
Min Delay         30197 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_3/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.399ns  (logic 0.217ns (4.019%)  route 5.182ns (95.981%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.256ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.328ns
    Source Clock Delay      (SCD):    3.584ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.911ns (routing 1.381ns, distribution 1.530ns)
  Clock Net Delay (Destination): 2.807ns (routing 1.256ns, distribution 1.551ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.911     3.584    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.663 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.402     5.065    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.093 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       1.326     6.419    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X106Y182       LUT1 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.110     6.529 r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=17, routed)          2.454     8.983    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X107Y293       FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_3/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.807     3.328    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X107Y293       FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_3/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_8/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.100ns  (logic 0.204ns (4.000%)  route 4.896ns (96.000%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.210ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.374ns
    Source Clock Delay      (SCD):    3.584ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.911ns (routing 1.381ns, distribution 1.530ns)
  Clock Net Delay (Destination): 2.853ns (routing 1.256ns, distribution 1.597ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.911     3.584    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.663 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.402     5.065    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.093 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       1.412     6.505    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X105Y155       LUT1 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.097     6.602 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=14, routed)          2.082     8.684    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X113Y248       FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_8/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.853     3.374    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X113Y248       FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_8/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_4/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.967ns  (logic 0.206ns (4.147%)  route 4.761ns (95.853%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.474ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.110ns
    Source Clock Delay      (SCD):    3.584ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.911ns (routing 1.381ns, distribution 1.530ns)
  Clock Net Delay (Destination): 2.589ns (routing 1.256ns, distribution 1.333ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.911     3.584    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.663 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.402     5.065    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.093 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       1.620     6.713    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X31Y161        LUT1 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.099     6.812 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=20, routed)          1.739     8.551    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X26Y52         FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_4/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.589     3.110    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X26Y52         FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_4/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_17/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.939ns  (logic 0.206ns (4.170%)  route 4.733ns (95.830%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.545ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.039ns
    Source Clock Delay      (SCD):    3.584ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.911ns (routing 1.381ns, distribution 1.530ns)
  Clock Net Delay (Destination): 2.518ns (routing 1.256ns, distribution 1.262ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.911     3.584    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.663 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.402     5.065    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.093 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       1.620     6.713    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X31Y161        LUT1 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.099     6.812 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=20, routed)          1.711     8.523    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X33Y220        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_17/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.518     3.039    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X33Y220        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_17/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_6/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.792ns  (logic 0.217ns (4.529%)  route 4.575ns (95.471%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.270ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.314ns
    Source Clock Delay      (SCD):    3.584ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.911ns (routing 1.381ns, distribution 1.530ns)
  Clock Net Delay (Destination): 2.793ns (routing 1.256ns, distribution 1.537ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.911     3.584    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.663 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.402     5.065    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.093 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       1.326     6.419    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X106Y182       LUT1 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.110     6.529 r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=17, routed)          1.847     8.376    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X106Y268       FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_6/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.793     3.314    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X106Y268       FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_6/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_2/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.761ns  (logic 0.204ns (4.285%)  route 4.557ns (95.715%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.262ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.322ns
    Source Clock Delay      (SCD):    3.584ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.911ns (routing 1.381ns, distribution 1.530ns)
  Clock Net Delay (Destination): 2.801ns (routing 1.256ns, distribution 1.545ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.911     3.584    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.663 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.402     5.065    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.093 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       1.412     6.505    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X105Y155       LUT1 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.097     6.602 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=14, routed)          1.743     8.345    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X110Y229       FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_2/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.801     3.322    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X110Y229       FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_2/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_7/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.751ns  (logic 0.257ns (5.410%)  route 4.494ns (94.590%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.108ns
    Source Clock Delay      (SCD):    3.584ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.911ns (routing 1.381ns, distribution 1.530ns)
  Clock Net Delay (Destination): 2.587ns (routing 1.256ns, distribution 1.331ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.911     3.584    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.663 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.402     5.065    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.093 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       1.318     6.411    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X73Y195        LUT1 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150     6.561 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=16, routed)          1.774     8.335    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X74Y270        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_7/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.587     3.108    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X74Y270        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_7/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_5/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.740ns  (logic 0.206ns (4.346%)  route 4.534ns (95.654%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.534ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.050ns
    Source Clock Delay      (SCD):    3.584ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.911ns (routing 1.381ns, distribution 1.530ns)
  Clock Net Delay (Destination): 2.529ns (routing 1.256ns, distribution 1.273ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.911     3.584    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.663 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.402     5.065    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.093 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       1.620     6.713    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X31Y161        LUT1 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.099     6.812 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=20, routed)          1.512     8.324    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X33Y201        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_5/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.529     3.050    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X33Y201        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_5/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_1/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.740ns  (logic 0.257ns (5.422%)  route 4.483ns (94.578%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.493ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.091ns
    Source Clock Delay      (SCD):    3.584ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.911ns (routing 1.381ns, distribution 1.530ns)
  Clock Net Delay (Destination): 2.570ns (routing 1.256ns, distribution 1.314ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.911     3.584    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.663 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.402     5.065    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.093 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       1.318     6.411    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X73Y195        LUT1 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150     6.561 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=16, routed)          1.763     8.324    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X69Y98         FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_1/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.570     3.091    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X69Y98         FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_1/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_13/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.669ns  (logic 0.206ns (4.412%)  route 4.463ns (95.588%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.543ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.041ns
    Source Clock Delay      (SCD):    3.584ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.911ns (routing 1.381ns, distribution 1.530ns)
  Clock Net Delay (Destination): 2.520ns (routing 1.256ns, distribution 1.264ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.911     3.584    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.663 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.402     5.065    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.093 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       1.620     6.713    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X31Y161        LUT1 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.099     6.812 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=20, routed)          1.441     8.253    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X37Y202        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_13/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.520     3.041    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X37Y202        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_13/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[10]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.355ns  (logic 0.056ns (4.133%)  route 1.299ns (95.867%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.320ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.263ns
    Source Clock Delay      (SCD):    1.943ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.594ns (routing 0.748ns, distribution 0.846ns)
  Clock Net Delay (Destination): 1.815ns (routing 0.827ns, distribution 0.988ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.594     1.943    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.982 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.730     2.712    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.729 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       0.569     3.298    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aresetn
    SLICE_X81Y277        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[10]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.815     2.263    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X81Y277        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].prodg_y_full_real_r_reg[2]/DSP_M_DATA_INST/RSTM
                            (rising edge-triggered cell DSP_M_DATA clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.358ns  (logic 0.056ns (4.124%)  route 1.302ns (95.876%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.360ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.303ns
    Source Clock Delay      (SCD):    1.943ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.594ns (routing 0.748ns, distribution 0.846ns)
  Clock Net Delay (Destination): 1.855ns (routing 0.827ns, distribution 1.028ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.594     1.943    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.982 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.730     2.712    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.729 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       0.572     3.301    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].prodg_y_full_real_r_reg[2]/RSTM
    DSP48E2_X15Y111      DSP_M_DATA                                   r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].prodg_y_full_real_r_reg[2]/DSP_M_DATA_INST/RSTM  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.855     2.303    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].prodg_y_full_real_r_reg[2]/CLK
    DSP48E2_X15Y111      DSP_M_DATA                                   r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].prodg_y_full_real_r_reg[2]/DSP_M_DATA_INST/CLK

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].prodg_y_full_real_r_reg[7]/DSP_M_DATA_INST/RSTM
                            (rising edge-triggered cell DSP_M_DATA clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.358ns  (logic 0.056ns (4.124%)  route 1.302ns (95.876%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.364ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.307ns
    Source Clock Delay      (SCD):    1.943ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.594ns (routing 0.748ns, distribution 0.846ns)
  Clock Net Delay (Destination): 1.859ns (routing 0.827ns, distribution 1.032ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.594     1.943    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.982 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.730     2.712    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.729 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       0.572     3.301    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].prodg_y_full_real_r_reg[7]/RSTM
    DSP48E2_X15Y106      DSP_M_DATA                                   r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].prodg_y_full_real_r_reg[7]/DSP_M_DATA_INST/RSTM  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.859     2.307    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].prodg_y_full_real_r_reg[7]/CLK
    DSP48E2_X15Y106      DSP_M_DATA                                   r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].prodg_y_full_real_r_reg[7]/DSP_M_DATA_INST/CLK

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[15].phase_v0_r4_reg[15][1]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.359ns  (logic 0.056ns (4.121%)  route 1.303ns (95.879%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.330ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.273ns
    Source Clock Delay      (SCD):    1.943ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.594ns (routing 0.748ns, distribution 0.846ns)
  Clock Net Delay (Destination): 1.825ns (routing 0.827ns, distribution 0.998ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.594     1.943    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.982 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.730     2.712    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.729 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       0.573     3.302    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aresetn
    SLICE_X84Y277        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[15].phase_v0_r4_reg[15][1]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.825     2.273    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X84Y277        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[15].phase_v0_r4_reg[15][1]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r4_reg[6]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.359ns  (logic 0.056ns (4.121%)  route 1.303ns (95.879%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.330ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.273ns
    Source Clock Delay      (SCD):    1.943ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.594ns (routing 0.748ns, distribution 0.846ns)
  Clock Net Delay (Destination): 1.825ns (routing 0.827ns, distribution 0.998ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.594     1.943    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.982 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.730     2.712    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.729 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       0.573     3.302    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aresetn
    SLICE_X84Y277        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r4_reg[6]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.825     2.273    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X84Y277        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r4_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r5_reg[31]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.359ns  (logic 0.056ns (4.121%)  route 1.303ns (95.879%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.330ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.273ns
    Source Clock Delay      (SCD):    1.943ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.594ns (routing 0.748ns, distribution 0.846ns)
  Clock Net Delay (Destination): 1.825ns (routing 0.827ns, distribution 0.998ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.594     1.943    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.982 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.730     2.712    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.729 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       0.573     3.302    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aresetn
    SLICE_X84Y277        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r5_reg[31]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.825     2.273    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X84Y277        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r5_reg[31]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1102]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.359ns  (logic 0.056ns (4.121%)  route 1.303ns (95.879%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.330ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.273ns
    Source Clock Delay      (SCD):    1.943ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.594ns (routing 0.748ns, distribution 0.846ns)
  Clock Net Delay (Destination): 1.825ns (routing 0.827ns, distribution 0.998ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.594     1.943    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.982 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.730     2.712    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.729 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       0.573     3.302    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/clear
    SLICE_X84Y277        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1102]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.825     2.273    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X84Y277        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1102]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1111]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.359ns  (logic 0.056ns (4.121%)  route 1.303ns (95.879%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.330ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.273ns
    Source Clock Delay      (SCD):    1.943ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.594ns (routing 0.748ns, distribution 0.846ns)
  Clock Net Delay (Destination): 1.825ns (routing 0.827ns, distribution 0.998ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.594     1.943    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.982 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.730     2.712    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.729 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       0.573     3.302    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/clear
    SLICE_X84Y277        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1111]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.825     2.273    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X84Y277        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1111]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[12].phase_v1_r1_reg[12][18]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.360ns  (logic 0.056ns (4.119%)  route 1.304ns (95.881%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.324ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.267ns
    Source Clock Delay      (SCD):    1.943ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.594ns (routing 0.748ns, distribution 0.846ns)
  Clock Net Delay (Destination): 1.819ns (routing 0.827ns, distribution 0.992ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.594     1.943    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.982 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.730     2.712    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.729 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       0.574     3.303    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aresetn
    SLICE_X81Y264        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[12].phase_v1_r1_reg[12][18]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.819     2.267    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X81Y264        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[12].phase_v1_r1_reg[12][18]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[12].phase_v1_r1_reg[12][19]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.360ns  (logic 0.056ns (4.119%)  route 1.304ns (95.881%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.324ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.267ns
    Source Clock Delay      (SCD):    1.943ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.594ns (routing 0.748ns, distribution 0.846ns)
  Clock Net Delay (Destination): 1.819ns (routing 0.827ns, distribution 0.992ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.594     1.943    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.982 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.730     2.712    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.729 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       0.574     3.303    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aresetn
    SLICE_X81Y264        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[12].phase_v1_r1_reg[12][19]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.819     2.267    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X81Y264        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[12].phase_v1_r1_reg[12][19]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  RFDAC0_CLK

Max Delay             4 Endpoints
Min Delay             4 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.174ns  (logic 0.176ns (14.986%)  route 0.998ns (85.014%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -1.720ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.211ns
    Source Clock Delay      (SCD):    4.931ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.372ns (routing 0.878ns, distribution 1.494ns)
  Clock Net Delay (Destination): 2.690ns (routing 1.256ns, distribution 1.434ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.372     4.931    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X85Y144        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y144        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     5.011 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/Q
                         net (fo=207, routed)         0.681     5.692    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]_0[1]
    SLICE_X92Y146        LUT2 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.096     5.788 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][1]_i_1__0/O
                         net (fo=1, routed)           0.317     6.105    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_g[1]
    SLICE_X94Y147        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.690     3.211    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X94Y147        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.053ns  (logic 0.213ns (20.223%)  route 0.840ns (79.777%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -1.726ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.205ns
    Source Clock Delay      (SCD):    4.931ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.372ns (routing 0.878ns, distribution 1.494ns)
  Clock Net Delay (Destination): 2.684ns (routing 1.256ns, distribution 1.428ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.372     4.931    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X85Y144        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y144        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     5.011 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/Q
                         net (fo=207, routed)         0.825     5.836    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]_0[1]
    SLICE_X95Y152        LUT2 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.133     5.969 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][2]_i_1__0/O
                         net (fo=1, routed)           0.015     5.984    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_g[2]
    SLICE_X95Y152        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.684     3.205    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X95Y152        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.880ns  (logic 0.129ns (14.651%)  route 0.751ns (85.349%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -1.742ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.200ns
    Source Clock Delay      (SCD):    4.942ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.383ns (routing 0.878ns, distribution 1.505ns)
  Clock Net Delay (Destination): 2.679ns (routing 1.256ns, distribution 1.423ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.383     4.942    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X85Y134        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y134        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     5.021 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/Q
                         net (fo=204, routed)         0.488     5.509    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]_0[0]
    SLICE_X92Y146        LUT2 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050     5.559 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][0]_i_1__0/O
                         net (fo=4, routed)           0.263     5.822    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/D[0]
    SLICE_X92Y149        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.679     3.200    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X92Y149        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.329ns  (logic 0.079ns (23.988%)  route 0.250ns (76.012%))
  Logic Levels:           0  
  Clock Path Skew:        -1.742ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.189ns
    Source Clock Delay      (SCD):    4.931ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.372ns (routing 0.878ns, distribution 1.494ns)
  Clock Net Delay (Destination): 2.668ns (routing 1.256ns, distribution 1.412ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.372     4.931    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X85Y144        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y144        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     5.010 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/Q
                         net (fo=203, routed)         0.250     5.260    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]_0[2]
    SLICE_X85Y149        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.668     3.189    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X85Y149        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.146ns  (logic 0.039ns (26.702%)  route 0.107ns (73.298%))
  Logic Levels:           0  
  Clock Path Skew:        -0.729ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.265ns
    Source Clock Delay      (SCD):    2.994ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.309ns (routing 0.484ns, distribution 0.825ns)
  Clock Net Delay (Destination): 1.817ns (routing 0.827ns, distribution 0.990ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.309     2.994    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X85Y144        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y144        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     3.033 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/Q
                         net (fo=203, routed)         0.107     3.140    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]_0[2]
    SLICE_X85Y149        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.817     2.265    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X85Y149        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]_rep__0/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.377ns  (logic 0.060ns (15.910%)  route 0.317ns (84.090%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.723ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.273ns
    Source Clock Delay      (SCD):    2.997ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.312ns (routing 0.484ns, distribution 0.828ns)
  Clock Net Delay (Destination): 1.825ns (routing 0.827ns, distribution 0.998ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.312     2.997    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X85Y144        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]_rep__0/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y144        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.040     3.037 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]_rep__0/Q
                         net (fo=115, routed)         0.311     3.348    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_reg[3]_rep__0_n_0_alias
    SLICE_X95Y152        LUT2 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.020     3.368 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][2]_i_1__0/O
                         net (fo=1, routed)           0.006     3.374    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_g[2]
    SLICE_X95Y152        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.825     2.273    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X95Y152        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.403ns  (logic 0.091ns (22.560%)  route 0.312ns (77.440%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.725ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.269ns
    Source Clock Delay      (SCD):    2.994ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.309ns (routing 0.484ns, distribution 0.825ns)
  Clock Net Delay (Destination): 1.821ns (routing 0.827ns, distribution 0.994ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.309     2.994    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X85Y144        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y144        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     3.035 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[0]/Q
                         net (fo=203, routed)         0.201     3.236    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_reg[0]_alias
    SLICE_X92Y146        LUT2 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.050     3.286 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][0]_i_1__0/O
                         net (fo=4, routed)           0.111     3.397    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/D[0]
    SLICE_X92Y149        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.821     2.269    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X92Y149        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.448ns  (logic 0.059ns (13.163%)  route 0.389ns (86.837%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.720ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.280ns
    Source Clock Delay      (SCD):    3.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.315ns (routing 0.484ns, distribution 0.831ns)
  Clock Net Delay (Destination): 1.832ns (routing 0.827ns, distribution 1.005ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.315     3.000    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X85Y134        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y134        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     3.039 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/Q
                         net (fo=204, routed)         0.249     3.288    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]_0[0]
    SLICE_X92Y146        LUT2 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.020     3.308 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][1]_i_1__0/O
                         net (fo=1, routed)           0.140     3.448    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_g[1]
    SLICE_X94Y147        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.832     2.280    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X94Y147        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  RFDAC0_CLK

Max Delay           822 Endpoints
Min Delay           822 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.472ns  (logic 0.652ns (14.578%)  route 3.820ns (85.422%))
  Logic Levels:           6  (LUT3=2 LUT5=3 LUT6=1)
  Clock Path Skew:        -1.615ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.114ns
    Source Clock Delay      (SCD):    4.729ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.215ns (routing 1.037ns, distribution 1.178ns)
  Clock Net Delay (Destination): 2.593ns (routing 1.256ns, distribution 1.337ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.215     4.729    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/c_clk_i
    SLICE_X72Y232        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y232        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     4.809 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[8]/Q
                         net (fo=1, routed)           0.871     5.680    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg[8]
    SLICE_X72Y139        LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.088     5.768 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg_i_3__13/O
                         net (fo=3, routed)           0.238     6.006    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg_i_3__13_n_0
    SLICE_X73Y138        LUT5 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.051     6.057 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/core_en_i_9/O
                         net (fo=4, routed)           0.643     6.700    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]
    SLICE_X77Y170        LUT5 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.123     6.823 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/core_en_i_2/O
                         net (fo=3, routed)           0.154     6.977    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER_n_303
    SLICE_X76Y169        LUT5 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     7.102 r  d_1_i/qick_processor_0/inst/QPROC/core_en/O
                         net (fo=600, routed)         0.742     7.844    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/E[0]
    SLICE_X60Y170        LUT3 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.088     7.932 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[3]_i_2/O
                         net (fo=34, routed)          0.345     8.277    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/time_updt_core
    SLICE_X55Y174        LUT3 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.097     8.374 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[3]_i_1/O
                         net (fo=1, routed)           0.827     9.201    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[6]_0[3]
    SLICE_X75Y175        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.593     3.114    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/t_clk_i
    SLICE_X75Y175        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.397ns  (logic 0.658ns (14.964%)  route 3.739ns (85.036%))
  Logic Levels:           6  (LUT5=3 LUT6=3)
  Clock Path Skew:        -1.619ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.110ns
    Source Clock Delay      (SCD):    4.729ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.215ns (routing 1.037ns, distribution 1.178ns)
  Clock Net Delay (Destination): 2.589ns (routing 1.256ns, distribution 1.333ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.215     4.729    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/c_clk_i
    SLICE_X72Y232        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y232        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     4.809 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[8]/Q
                         net (fo=1, routed)           0.871     5.680    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg[8]
    SLICE_X72Y139        LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.088     5.768 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg_i_3__13/O
                         net (fo=3, routed)           0.238     6.006    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg_i_3__13_n_0
    SLICE_X73Y138        LUT5 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.051     6.057 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/core_en_i_9/O
                         net (fo=4, routed)           0.643     6.700    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]
    SLICE_X77Y170        LUT5 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.123     6.823 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/core_en_i_2/O
                         net (fo=3, routed)           0.154     6.977    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER_n_303
    SLICE_X76Y169        LUT5 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     7.102 r  d_1_i/qick_processor_0/inst/QPROC/core_en/O
                         net (fo=600, routed)         0.571     7.673    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/E[0]
    SLICE_X61Y169        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.039     7.712 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_2/O
                         net (fo=4, routed)           0.518     8.229    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/int_time_pen
    SLICE_X46Y177        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152     8.381 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_1/O
                         net (fo=1, routed)           0.745     9.126    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[6]_0[4]
    SLICE_X77Y175        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.589     3.110    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/t_clk_i
    SLICE_X77Y175        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.016ns  (logic 0.436ns (21.627%)  route 1.580ns (78.373%))
  Logic Levels:           3  (LUT3=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -1.653ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.165ns
    Source Clock Delay      (SCD):    4.818ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.304ns (routing 1.037ns, distribution 1.267ns)
  Clock Net Delay (Destination): 2.644ns (routing 1.256ns, distribution 1.388ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.304     4.818    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/c_clk_i
    SLICE_X81Y153        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y153        FDCE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     4.898 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.807     5.705    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/clr_fifo_req
    SLICE_X80Y149        LUT3 (Prop_C5LUT_SLICEL_I0_O)
                                                      0.110     5.815 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/t_fifo_wave_empty_inferred_i_9/O
                         net (fo=1, routed)           0.131     5.946    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].ADDSUB_MACRO_inst/wave_pop_r_reg[3][0]
    SLICE_X80Y149        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.149     6.095 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].ADDSUB_MACRO_inst/wave_pop_r[3]_i_1/O
                         net (fo=2, routed)           0.050     6.145    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X80Y149        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.097     6.242 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__44/O
                         net (fo=18, routed)          0.592     6.834    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X81Y150        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.644     3.165    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X81Y150        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.016ns  (logic 0.436ns (21.627%)  route 1.580ns (78.373%))
  Logic Levels:           3  (LUT3=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -1.653ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.165ns
    Source Clock Delay      (SCD):    4.818ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.304ns (routing 1.037ns, distribution 1.267ns)
  Clock Net Delay (Destination): 2.644ns (routing 1.256ns, distribution 1.388ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.304     4.818    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/c_clk_i
    SLICE_X81Y153        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y153        FDCE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     4.898 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.807     5.705    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/clr_fifo_req
    SLICE_X80Y149        LUT3 (Prop_C5LUT_SLICEL_I0_O)
                                                      0.110     5.815 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/t_fifo_wave_empty_inferred_i_9/O
                         net (fo=1, routed)           0.131     5.946    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].ADDSUB_MACRO_inst/wave_pop_r_reg[3][0]
    SLICE_X80Y149        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.149     6.095 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].ADDSUB_MACRO_inst/wave_pop_r[3]_i_1/O
                         net (fo=2, routed)           0.050     6.145    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X80Y149        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.097     6.242 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__44/O
                         net (fo=18, routed)          0.592     6.834    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X81Y150        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.644     3.165    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X81Y150        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.999ns  (logic 0.436ns (21.807%)  route 1.563ns (78.193%))
  Logic Levels:           3  (LUT3=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -1.645ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.173ns
    Source Clock Delay      (SCD):    4.818ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.304ns (routing 1.037ns, distribution 1.267ns)
  Clock Net Delay (Destination): 2.652ns (routing 1.256ns, distribution 1.396ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.304     4.818    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/c_clk_i
    SLICE_X81Y153        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y153        FDCE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     4.898 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.807     5.705    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/clr_fifo_req
    SLICE_X80Y149        LUT3 (Prop_C5LUT_SLICEL_I0_O)
                                                      0.110     5.815 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/t_fifo_wave_empty_inferred_i_9/O
                         net (fo=1, routed)           0.131     5.946    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].ADDSUB_MACRO_inst/wave_pop_r_reg[3][0]
    SLICE_X80Y149        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.149     6.095 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].ADDSUB_MACRO_inst/wave_pop_r[3]_i_1/O
                         net (fo=2, routed)           0.050     6.145    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X80Y149        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.097     6.242 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__44/O
                         net (fo=18, routed)          0.575     6.817    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X81Y149        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.652     3.173    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X81Y149        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.998ns  (logic 0.436ns (21.818%)  route 1.562ns (78.182%))
  Logic Levels:           3  (LUT3=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -1.645ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.173ns
    Source Clock Delay      (SCD):    4.818ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.304ns (routing 1.037ns, distribution 1.267ns)
  Clock Net Delay (Destination): 2.652ns (routing 1.256ns, distribution 1.396ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.304     4.818    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/c_clk_i
    SLICE_X81Y153        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y153        FDCE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     4.898 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.807     5.705    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/clr_fifo_req
    SLICE_X80Y149        LUT3 (Prop_C5LUT_SLICEL_I0_O)
                                                      0.110     5.815 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/t_fifo_wave_empty_inferred_i_9/O
                         net (fo=1, routed)           0.131     5.946    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].ADDSUB_MACRO_inst/wave_pop_r_reg[3][0]
    SLICE_X80Y149        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.149     6.095 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].ADDSUB_MACRO_inst/wave_pop_r[3]_i_1/O
                         net (fo=2, routed)           0.050     6.145    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X80Y149        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.097     6.242 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__44/O
                         net (fo=18, routed)          0.574     6.816    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X81Y149        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.652     3.173    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X81Y149        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[5].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[5].wave_fifo_inst/wr_gptr_cdc_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.937ns  (logic 0.079ns (4.078%)  route 1.858ns (95.922%))
  Logic Levels:           0  
  Clock Path Skew:        -1.679ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.063ns
    Source Clock Delay      (SCD):    4.742ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.228ns (routing 1.037ns, distribution 1.191ns)
  Clock Net Delay (Destination): 2.542ns (routing 1.256ns, distribution 1.286ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.228     4.742    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[5].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X74Y191        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[5].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y191        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.821 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[5].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/Q
                         net (fo=4, routed)           1.858     6.679    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[5].wave_fifo_inst/wr_gptr[8]
    SLICE_X73Y215        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[5].wave_fifo_inst/wr_gptr_cdc_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.542     3.063    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[5].wave_fifo_inst/t_clk_i
    SLICE_X73Y215        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[5].wave_fifo_inst/wr_gptr_cdc_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.915ns  (logic 0.491ns (25.637%)  route 1.424ns (74.363%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -1.641ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.084ns
    Source Clock Delay      (SCD):    4.725ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.211ns (routing 1.037ns, distribution 1.174ns)
  Clock Net Delay (Destination): 2.563ns (routing 1.256ns, distribution 1.307ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.211     4.725    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/c_clk_i
    SLICE_X73Y216        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y216        FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     4.805 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.261     5.066    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req
    SLICE_X73Y216        LUT3 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.157     5.223 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/t_fifo_trig_empty_inferred_i_14/O
                         net (fo=1, routed)           0.456     5.679    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X69Y237        LUT5 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     5.718 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[0]_i_2/O
                         net (fo=1, routed)           0.199     5.917    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r_reg[0]
    SLICE_X71Y236        LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.124     6.041 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r[0]_i_1/O
                         net (fo=2, routed)           0.195     6.236    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop
    SLICE_X72Y233        LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.091     6.327 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1/O
                         net (fo=18, routed)          0.314     6.640    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X70Y233        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.563     3.084    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X70Y233        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[6]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.915ns  (logic 0.491ns (25.637%)  route 1.424ns (74.363%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -1.641ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.084ns
    Source Clock Delay      (SCD):    4.725ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.211ns (routing 1.037ns, distribution 1.174ns)
  Clock Net Delay (Destination): 2.563ns (routing 1.256ns, distribution 1.307ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.211     4.725    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/c_clk_i
    SLICE_X73Y216        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y216        FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     4.805 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.261     5.066    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req
    SLICE_X73Y216        LUT3 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.157     5.223 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/t_fifo_trig_empty_inferred_i_14/O
                         net (fo=1, routed)           0.456     5.679    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X69Y237        LUT5 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     5.718 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[0]_i_2/O
                         net (fo=1, routed)           0.199     5.917    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r_reg[0]
    SLICE_X71Y236        LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.124     6.041 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r[0]_i_1/O
                         net (fo=2, routed)           0.195     6.236    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop
    SLICE_X72Y233        LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.091     6.327 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1/O
                         net (fo=18, routed)          0.314     6.640    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X70Y233        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[6]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.563     3.084    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X70Y233        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[7]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.915ns  (logic 0.491ns (25.637%)  route 1.424ns (74.363%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -1.641ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.084ns
    Source Clock Delay      (SCD):    4.725ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.211ns (routing 1.037ns, distribution 1.174ns)
  Clock Net Delay (Destination): 2.563ns (routing 1.256ns, distribution 1.307ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.211     4.725    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/c_clk_i
    SLICE_X73Y216        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y216        FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     4.805 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.261     5.066    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req
    SLICE_X73Y216        LUT3 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.157     5.223 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/t_fifo_trig_empty_inferred_i_14/O
                         net (fo=1, routed)           0.456     5.679    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X69Y237        LUT5 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     5.718 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[0]_i_2/O
                         net (fo=1, routed)           0.199     5.917    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r_reg[0]
    SLICE_X71Y236        LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.124     6.041 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r[0]_i_1/O
                         net (fo=2, routed)           0.195     6.236    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop
    SLICE_X72Y233        LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.091     6.327 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1/O
                         net (fo=18, routed)          0.314     6.640    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X70Y233        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[7]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.563     3.084    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X70Y233        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[7]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/wr_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.077ns  (logic 0.039ns (50.859%)  route 0.038ns (49.141%))
  Logic Levels:           0  
  Clock Path Skew:        -0.705ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.204ns
    Source Clock Delay      (SCD):    2.910ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.224ns (routing 0.571ns, distribution 0.653ns)
  Clock Net Delay (Destination): 1.756ns (routing 0.827ns, distribution 0.929ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.224     2.910    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X74Y149        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y149        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     2.949 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/Q
                         net (fo=2, routed)           0.038     2.986    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/wr_gptr[2]
    SLICE_X74Y148        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/wr_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.756     2.204    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/t_clk_i
    SLICE_X74Y148        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/wr_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/wr_gptr_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.093ns  (logic 0.039ns (42.079%)  route 0.054ns (57.921%))
  Logic Levels:           0  
  Clock Path Skew:        -0.713ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.200ns
    Source Clock Delay      (SCD):    2.913ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.227ns (routing 0.571ns, distribution 0.656ns)
  Clock Net Delay (Destination): 1.752ns (routing 0.827ns, distribution 0.925ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.227     2.913    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X77Y143        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y143        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     2.952 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/Q
                         net (fo=2, routed)           0.054     3.006    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/wr_gptr[1]
    SLICE_X77Y143        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/wr_gptr_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.752     2.200    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/t_clk_i
    SLICE_X77Y143        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/wr_gptr_cdc_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/wr_gptr_cdc_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.096ns  (logic 0.039ns (40.760%)  route 0.057ns (59.240%))
  Logic Levels:           0  
  Clock Path Skew:        -0.713ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.199ns
    Source Clock Delay      (SCD):    2.912ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.226ns (routing 0.571ns, distribution 0.655ns)
  Clock Net Delay (Destination): 1.751ns (routing 0.827ns, distribution 0.924ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.226     2.912    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X77Y144        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y144        FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     2.951 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/Q
                         net (fo=2, routed)           0.057     3.008    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/wr_gptr[8]
    SLICE_X77Y144        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/wr_gptr_cdc_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.751     2.199    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/t_clk_i
    SLICE_X77Y144        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/wr_gptr_cdc_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/wr_gptr_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.218%)  route 0.060ns (60.782%))
  Logic Levels:           0  
  Clock Path Skew:        -0.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.200ns
    Source Clock Delay      (SCD):    2.910ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.224ns (routing 0.571ns, distribution 0.653ns)
  Clock Net Delay (Destination): 1.752ns (routing 0.827ns, distribution 0.925ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.224     2.910    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X74Y149        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y149        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.949 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/Q
                         net (fo=2, routed)           0.060     3.009    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/wr_gptr[1]
    SLICE_X74Y148        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/wr_gptr_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.752     2.200    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/t_clk_i
    SLICE_X74Y148        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/wr_gptr_cdc_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.sync_ab_en_inst/a_pulse_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.sync_ab_en_inst/pulse_req_cdc_reg/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.041ns (40.841%)  route 0.059ns (59.159%))
  Logic Levels:           0  
  Clock Path Skew:        -0.725ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.189ns
    Source Clock Delay      (SCD):    2.914ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.228ns (routing 0.571ns, distribution 0.657ns)
  Clock Net Delay (Destination): 1.741ns (routing 0.827ns, distribution 0.914ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.228     2.914    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.sync_ab_en_inst/c_clk_i
    SLICE_X73Y155        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.sync_ab_en_inst/a_pulse_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y155        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     2.955 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.sync_ab_en_inst/a_pulse_req_reg/Q
                         net (fo=2, routed)           0.059     3.014    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.sync_ab_en_inst/a_pulse_req
    SLICE_X73Y154        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.sync_ab_en_inst/pulse_req_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.741     2.189    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.sync_ab_en_inst/t_clk_i
    SLICE_X73Y154        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.sync_ab_en_inst/pulse_req_cdc_reg/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/wr_gptr_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.104ns  (logic 0.038ns (36.383%)  route 0.066ns (63.617%))
  Logic Levels:           0  
  Clock Path Skew:        -0.735ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.178ns
    Source Clock Delay      (SCD):    2.913ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.227ns (routing 0.571ns, distribution 0.656ns)
  Clock Net Delay (Destination): 1.730ns (routing 0.827ns, distribution 0.903ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.227     2.913    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X67Y194        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y194        FDCE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     2.951 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/Q
                         net (fo=2, routed)           0.066     3.017    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/wr_gptr[7]
    SLICE_X67Y195        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/wr_gptr_cdc_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.730     2.178    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/t_clk_i
    SLICE_X67Y195        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/wr_gptr_cdc_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/wr_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.925%)  route 0.059ns (60.075%))
  Logic Levels:           0  
  Clock Path Skew:        -0.712ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.208ns
    Source Clock Delay      (SCD):    2.921ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.235ns (routing 0.571ns, distribution 0.664ns)
  Clock Net Delay (Destination): 1.760ns (routing 0.827ns, distribution 0.933ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.235     2.921    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X74Y170        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y170        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     2.960 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/Q
                         net (fo=2, routed)           0.059     3.018    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/wr_gptr[2]
    SLICE_X74Y169        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/wr_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.760     2.208    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/t_clk_i
    SLICE_X74Y169        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/wr_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/wr_gptr_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.925%)  route 0.059ns (60.075%))
  Logic Levels:           0  
  Clock Path Skew:        -0.716ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.204ns
    Source Clock Delay      (SCD):    2.921ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.235ns (routing 0.571ns, distribution 0.664ns)
  Clock Net Delay (Destination): 1.756ns (routing 0.827ns, distribution 0.929ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.235     2.921    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X74Y170        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y170        FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     2.960 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/Q
                         net (fo=2, routed)           0.059     3.018    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/wr_gptr[3]
    SLICE_X74Y169        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/wr_gptr_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.756     2.204    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/t_clk_i
    SLICE_X74Y169        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/wr_gptr_cdc_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/wr_gptr_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.925%)  route 0.059ns (60.075%))
  Logic Levels:           0  
  Clock Path Skew:        -0.730ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.195ns
    Source Clock Delay      (SCD):    2.925ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.239ns (routing 0.571ns, distribution 0.668ns)
  Clock Net Delay (Destination): 1.747ns (routing 0.827ns, distribution 0.920ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.239     2.925    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X68Y163        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y163        FDCE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     2.964 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/Q
                         net (fo=2, routed)           0.059     3.023    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/wr_gptr[3]
    SLICE_X68Y162        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/wr_gptr_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.747     2.195    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/t_clk_i
    SLICE_X68Y162        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/wr_gptr_cdc_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/wr_gptr_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.039ns (38.817%)  route 0.061ns (61.183%))
  Logic Levels:           0  
  Clock Path Skew:        -0.716ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.208ns
    Source Clock Delay      (SCD):    2.924ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.238ns (routing 0.571ns, distribution 0.667ns)
  Clock Net Delay (Destination): 1.760ns (routing 0.827ns, distribution 0.933ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.238     2.924    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X74Y171        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y171        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     2.963 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/Q
                         net (fo=2, routed)           0.061     3.025    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/wr_gptr[1]
    SLICE_X74Y169        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/wr_gptr_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.760     2.208    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/t_clk_i
    SLICE_X74Y169        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/wr_gptr_cdc_reg[1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  RFDAC0_CLK

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.186ns  (logic 0.079ns (6.661%)  route 1.107ns (93.339%))
  Logic Levels:           0  
  Clock Path Skew:        0.741ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.373ns
    Source Clock Delay      (SCD):    2.632ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.406ns (routing 0.662ns, distribution 1.744ns)
  Clock Net Delay (Destination): 2.852ns (routing 1.256ns, distribution 1.596ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.406     2.632    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X114Y157       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X114Y157       FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.711 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/Q
                         net (fo=1, routed)           1.107     3.818    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/src_in
    SLICE_X116Y248       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.852     3.373    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/dest_clk
    SLICE_X116Y248       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.735ns  (logic 0.078ns (10.612%)  route 0.657ns (89.388%))
  Logic Levels:           0  
  Clock Path Skew:        0.647ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.306ns
    Source Clock Delay      (SCD):    2.659ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.433ns (routing 0.662ns, distribution 1.771ns)
  Clock Net Delay (Destination): 2.785ns (routing 1.256ns, distribution 1.529ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.433     2.659    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X115Y165       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X115Y165       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.737 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/Q
                         net (fo=1, routed)           0.657     3.394    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/src_in
    SLICE_X118Y215       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.785     3.306    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/dest_clk
    SLICE_X118Y215       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.355ns  (logic 0.039ns (10.986%)  route 0.316ns (89.014%))
  Logic Levels:           0  
  Clock Path Skew:        0.884ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.334ns
    Source Clock Delay      (SCD):    1.450ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.330ns (routing 0.359ns, distribution 0.971ns)
  Clock Net Delay (Destination): 1.886ns (routing 0.827ns, distribution 1.059ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.330     1.450    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X115Y165       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X115Y165       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/Q
                         net (fo=1, routed)           0.316     1.805    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/src_in
    SLICE_X118Y215       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.886     2.334    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/dest_clk
    SLICE_X118Y215       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.593ns  (logic 0.039ns (6.577%)  route 0.554ns (93.423%))
  Logic Levels:           0  
  Clock Path Skew:        0.940ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.380ns
    Source Clock Delay      (SCD):    1.440ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.320ns (routing 0.359ns, distribution 0.961ns)
  Clock Net Delay (Destination): 1.932ns (routing 0.827ns, distribution 1.105ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.320     1.440    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X114Y157       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X114Y157       FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.479 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/Q
                         net (fo=1, routed)           0.554     2.033    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/src_in
    SLICE_X116Y248       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.932     2.380    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/dest_clk
    SLICE_X116Y248       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.767ns  (logic 0.051ns (1.354%)  route 3.716ns (98.646%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 2.051ns (routing 0.798ns, distribution 1.253ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           2.118     2.118    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X72Y287        LUT1 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.051     2.169 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           1.598     3.767    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X76Y115        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.051     5.001    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X76Y115        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.842ns  (logic 0.022ns (1.194%)  route 1.820ns (98.806%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 1.430ns (routing 0.537ns, distribution 0.893ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           1.017     1.017    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X72Y287        LUT1 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.022     1.039 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.803     1.842    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X76Y115        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.430     2.819    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X76Y115        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay           349 Endpoints
Min Delay           349 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.971ns  (logic 0.078ns (8.031%)  route 0.893ns (91.969%))
  Logic Levels:           0  
  Clock Path Skew:        1.429ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.960ns
    Source Clock Delay      (SCD):    3.531ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.858ns (routing 1.381ns, distribution 1.477ns)
  Clock Net Delay (Destination): 2.010ns (routing 0.798ns, distribution 1.212ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.858     3.531    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X69Y238        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y238        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     3.609 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/Q
                         net (fo=2, routed)           0.893     4.502    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X70Y163        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.010     4.960    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X70Y163        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.875ns  (logic 0.079ns (9.026%)  route 0.796ns (90.974%))
  Logic Levels:           0  
  Clock Path Skew:        1.462ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.948ns
    Source Clock Delay      (SCD):    3.486ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.813ns (routing 1.381ns, distribution 1.432ns)
  Clock Net Delay (Destination): 1.998ns (routing 0.798ns, distribution 1.200ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.813     3.486    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X73Y211        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y211        FDCE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.565 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/Q
                         net (fo=2, routed)           0.796     4.361    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X73Y145        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.998     4.948    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X73Y145        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.797ns  (logic 0.078ns (9.783%)  route 0.719ns (90.217%))
  Logic Levels:           0  
  Clock Path Skew:        1.421ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.964ns
    Source Clock Delay      (SCD):    3.543ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.870ns (routing 1.381ns, distribution 1.489ns)
  Clock Net Delay (Destination): 2.014ns (routing 0.798ns, distribution 1.216ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.870     3.543    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X70Y159        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y159        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     3.621 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/Q
                         net (fo=2, routed)           0.719     4.340    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/trigger
    SLICE_X74Y120        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.014     4.964    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X74Y120        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.482ns  (logic 0.078ns (16.173%)  route 0.404ns (83.827%))
  Logic Levels:           0  
  Clock Path Skew:        1.421ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.974ns
    Source Clock Delay      (SCD):    3.553ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.880ns (routing 1.381ns, distribution 1.499ns)
  Clock Net Delay (Destination): 2.024ns (routing 0.798ns, distribution 1.226ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.880     3.553    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y140        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y140        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     3.631 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/Q
                         net (fo=2, routed)           0.404     4.035    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X72Y135        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.024     4.974    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X72Y135        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.404ns  (logic 0.078ns (19.293%)  route 0.326ns (80.707%))
  Logic Levels:           0  
  Clock Path Skew:        1.433ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.986ns
    Source Clock Delay      (SCD):    3.553ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.880ns (routing 1.381ns, distribution 1.499ns)
  Clock Net Delay (Destination): 2.036ns (routing 0.798ns, distribution 1.238ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.880     3.553    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y140        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y140        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     3.631 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[13]/Q
                         net (fo=2, routed)           0.326     3.957    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X76Y136        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.036     4.986    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X76Y136        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.368ns  (logic 0.167ns (12.204%)  route 1.201ns (87.796%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        1.385ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.061ns
    Source Clock Delay      (SCD):    3.676ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.003ns (routing 1.381ns, distribution 1.622ns)
  Clock Net Delay (Destination): 2.111ns (routing 0.798ns, distribution 1.313ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.003     3.676    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X93Y167        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y167        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     3.755 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[0]/Q
                         net (fo=557, routed)         0.973     4.728    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]_0[0]
    SLICE_X81Y129        LUT2 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.088     4.816 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg[0][0]_i_1/O
                         net (fo=2, routed)           0.228     5.044    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/wptr_reg[0][0]
    SLICE_X81Y129        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.111     5.061    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X81Y129        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_490_503/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[491]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.263ns  (logic 0.305ns (24.149%)  route 0.958ns (75.851%))
  Logic Levels:           0  
  Clock Path Skew:        1.255ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.982ns
    Source Clock Delay      (SCD):    3.727ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.054ns (routing 1.381ns, distribution 1.673ns)
  Clock Net Delay (Destination): 2.032ns (routing 0.798ns, distribution 1.234ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.054     3.727    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_490_503/WCLK
    SLICE_X90Y137        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_490_503/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y137        RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.305     4.032 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_490_503/RAMA_D1/O
                         net (fo=1, routed)           0.958     4.990    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[491]
    SLICE_X78Y137        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[491]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.032     4.982    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X78Y137        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[491]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_490_503/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[490]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.175ns  (logic 0.289ns (24.596%)  route 0.886ns (75.404%))
  Logic Levels:           0  
  Clock Path Skew:        1.255ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.982ns
    Source Clock Delay      (SCD):    3.727ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.054ns (routing 1.381ns, distribution 1.673ns)
  Clock Net Delay (Destination): 2.032ns (routing 0.798ns, distribution 1.234ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.054     3.727    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_490_503/WCLK
    SLICE_X90Y137        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_490_503/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y137        RAMD32 (Prop_A5LUT_SLICEM_CLK_O)
                                                      0.289     4.016 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_490_503/RAMA/O
                         net (fo=1, routed)           0.886     4.902    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[490]
    SLICE_X78Y137        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[490]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.032     4.982    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X78Y137        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[490]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.168ns  (logic 0.177ns (15.155%)  route 0.991ns (84.845%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        1.425ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.061ns
    Source Clock Delay      (SCD):    3.636ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.963ns (routing 1.381ns, distribution 1.582ns)
  Clock Net Delay (Destination): 2.111ns (routing 0.798ns, distribution 1.313ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.963     3.636    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X81Y129        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y129        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     3.717 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/Q
                         net (fo=556, routed)         0.976     4.693    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]_0[3]
    SLICE_X81Y129        LUT2 (Prop_H5LUT_SLICEL_I1_O)
                                                      0.096     4.789 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg[0][2]_i_1/O
                         net (fo=1, routed)           0.015     4.804    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/wptr_g[2]
    SLICE_X81Y129        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.111     5.061    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X81Y129        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_462_475/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[470]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.105ns  (logic 0.288ns (26.063%)  route 0.817ns (73.937%))
  Logic Levels:           0  
  Clock Path Skew:        1.289ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.977ns
    Source Clock Delay      (SCD):    3.688ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.015ns (routing 1.381ns, distribution 1.634ns)
  Clock Net Delay (Destination): 2.027ns (routing 0.798ns, distribution 1.229ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.015     3.688    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_462_475/WCLK
    SLICE_X83Y131        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_462_475/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y131        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.288     3.976 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_462_475/RAME/O
                         net (fo=1, routed)           0.817     4.793    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[470]
    SLICE_X79Y138        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[470]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.027     4.977    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X79Y138        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[470]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.177ns  (logic 0.038ns (21.458%)  route 0.139ns (78.542%))
  Logic Levels:           0  
  Clock Path Skew:        0.877ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.802ns
    Source Clock Delay      (SCD):    1.925ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.576ns (routing 0.748ns, distribution 0.828ns)
  Clock Net Delay (Destination): 1.413ns (routing 0.537ns, distribution 0.876ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.576     1.925    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y140        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y140        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     1.963 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[13]/Q
                         net (fo=2, routed)           0.139     2.102    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X76Y136        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.413     2.802    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X76Y136        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.222ns  (logic 0.039ns (17.560%)  route 0.183ns (82.440%))
  Logic Levels:           0  
  Clock Path Skew:        0.869ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.793ns
    Source Clock Delay      (SCD):    1.925ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.576ns (routing 0.748ns, distribution 0.828ns)
  Clock Net Delay (Destination): 1.404ns (routing 0.537ns, distribution 0.867ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.576     1.925    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y140        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y140        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.964 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/Q
                         net (fo=2, routed)           0.183     2.147    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X72Y135        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.404     2.793    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X72Y135        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.386ns  (logic 0.039ns (10.101%)  route 0.347ns (89.899%))
  Logic Levels:           0  
  Clock Path Skew:        0.866ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.781ns
    Source Clock Delay      (SCD):    1.915ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.566ns (routing 0.748ns, distribution 0.818ns)
  Clock Net Delay (Destination): 1.392ns (routing 0.537ns, distribution 0.855ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.566     1.915    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X70Y159        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y159        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.954 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/Q
                         net (fo=2, routed)           0.347     2.301    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/trigger
    SLICE_X74Y120        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.392     2.781    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X74Y120        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.426ns  (logic 0.039ns (9.153%)  route 0.387ns (90.847%))
  Logic Levels:           0  
  Clock Path Skew:        0.884ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.774ns
    Source Clock Delay      (SCD):    1.890ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.541ns (routing 0.748ns, distribution 0.793ns)
  Clock Net Delay (Destination): 1.385ns (routing 0.537ns, distribution 0.848ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.541     1.890    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X73Y211        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y211        FDCE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.929 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/Q
                         net (fo=2, routed)           0.387     2.316    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X73Y145        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.385     2.774    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X73Y145        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.474ns  (logic 0.039ns (8.226%)  route 0.435ns (91.774%))
  Logic Levels:           0  
  Clock Path Skew:        0.875ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.782ns
    Source Clock Delay      (SCD):    1.907ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.558ns (routing 0.748ns, distribution 0.810ns)
  Clock Net Delay (Destination): 1.393ns (routing 0.537ns, distribution 0.856ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.558     1.907    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X69Y238        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y238        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.946 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/Q
                         net (fo=2, routed)           0.435     2.381    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X70Y163        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.393     2.782    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X70Y163        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.168ns  (logic 0.099ns (58.762%)  route 0.069ns (41.238%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.879ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.852ns
    Source Clock Delay      (SCD):    1.973ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.624ns (routing 0.748ns, distribution 0.876ns)
  Clock Net Delay (Destination): 1.463ns (routing 0.537ns, distribution 0.926ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.624     1.973    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X81Y129        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y129        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     2.014 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[2]/Q
                         net (fo=557, routed)         0.063     2.077    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]_0[2]
    SLICE_X81Y129        LUT2 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.058     2.135 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg[0][2]_i_1/O
                         net (fo=1, routed)           0.006     2.141    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/wptr_g[2]
    SLICE_X81Y129        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.463     2.852    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X81Y129        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_504_517/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[509]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.183ns  (logic 0.110ns (60.109%)  route 0.073ns (39.891%))
  Logic Levels:           0  
  Clock Path Skew:        0.864ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.863ns
    Source Clock Delay      (SCD):    1.999ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.650ns (routing 0.748ns, distribution 0.902ns)
  Clock Net Delay (Destination): 1.474ns (routing 0.537ns, distribution 0.937ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.650     1.999    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_504_517/WCLK
    SLICE_X86Y154        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_504_517/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y154        RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.110     2.109 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_504_517/RAMC_D1/O
                         net (fo=1, routed)           0.073     2.182    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[509]
    SLICE_X86Y153        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[509]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.474     2.863    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X86Y153        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[509]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_504_517/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[517]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.186ns  (logic 0.105ns (56.452%)  route 0.081ns (43.548%))
  Logic Levels:           0  
  Clock Path Skew:        0.862ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.861ns
    Source Clock Delay      (SCD):    1.999ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.650ns (routing 0.748ns, distribution 0.902ns)
  Clock Net Delay (Destination): 1.472ns (routing 0.537ns, distribution 0.935ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.650     1.999    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_504_517/WCLK
    SLICE_X86Y154        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_504_517/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y154        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.105     2.104 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_504_517/RAMG_D1/O
                         net (fo=1, routed)           0.081     2.185    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[517]
    SLICE_X86Y153        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[517]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.472     2.861    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X86Y153        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[517]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_532_545/RAMG/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[544]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.188ns  (logic 0.105ns (55.851%)  route 0.083ns (44.149%))
  Logic Levels:           0  
  Clock Path Skew:        0.860ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.860ns
    Source Clock Delay      (SCD):    2.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.651ns (routing 0.748ns, distribution 0.903ns)
  Clock Net Delay (Destination): 1.471ns (routing 0.537ns, distribution 0.934ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.651     2.000    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_532_545/WCLK
    SLICE_X87Y154        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_532_545/RAMG/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y154        RAMD32 (Prop_G5LUT_SLICEM_CLK_O)
                                                      0.105     2.105 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_532_545/RAMG/O
                         net (fo=1, routed)           0.083     2.188    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[544]
    SLICE_X88Y154        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[544]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.471     2.860    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X88Y154        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[544]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_210_223/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[223]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.183ns  (logic 0.105ns (57.377%)  route 0.078ns (42.623%))
  Logic Levels:           0  
  Clock Path Skew:        0.866ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.872ns
    Source Clock Delay      (SCD):    2.006ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.657ns (routing 0.748ns, distribution 0.909ns)
  Clock Net Delay (Destination): 1.483ns (routing 0.537ns, distribution 0.946ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.657     2.006    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_210_223/WCLK
    SLICE_X93Y147        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_210_223/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y147        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.105     2.111 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_210_223/RAMG_D1/O
                         net (fo=1, routed)           0.078     2.189    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[223]
    SLICE_X94Y147        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[223]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.483     2.872    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X94Y147        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[223]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay           750 Endpoints
Min Delay           750 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.599ns  (logic 0.079ns (13.189%)  route 0.520ns (86.811%))
  Logic Levels:           0  
  Clock Path Skew:        2.583ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.189ns
    Source Clock Delay      (SCD):    2.606ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.380ns (routing 0.662ns, distribution 1.718ns)
  Clock Net Delay (Destination): 2.239ns (routing 0.798ns, distribution 1.441ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.380     2.606    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X105Y108       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y108       FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     2.685 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/Q
                         net (fo=1, routed)           0.520     3.205    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/src_in
    SLICE_X105Y79        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.239     5.189    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/dest_clk
    SLICE_X105Y79        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc2_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.543ns  (logic 0.079ns (14.549%)  route 0.464ns (85.451%))
  Logic Levels:           0  
  Clock Path Skew:        2.536ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.170ns
    Source Clock Delay      (SCD):    2.634ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.408ns (routing 0.662ns, distribution 1.746ns)
  Clock Net Delay (Destination): 2.220ns (routing 0.798ns, distribution 1.422ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.408     2.634    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X111Y137       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc2_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y137       FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.713 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc2_done_i_reg/Q
                         net (fo=1, routed)           0.464     3.177    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/src_in
    SLICE_X106Y137       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.220     5.170    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/dest_clk
    SLICE_X106Y137       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.450ns  (logic 0.079ns (17.559%)  route 0.371ns (82.441%))
  Logic Levels:           0  
  Clock Path Skew:        2.562ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.965ns
    Source Clock Delay      (SCD):    2.403ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.177ns (routing 0.662ns, distribution 1.515ns)
  Clock Net Delay (Destination): 2.015ns (routing 0.798ns, distribution 1.217ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.177     2.403    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X74Y90         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y90         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.482 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.371     2.853    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X75Y89         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.015     4.965    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X75Y89         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.355ns  (logic 0.079ns (22.229%)  route 0.276ns (77.771%))
  Logic Levels:           0  
  Clock Path Skew:        2.543ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.968ns
    Source Clock Delay      (SCD):    2.425ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.199ns (routing 0.662ns, distribution 1.537ns)
  Clock Net Delay (Destination): 2.018ns (routing 0.798ns, distribution 1.220ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.199     2.425    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X73Y97         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y97         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.504 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.276     2.780    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X73Y103        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.018     4.968    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X73Y103        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]_replica_2/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.937ns  (logic 0.178ns (9.188%)  route 1.759ns (90.812%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        2.698ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.070ns
    Source Clock Delay      (SCD):    2.372ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.146ns (routing 0.662ns, distribution 1.484ns)
  Clock Net Delay (Destination): 2.120ns (routing 0.798ns, distribution 1.322ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.146     2.372    d_1_i/axis_avg_buffer_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X63Y115        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y115        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     2.451 r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[3]/Q
                         net (fo=2, routed)           0.887     3.338    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[3]
    SLICE_X62Y96         LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.099     3.437 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[3]_i_1/O
                         net (fo=9, routed)           0.872     4.309    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in[3]
    SLICE_X54Y50         FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]_replica_2/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.120     5.070    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X54Y50         FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]_replica_2/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]_replica_1/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.900ns  (logic 0.178ns (9.367%)  route 1.722ns (90.633%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        2.633ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.005ns
    Source Clock Delay      (SCD):    2.372ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.146ns (routing 0.662ns, distribution 1.484ns)
  Clock Net Delay (Destination): 2.055ns (routing 0.798ns, distribution 1.257ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.146     2.372    d_1_i/axis_avg_buffer_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X63Y115        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y115        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     2.451 r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[3]/Q
                         net (fo=2, routed)           0.887     3.338    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[3]
    SLICE_X62Y96         LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.099     3.437 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[3]_i_1/O
                         net (fo=9, routed)           0.835     4.272    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in[3]
    SLICE_X64Y50         FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]_replica_1/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.055     5.005    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X64Y50         FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]_replica_1/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_1/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.843ns  (logic 0.214ns (11.614%)  route 1.629ns (88.386%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        2.736ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.108ns
    Source Clock Delay      (SCD):    2.372ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.146ns (routing 0.662ns, distribution 1.484ns)
  Clock Net Delay (Destination): 2.158ns (routing 0.798ns, distribution 1.360ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.146     2.372    d_1_i/axis_avg_buffer_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X63Y115        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y115        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     2.451 r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[1]/Q
                         net (fo=2, routed)           0.569     3.020    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[1]
    SLICE_X62Y96         LUT4 (Prop_G5LUT_SLICEL_I0_O)
                                                      0.135     3.155 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[1]_i_1/O
                         net (fo=9, routed)           1.060     4.215    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in[1]
    SLICE_X44Y46         FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_1/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.158     5.108    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X44Y46         FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_1/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]_replica_4/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.837ns  (logic 0.178ns (9.691%)  route 1.659ns (90.309%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        2.680ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.052ns
    Source Clock Delay      (SCD):    2.372ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.146ns (routing 0.662ns, distribution 1.484ns)
  Clock Net Delay (Destination): 2.102ns (routing 0.798ns, distribution 1.304ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.146     2.372    d_1_i/axis_avg_buffer_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X63Y115        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y115        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     2.451 r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[3]/Q
                         net (fo=2, routed)           0.887     3.338    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[3]
    SLICE_X62Y96         LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.099     3.437 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[3]_i_1/O
                         net (fo=9, routed)           0.772     4.209    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in[3]
    SLICE_X56Y64         FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]_replica_4/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.102     5.052    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X56Y64         FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]_replica_4/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]_replica_3/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.801ns  (logic 0.178ns (9.884%)  route 1.623ns (90.116%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        2.617ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.989ns
    Source Clock Delay      (SCD):    2.372ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.146ns (routing 0.662ns, distribution 1.484ns)
  Clock Net Delay (Destination): 2.039ns (routing 0.798ns, distribution 1.241ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.146     2.372    d_1_i/axis_avg_buffer_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X63Y115        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y115        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     2.451 r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[3]/Q
                         net (fo=2, routed)           0.887     3.338    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[3]
    SLICE_X62Y96         LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.099     3.437 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[3]_i_1/O
                         net (fo=9, routed)           0.736     4.173    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in[3]
    SLICE_X63Y60         FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]_replica_3/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.039     4.989    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X63Y60         FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]_replica_3/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[11]_replica_1/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.689ns  (logic 0.202ns (11.961%)  route 1.487ns (88.039%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        2.631ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.070ns
    Source Clock Delay      (SCD):    2.439ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.213ns (routing 0.662ns, distribution 1.551ns)
  Clock Net Delay (Destination): 2.120ns (routing 0.798ns, distribution 1.322ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.213     2.439    d_1_i/axis_avg_buffer_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X72Y111        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y111        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     2.519 r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[11]/Q
                         net (fo=2, routed)           0.803     3.322    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[11]
    SLICE_X61Y85         LUT4 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.122     3.444 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[11]_i_1__0/O
                         net (fo=5, routed)           0.684     4.128    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in[11]
    SLICE_X54Y50         FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[11]_replica_1/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.120     5.070    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X54Y50         FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[11]_replica_1/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.156ns  (logic 0.039ns (25.066%)  route 0.117ns (74.934%))
  Logic Levels:           0  
  Clock Path Skew:        1.468ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.791ns
    Source Clock Delay      (SCD):    1.323ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.203ns (routing 0.359ns, distribution 0.844ns)
  Clock Net Delay (Destination): 1.402ns (routing 0.537ns, distribution 0.865ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.203     1.323    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X73Y97         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y97         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.362 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.117     1.478    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X73Y103        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.402     2.791    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X73Y103        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.164ns  (logic 0.039ns (23.780%)  route 0.125ns (76.219%))
  Logic Levels:           0  
  Clock Path Skew:        1.474ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.796ns
    Source Clock Delay      (SCD):    1.322ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.202ns (routing 0.359ns, distribution 0.843ns)
  Clock Net Delay (Destination): 1.407ns (routing 0.537ns, distribution 0.870ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.202     1.322    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X73Y103        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y103        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.361 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/Q
                         net (fo=1, routed)           0.125     1.486    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[0]
    SLICE_X73Y105        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.407     2.796    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X73Y105        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.172ns  (logic 0.039ns (22.674%)  route 0.133ns (77.326%))
  Logic Levels:           0  
  Clock Path Skew:        1.470ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.797ns
    Source Clock Delay      (SCD):    1.327ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.207ns (routing 0.359ns, distribution 0.848ns)
  Clock Net Delay (Destination): 1.408ns (routing 0.537ns, distribution 0.871ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.207     1.327    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X75Y103        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y103        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     1.366 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/Q
                         net (fo=1, routed)           0.133     1.499    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[3]
    SLICE_X74Y105        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.408     2.797    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X74Y105        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.176ns  (logic 0.039ns (22.159%)  route 0.137ns (77.841%))
  Logic Levels:           0  
  Clock Path Skew:        1.468ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.796ns
    Source Clock Delay      (SCD):    1.328ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.208ns (routing 0.359ns, distribution 0.849ns)
  Clock Net Delay (Destination): 1.407ns (routing 0.537ns, distribution 0.870ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.208     1.328    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X75Y103        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y103        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.367 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/Q
                         net (fo=1, routed)           0.137     1.504    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[1]
    SLICE_X73Y105        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.407     2.796    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X73Y105        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.192ns  (logic 0.039ns (20.312%)  route 0.153ns (79.687%))
  Logic Levels:           0  
  Clock Path Skew:        1.471ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.789ns
    Source Clock Delay      (SCD):    1.318ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.198ns (routing 0.359ns, distribution 0.839ns)
  Clock Net Delay (Destination): 1.400ns (routing 0.537ns, distribution 0.863ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.198     1.318    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X75Y89         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y89         FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     1.357 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/Q
                         net (fo=1, routed)           0.153     1.510    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[4]
    SLICE_X75Y90         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.400     2.789    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X75Y90         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.196ns  (logic 0.039ns (19.906%)  route 0.157ns (80.094%))
  Logic Levels:           0  
  Clock Path Skew:        1.478ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.794ns
    Source Clock Delay      (SCD):    1.316ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.196ns (routing 0.359ns, distribution 0.837ns)
  Clock Net Delay (Destination): 1.405ns (routing 0.537ns, distribution 0.868ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.196     1.316    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X74Y90         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y90         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.355 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.157     1.511    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X75Y89         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.405     2.794    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X75Y89         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.191ns  (logic 0.039ns (20.419%)  route 0.152ns (79.581%))
  Logic Levels:           0  
  Clock Path Skew:        1.470ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.797ns
    Source Clock Delay      (SCD):    1.327ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.207ns (routing 0.359ns, distribution 0.848ns)
  Clock Net Delay (Destination): 1.408ns (routing 0.537ns, distribution 0.871ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.207     1.327    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X75Y103        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y103        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.366 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/Q
                         net (fo=1, routed)           0.152     1.518    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[2]
    SLICE_X74Y105        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.408     2.797    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X74Y105        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.208ns  (logic 0.039ns (18.750%)  route 0.169ns (81.250%))
  Logic Levels:           0  
  Clock Path Skew:        1.473ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.789ns
    Source Clock Delay      (SCD):    1.316ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.196ns (routing 0.359ns, distribution 0.837ns)
  Clock Net Delay (Destination): 1.400ns (routing 0.537ns, distribution 0.863ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.196     1.316    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X75Y90         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y90         FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.039     1.355 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/Q
                         net (fo=1, routed)           0.169     1.524    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[2]
    SLICE_X75Y90         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.400     2.789    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X75Y90         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.202ns  (logic 0.040ns (19.802%)  route 0.162ns (80.198%))
  Logic Levels:           0  
  Clock Path Skew:        1.469ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.796ns
    Source Clock Delay      (SCD):    1.327ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.207ns (routing 0.359ns, distribution 0.848ns)
  Clock Net Delay (Destination): 1.407ns (routing 0.537ns, distribution 0.870ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.207     1.327    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X75Y103        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y103        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.040     1.367 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/Q
                         net (fo=1, routed)           0.162     1.529    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[4]
    SLICE_X73Y105        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.407     2.796    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X73Y105        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.221ns  (logic 0.041ns (18.552%)  route 0.180ns (81.448%))
  Logic Levels:           0  
  Clock Path Skew:        1.473ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.789ns
    Source Clock Delay      (SCD):    1.316ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.196ns (routing 0.359ns, distribution 0.837ns)
  Clock Net Delay (Destination): 1.400ns (routing 0.537ns, distribution 0.863ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.196     1.316    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X75Y90         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y90         FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     1.357 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/Q
                         net (fo=1, routed)           0.180     1.537    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[1]
    SLICE_X75Y90         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.400     2.789    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X75Y90         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay             7 Endpoints
Min Delay             7 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.884ns  (logic 0.146ns (16.516%)  route 0.738ns (83.484%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.701ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.054ns
    Source Clock Delay      (SCD):    4.353ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.143ns (routing 0.788ns, distribution 1.355ns)
  Clock Net Delay (Destination): 2.104ns (routing 0.798ns, distribution 1.306ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.143     4.353    d_1_i/ddr4/rst_ddr4/U0/slowest_sync_clk
    SLICE_X62Y223        FDRE                                         r  d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y223        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     4.433 f  d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           0.723     5.156    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X44Y194        LUT1 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.066     5.222 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.015     5.237    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X44Y194        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.104     5.054    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X44Y194        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.240ns  (logic 0.078ns (32.500%)  route 0.162ns (67.500%))
  Logic Levels:           0  
  Clock Path Skew:        0.602ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.058ns
    Source Clock Delay      (SCD):    4.456ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.246ns (routing 0.788ns, distribution 1.458ns)
  Clock Net Delay (Destination): 2.108ns (routing 0.798ns, distribution 1.310ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.246     4.456    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X45Y196        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y196        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     4.534 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=1, routed)           0.162     4.696    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X44Y196        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.108     5.058    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X44Y196        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.389ns  (logic 0.078ns (20.051%)  route 0.311ns (79.949%))
  Logic Levels:           0  
  Clock Path Skew:        0.610ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.049ns
    Source Clock Delay      (SCD):    4.439ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.229ns (routing 0.788ns, distribution 1.441ns)
  Clock Net Delay (Destination): 2.099ns (routing 0.798ns, distribution 1.301ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.229     4.439    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X41Y210        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y210        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     4.517 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.311     4.828    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X41Y210        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.099     5.049    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X41Y210        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.362ns  (logic 0.076ns (20.994%)  route 0.286ns (79.005%))
  Logic Levels:           0  
  Clock Path Skew:        0.611ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.058ns
    Source Clock Delay      (SCD):    4.447ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.237ns (routing 0.788ns, distribution 1.449ns)
  Clock Net Delay (Destination): 2.108ns (routing 0.798ns, distribution 1.310ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.237     4.447    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X41Y207        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y207        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.523 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.286     4.809    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X41Y207        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.108     5.058    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X41Y207        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.368ns  (logic 0.079ns (21.467%)  route 0.289ns (78.533%))
  Logic Levels:           0  
  Clock Path Skew:        0.610ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.049ns
    Source Clock Delay      (SCD):    4.439ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.229ns (routing 0.788ns, distribution 1.441ns)
  Clock Net Delay (Destination): 2.099ns (routing 0.798ns, distribution 1.301ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.229     4.439    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X41Y210        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y210        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     4.518 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.289     4.807    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X41Y210        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.099     5.049    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X41Y210        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.357ns  (logic 0.079ns (22.129%)  route 0.278ns (77.871%))
  Logic Levels:           0  
  Clock Path Skew:        0.611ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.058ns
    Source Clock Delay      (SCD):    4.447ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.237ns (routing 0.788ns, distribution 1.449ns)
  Clock Net Delay (Destination): 2.108ns (routing 0.798ns, distribution 1.310ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.237     4.447    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X41Y207        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y207        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     4.526 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.278     4.804    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0]
    SLICE_X41Y207        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.108     5.058    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X41Y207        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.292ns  (logic 0.078ns (26.712%)  route 0.214ns (73.288%))
  Logic Levels:           0  
  Clock Path Skew:        0.609ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.056ns
    Source Clock Delay      (SCD):    4.447ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.237ns (routing 0.788ns, distribution 1.449ns)
  Clock Net Delay (Destination): 2.106ns (routing 0.798ns, distribution 1.308ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.237     4.447    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X41Y207        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y207        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     4.525 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.214     4.739    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X40Y205        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.106     5.056    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X40Y205        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.394%)  route 0.060ns (60.606%))
  Logic Levels:           0  
  Clock Path Skew:        0.048ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.839ns
    Source Clock Delay      (SCD):    2.792ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.237ns (routing 0.435ns, distribution 0.802ns)
  Clock Net Delay (Destination): 1.450ns (routing 0.537ns, distribution 0.913ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.237     2.792    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X45Y196        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y196        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     2.831 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=1, routed)           0.060     2.891    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X44Y196        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.450     2.839    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X44Y196        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.126ns  (logic 0.039ns (30.952%)  route 0.087ns (69.048%))
  Logic Levels:           0  
  Clock Path Skew:        0.049ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.837ns
    Source Clock Delay      (SCD):    2.788ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.233ns (routing 0.435ns, distribution 0.798ns)
  Clock Net Delay (Destination): 1.448ns (routing 0.537ns, distribution 0.911ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.233     2.788    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X41Y207        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y207        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     2.827 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.087     2.914    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X40Y205        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.448     2.837    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X40Y205        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.151ns  (logic 0.039ns (25.828%)  route 0.112ns (74.172%))
  Logic Levels:           0  
  Clock Path Skew:        0.054ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.842ns
    Source Clock Delay      (SCD):    2.788ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.233ns (routing 0.435ns, distribution 0.798ns)
  Clock Net Delay (Destination): 1.453ns (routing 0.537ns, distribution 0.916ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.233     2.788    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X41Y207        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y207        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.827 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.112     2.939    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0]
    SLICE_X41Y207        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.453     2.842    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X41Y207        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.157ns  (logic 0.039ns (24.841%)  route 0.118ns (75.159%))
  Logic Levels:           0  
  Clock Path Skew:        0.051ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.835ns
    Source Clock Delay      (SCD):    2.784ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.229ns (routing 0.435ns, distribution 0.794ns)
  Clock Net Delay (Destination): 1.446ns (routing 0.537ns, distribution 0.909ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.229     2.784    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X41Y210        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y210        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.823 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.118     2.941    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X41Y210        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.446     2.835    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X41Y210        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.157ns  (logic 0.038ns (24.204%)  route 0.119ns (75.796%))
  Logic Levels:           0  
  Clock Path Skew:        0.054ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.842ns
    Source Clock Delay      (SCD):    2.788ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.233ns (routing 0.435ns, distribution 0.798ns)
  Clock Net Delay (Destination): 1.453ns (routing 0.537ns, distribution 0.916ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.233     2.788    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X41Y207        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y207        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.826 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.119     2.945    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X41Y207        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.453     2.842    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X41Y207        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.169ns  (logic 0.039ns (23.077%)  route 0.130ns (76.923%))
  Logic Levels:           0  
  Clock Path Skew:        0.051ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.835ns
    Source Clock Delay      (SCD):    2.784ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.229ns (routing 0.435ns, distribution 0.794ns)
  Clock Net Delay (Destination): 1.446ns (routing 0.537ns, distribution 0.909ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.229     2.784    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X41Y210        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y210        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     2.823 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.130     2.953    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X41Y210        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.446     2.835    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X41Y210        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.441ns  (logic 0.059ns (13.379%)  route 0.382ns (86.621%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.100ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.836ns
    Source Clock Delay      (SCD):    2.736ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.181ns (routing 0.435ns, distribution 0.746ns)
  Clock Net Delay (Destination): 1.447ns (routing 0.537ns, distribution 0.910ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.181     2.736    d_1_i/ddr4/rst_ddr4/U0/slowest_sync_clk
    SLICE_X62Y223        FDRE                                         r  d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y223        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.775 f  d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           0.376     3.151    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X44Y194        LUT1 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.020     3.171 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.006     3.177    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X44Y194        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.447     2.836    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X44Y194        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.582ns  (logic 0.068ns (2.634%)  route 2.514ns (97.366%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 2.041ns (routing 0.940ns, distribution 1.101ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           2.118     2.118    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X72Y287        LUT1 (Prop_C5LUT_SLICEM_I0_O)
                                                      0.068     2.186 r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.396     2.582    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X73Y306        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.041     5.023    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X73Y306        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.226ns  (logic 0.023ns (1.876%)  route 1.203ns (98.124%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 1.422ns (routing 0.639ns, distribution 0.783ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           1.017     1.017    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X72Y287        LUT1 (Prop_C5LUT_SLICEM_I0_O)
                                                      0.023     1.040 r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.186     1.226    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X73Y306        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.422     2.770    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X73Y306        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay           303 Endpoints
Min Delay           303 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/rd_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.668ns  (logic 0.079ns (4.735%)  route 1.589ns (95.265%))
  Logic Levels:           0  
  Clock Path Skew:        1.401ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.943ns
    Source Clock Delay      (SCD):    3.542ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.869ns (routing 1.381ns, distribution 1.488ns)
  Clock Net Delay (Destination): 1.961ns (routing 0.940ns, distribution 1.021ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.869     3.542    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X70Y237        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y237        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     3.621 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/Q
                         net (fo=3, routed)           1.589     5.210    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/rd_gptr[2]
    SLICE_X76Y207        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/rd_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.961     4.943    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/c_clk_i
    SLICE_X76Y207        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/rd_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/rd_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.315ns  (logic 0.079ns (6.009%)  route 1.236ns (93.991%))
  Logic Levels:           0  
  Clock Path Skew:        1.420ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.047ns
    Source Clock Delay      (SCD):    3.626ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.953ns (routing 1.381ns, distribution 1.572ns)
  Clock Net Delay (Destination): 2.065ns (routing 0.940ns, distribution 1.125ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.953     3.626    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X81Y149        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y149        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.705 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/Q
                         net (fo=5, routed)           1.236     4.941    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/rd_gptr[2]
    SLICE_X81Y154        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/rd_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.065     5.047    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/c_clk_i
    SLICE_X81Y154        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/rd_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_cdc_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.283ns  (logic 0.079ns (6.159%)  route 1.204ns (93.841%))
  Logic Levels:           0  
  Clock Path Skew:        1.436ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.074ns
    Source Clock Delay      (SCD):    3.638ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.965ns (routing 1.381ns, distribution 1.584ns)
  Clock Net Delay (Destination): 2.092ns (routing 0.940ns, distribution 1.152ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.965     3.638    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X81Y124        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y124        FDCE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     3.717 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/Q
                         net (fo=5, routed)           1.204     4.921    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr[5]
    SLICE_X82Y126        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_cdc_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.092     5.074    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/c_clk_i
    SLICE_X82Y126        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_cdc_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/rd_gptr_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.147ns  (logic 0.079ns (6.889%)  route 1.068ns (93.111%))
  Logic Levels:           0  
  Clock Path Skew:        1.403ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.144ns
    Source Clock Delay      (SCD):    3.741ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.068ns (routing 1.381ns, distribution 1.687ns)
  Clock Net Delay (Destination): 2.162ns (routing 0.940ns, distribution 1.222ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.068     3.741    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X102Y199       FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y199       FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.820 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/Q
                         net (fo=5, routed)           1.068     4.888    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/rd_gptr[7]
    SLICE_X98Y177        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/rd_gptr_cdc_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.162     5.144    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/c_clk_i
    SLICE_X98Y177        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/rd_gptr_cdc_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_cdc_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.304ns  (logic 0.079ns (6.058%)  route 1.225ns (93.942%))
  Logic Levels:           0  
  Clock Path Skew:        1.406ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.962ns
    Source Clock Delay      (SCD):    3.556ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.883ns (routing 1.381ns, distribution 1.502ns)
  Clock Net Delay (Destination): 1.980ns (routing 0.940ns, distribution 1.040ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.883     3.556    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X74Y138        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y138        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.635 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/Q
                         net (fo=3, routed)           1.225     4.860    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr[8]
    SLICE_X72Y232        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_cdc_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.980     4.962    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/c_clk_i
    SLICE_X72Y232        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_cdc_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/rd_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.051ns  (logic 0.079ns (7.517%)  route 0.972ns (92.483%))
  Logic Levels:           0  
  Clock Path Skew:        1.398ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.083ns
    Source Clock Delay      (SCD):    3.684ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.011ns (routing 1.381ns, distribution 1.630ns)
  Clock Net Delay (Destination): 2.101ns (routing 0.940ns, distribution 1.161ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.011     3.684    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X92Y123        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y123        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     3.763 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/Q
                         net (fo=5, routed)           0.972     4.735    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/rd_gptr[2]
    SLICE_X93Y152        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/rd_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.101     5.083    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/c_clk_i
    SLICE_X93Y152        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/rd_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/rd_gptr_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.993ns  (logic 0.079ns (7.953%)  route 0.914ns (92.047%))
  Logic Levels:           0  
  Clock Path Skew:        1.356ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.097ns
    Source Clock Delay      (SCD):    3.741ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.068ns (routing 1.381ns, distribution 1.687ns)
  Clock Net Delay (Destination): 2.115ns (routing 0.940ns, distribution 1.175ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.068     3.741    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X101Y199       FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y199       FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.820 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/Q
                         net (fo=5, routed)           0.914     4.734    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/rd_gptr[4]
    SLICE_X93Y175        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/rd_gptr_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.115     5.097    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/c_clk_i
    SLICE_X93Y175        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/rd_gptr_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/rd_gptr_cdc_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.973ns  (logic 0.079ns (8.118%)  route 0.894ns (91.882%))
  Logic Levels:           0  
  Clock Path Skew:        1.400ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.082ns
    Source Clock Delay      (SCD):    3.681ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.008ns (routing 1.381ns, distribution 1.627ns)
  Clock Net Delay (Destination): 2.100ns (routing 0.940ns, distribution 1.160ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.008     3.681    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X92Y130        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y130        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     3.760 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/Q
                         net (fo=5, routed)           0.894     4.654    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/rd_gptr[5]
    SLICE_X93Y151        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/rd_gptr_cdc_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.100     5.082    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/c_clk_i
    SLICE_X93Y151        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/rd_gptr_cdc_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/rd_gptr_cdc_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.964ns  (logic 0.079ns (8.195%)  route 0.885ns (91.805%))
  Logic Levels:           0  
  Clock Path Skew:        1.391ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.081ns
    Source Clock Delay      (SCD):    3.689ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.016ns (routing 1.381ns, distribution 1.635ns)
  Clock Net Delay (Destination): 2.099ns (routing 0.940ns, distribution 1.159ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.016     3.689    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X92Y124        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y124        FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     3.768 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/Q
                         net (fo=5, routed)           0.885     4.653    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/rd_gptr[8]
    SLICE_X93Y151        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/rd_gptr_cdc_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.099     5.081    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/c_clk_i
    SLICE_X93Y151        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/rd_gptr_cdc_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/rd_gptr_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.930ns  (logic 0.080ns (8.602%)  route 0.850ns (91.398%))
  Logic Levels:           0  
  Clock Path Skew:        1.366ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.086ns
    Source Clock Delay      (SCD):    3.720ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.047ns (routing 1.381ns, distribution 1.666ns)
  Clock Net Delay (Destination): 2.104ns (routing 0.940ns, distribution 1.164ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       3.047     3.720    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X102Y198       FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y198       FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     3.800 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/Q
                         net (fo=5, routed)           0.850     4.650    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/rd_gptr[0]
    SLICE_X95Y181        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/rd_gptr_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.104     5.086    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/c_clk_i
    SLICE_X95Y181        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/rd_gptr_cdc_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/rd_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.104ns  (logic 0.039ns (37.369%)  route 0.065ns (62.632%))
  Logic Levels:           0  
  Clock Path Skew:        0.809ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.713ns
    Source Clock Delay      (SCD):    1.904ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.555ns (routing 0.748ns, distribution 0.807ns)
  Clock Net Delay (Destination): 1.365ns (routing 0.639ns, distribution 0.726ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.555     1.904    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X74Y207        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y207        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.943 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/Q
                         net (fo=3, routed)           0.065     2.008    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/rd_gptr[2]
    SLICE_X74Y205        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/rd_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.365     2.713    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/c_clk_i
    SLICE_X74Y205        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/rd_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/rd_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.103ns  (logic 0.039ns (38.022%)  route 0.064ns (61.978%))
  Logic Levels:           0  
  Clock Path Skew:        0.833ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.742ns
    Source Clock Delay      (SCD):    1.909ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.560ns (routing 0.748ns, distribution 0.812ns)
  Clock Net Delay (Destination): 1.394ns (routing 0.639ns, distribution 0.755ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.560     1.909    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X65Y176        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y176        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.948 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/Q
                         net (fo=3, routed)           0.064     2.012    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/rd_gptr[2]
    SLICE_X66Y176        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/rd_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.394     2.742    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/c_clk_i
    SLICE_X66Y176        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/rd_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/rd_gptr_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.103ns  (logic 0.041ns (39.965%)  route 0.062ns (60.035%))
  Logic Levels:           0  
  Clock Path Skew:        0.834ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.746ns
    Source Clock Delay      (SCD):    1.912ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.563ns (routing 0.748ns, distribution 0.815ns)
  Clock Net Delay (Destination): 1.398ns (routing 0.639ns, distribution 0.759ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.563     1.912    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X73Y159        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y159        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.953 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/Q
                         net (fo=3, routed)           0.062     2.014    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/rd_gptr[0]
    SLICE_X73Y161        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/rd_gptr_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.398     2.746    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/c_clk_i
    SLICE_X73Y161        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/rd_gptr_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr_cdc_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.116ns  (logic 0.039ns (33.515%)  route 0.077ns (66.485%))
  Logic Levels:           0  
  Clock Path Skew:        0.833ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.732ns
    Source Clock Delay      (SCD):    1.899ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.550ns (routing 0.748ns, distribution 0.802ns)
  Clock Net Delay (Destination): 1.384ns (routing 0.639ns, distribution 0.745ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.550     1.899    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X66Y182        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y182        FDCE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     1.938 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/Q
                         net (fo=5, routed)           0.077     2.015    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr[5]
    SLICE_X66Y184        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr_cdc_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.384     2.732    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/c_clk_i
    SLICE_X66Y184        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr_cdc_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/rd_gptr_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.925%)  route 0.059ns (60.075%))
  Logic Levels:           0  
  Clock Path Skew:        0.818ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.737ns
    Source Clock Delay      (SCD):    1.920ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.571ns (routing 0.748ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.389ns (routing 0.639ns, distribution 0.750ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.571     1.920    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X74Y140        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y140        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.959 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/Q
                         net (fo=3, routed)           0.059     2.017    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/rd_gptr[1]
    SLICE_X74Y139        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/rd_gptr_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.389     2.737    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/c_clk_i
    SLICE_X74Y139        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/rd_gptr_cdc_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[21]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.112ns  (logic 0.038ns (33.929%)  route 0.074ns (66.071%))
  Logic Levels:           0  
  Clock Path Skew:        0.834ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.739ns
    Source Clock Delay      (SCD):    1.906ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.557ns (routing 0.748ns, distribution 0.809ns)
  Clock Net Delay (Destination): 1.391ns (routing 0.639ns, distribution 0.752ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.557     1.906    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_clk_i
    SLICE_X67Y159        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y159        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     1.944 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[21]/Q
                         net (fo=1, routed)           0.074     2.018    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_time_abs_cdc[21]
    SLICE_X67Y159        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[21]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.391     2.739    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/c_clk_i
    SLICE_X67Y159        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[21]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/rd_gptr_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.207%)  route 0.060ns (60.793%))
  Logic Levels:           0  
  Clock Path Skew:        0.807ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.725ns
    Source Clock Delay      (SCD):    1.919ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.570ns (routing 0.748ns, distribution 0.822ns)
  Clock Net Delay (Destination): 1.377ns (routing 0.639ns, distribution 0.738ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.570     1.919    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X77Y155        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y155        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.958 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/Q
                         net (fo=3, routed)           0.060     2.018    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/rd_gptr[1]
    SLICE_X77Y153        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/rd_gptr_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.377     2.725    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/c_clk_i
    SLICE_X77Y153        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/rd_gptr_cdc_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/rd_gptr_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.041ns (40.819%)  route 0.059ns (59.181%))
  Logic Levels:           0  
  Clock Path Skew:        0.811ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.729ns
    Source Clock Delay      (SCD):    1.919ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.570ns (routing 0.748ns, distribution 0.822ns)
  Clock Net Delay (Destination): 1.381ns (routing 0.639ns, distribution 0.742ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.570     1.919    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X77Y155        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y155        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.960 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/Q
                         net (fo=3, routed)           0.059     2.019    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/rd_gptr[0]
    SLICE_X77Y154        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/rd_gptr_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.381     2.729    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/c_clk_i
    SLICE_X77Y154        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/rd_gptr_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.040ns (33.058%)  route 0.081ns (66.942%))
  Logic Levels:           0  
  Clock Path Skew:        0.840ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.739ns
    Source Clock Delay      (SCD):    1.899ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.550ns (routing 0.748ns, distribution 0.802ns)
  Clock Net Delay (Destination): 1.391ns (routing 0.639ns, distribution 0.752ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.550     1.899    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_clk_i
    SLICE_X68Y158        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y158        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     1.939 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[4]/Q
                         net (fo=1, routed)           0.081     2.020    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_time_abs_cdc[4]
    SLICE_X68Y158        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.391     2.739    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/c_clk_i
    SLICE_X68Y158        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[26]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[26]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.110ns  (logic 0.038ns (34.545%)  route 0.072ns (65.455%))
  Logic Levels:           0  
  Clock Path Skew:        0.826ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.736ns
    Source Clock Delay      (SCD):    1.910ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.561ns (routing 0.748ns, distribution 0.813ns)
  Clock Net Delay (Destination): 1.388ns (routing 0.639ns, distribution 0.749ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.561     1.910    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_clk_i
    SLICE_X67Y160        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[26]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y160        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     1.948 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[26]/Q
                         net (fo=1, routed)           0.072     2.020    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_time_abs_cdc[26]
    SLICE_X67Y160        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[26]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.388     2.736    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/c_clk_i
    SLICE_X67Y160        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[26]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay           494 Endpoints
Min Delay           494 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[28]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.083ns  (logic 0.289ns (26.685%)  route 0.794ns (73.315%))
  Logic Levels:           0  
  Clock Path Skew:        2.735ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.067ns
    Source Clock Delay      (SCD):    2.332ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.106ns (routing 0.662ns, distribution 1.444ns)
  Clock Net Delay (Destination): 2.085ns (routing 0.940ns, distribution 1.145ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.106     2.332    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X56Y100        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y100        RAMD32 (Prop_A5LUT_SLICEM_CLK_O)
                                                      0.289     2.621 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA/O
                         net (fo=1, routed)           0.794     3.415    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[28]
    SLICE_X57Y113        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[28]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.085     5.067    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X57Y113        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[28]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[47]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.060ns  (logic 0.307ns (28.962%)  route 0.753ns (71.038%))
  Logic Levels:           0  
  Clock Path Skew:        2.724ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.066ns
    Source Clock Delay      (SCD):    2.342ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.116ns (routing 0.662ns, distribution 1.454ns)
  Clock Net Delay (Destination): 2.084ns (routing 0.940ns, distribution 1.144ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.116     2.342    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X56Y117        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y117        RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.307     2.649 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMC_D1/O
                         net (fo=1, routed)           0.753     3.402    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[47]
    SLICE_X57Y123        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[47]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.084     5.066    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X57Y123        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[47]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.064ns  (logic 0.307ns (28.853%)  route 0.757ns (71.147%))
  Logic Levels:           0  
  Clock Path Skew:        2.754ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.083ns
    Source Clock Delay      (SCD):    2.329ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.103ns (routing 0.662ns, distribution 1.441ns)
  Clock Net Delay (Destination): 2.101ns (routing 0.940ns, distribution 1.161ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.103     2.329    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/WCLK
    SLICE_X56Y98         RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y98         RAMD32 (Prop_B6LUT_SLICEM_CLK_O)
                                                      0.307     2.636 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMB_D1/O
                         net (fo=1, routed)           0.757     3.393    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[17]
    SLICE_X52Y111        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.101     5.083    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X52Y111        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[17]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMC/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[60]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.026ns  (logic 0.288ns (28.070%)  route 0.738ns (71.930%))
  Logic Levels:           0  
  Clock Path Skew:        2.752ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.080ns
    Source Clock Delay      (SCD):    2.328ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.102ns (routing 0.662ns, distribution 1.440ns)
  Clock Net Delay (Destination): 2.098ns (routing 0.940ns, distribution 1.158ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.102     2.328    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/WCLK
    SLICE_X54Y98         RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMC/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y98         RAMD32 (Prop_C5LUT_SLICEM_CLK_O)
                                                      0.288     2.616 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMC/O
                         net (fo=1, routed)           0.738     3.354    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[60]
    SLICE_X56Y112        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[60]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.098     5.080    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X56Y112        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[60]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[61]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.011ns  (logic 0.307ns (30.366%)  route 0.704ns (69.634%))
  Logic Levels:           0  
  Clock Path Skew:        2.750ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.078ns
    Source Clock Delay      (SCD):    2.328ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.102ns (routing 0.662ns, distribution 1.440ns)
  Clock Net Delay (Destination): 2.096ns (routing 0.940ns, distribution 1.156ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.102     2.328    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/WCLK
    SLICE_X54Y98         RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y98         RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.307     2.635 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMC_D1/O
                         net (fo=1, routed)           0.704     3.339    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[61]
    SLICE_X57Y112        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[61]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.096     5.078    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X57Y112        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[61]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[36]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.984ns  (logic 0.288ns (29.268%)  route 0.696ns (70.732%))
  Logic Levels:           0  
  Clock Path Skew:        2.730ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.044ns
    Source Clock Delay      (SCD):    2.315ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.089ns (routing 0.662ns, distribution 1.427ns)
  Clock Net Delay (Destination): 2.062ns (routing 0.940ns, distribution 1.122ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.089     2.315    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X48Y149        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y149        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.288     2.603 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAME/O
                         net (fo=1, routed)           0.696     3.299    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[36]
    SLICE_X54Y150        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[36]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.062     5.044    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X54Y150        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[36]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[25]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.962ns  (logic 0.304ns (31.601%)  route 0.658ns (68.399%))
  Logic Levels:           0  
  Clock Path Skew:        2.747ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.076ns
    Source Clock Delay      (SCD):    2.329ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.103ns (routing 0.662ns, distribution 1.441ns)
  Clock Net Delay (Destination): 2.094ns (routing 0.940ns, distribution 1.154ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.103     2.329    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/WCLK
    SLICE_X56Y98         RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y98         RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.304     2.633 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMF_D1/O
                         net (fo=1, routed)           0.658     3.291    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[25]
    SLICE_X54Y112        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[25]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.094     5.076    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X54Y112        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[25]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.957ns  (logic 0.305ns (31.870%)  route 0.652ns (68.130%))
  Logic Levels:           0  
  Clock Path Skew:        2.747ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.078ns
    Source Clock Delay      (SCD):    2.331ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.105ns (routing 0.662ns, distribution 1.443ns)
  Clock Net Delay (Destination): 2.096ns (routing 0.940ns, distribution 1.156ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.105     2.331    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X54Y100        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y100        RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.305     2.636 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA_D1/O
                         net (fo=1, routed)           0.652     3.288    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[1]
    SLICE_X57Y112        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.096     5.078    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X57Y112        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[21]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.956ns  (logic 0.301ns (31.485%)  route 0.655ns (68.515%))
  Logic Levels:           0  
  Clock Path Skew:        2.754ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.083ns
    Source Clock Delay      (SCD):    2.329ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.103ns (routing 0.662ns, distribution 1.441ns)
  Clock Net Delay (Destination): 2.101ns (routing 0.940ns, distribution 1.161ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.103     2.329    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/WCLK
    SLICE_X56Y98         RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y98         RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.301     2.630 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMD_D1/O
                         net (fo=1, routed)           0.655     3.285    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[21]
    SLICE_X52Y111        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[21]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.101     5.083    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X52Y111        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[21]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMF/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[24]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.943ns  (logic 0.295ns (31.283%)  route 0.648ns (68.717%))
  Logic Levels:           0  
  Clock Path Skew:        2.754ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.083ns
    Source Clock Delay      (SCD):    2.329ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.103ns (routing 0.662ns, distribution 1.441ns)
  Clock Net Delay (Destination): 2.101ns (routing 0.940ns, distribution 1.161ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.103     2.329    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/WCLK
    SLICE_X56Y98         RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMF/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y98         RAMD32 (Prop_F5LUT_SLICEM_CLK_O)
                                                      0.295     2.624 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMF/O
                         net (fo=1, routed)           0.648     3.272    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[24]
    SLICE_X52Y111        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[24]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.101     5.083    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X52Y111        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[24]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.103ns  (logic 0.039ns (37.864%)  route 0.064ns (62.136%))
  Logic Levels:           0  
  Clock Path Skew:        1.571ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.810ns
    Source Clock Delay      (SCD):    1.240ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.120ns (routing 0.359ns, distribution 0.761ns)
  Clock Net Delay (Destination): 1.462ns (routing 0.639ns, distribution 0.823ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.120     1.240    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X45Y146        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y146        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.279 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.064     1.343    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[0]
    SLICE_X45Y148        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.462     2.810    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X45Y148        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.105ns  (logic 0.039ns (37.143%)  route 0.066ns (62.857%))
  Logic Levels:           0  
  Clock Path Skew:        1.573ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.812ns
    Source Clock Delay      (SCD):    1.240ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.120ns (routing 0.359ns, distribution 0.761ns)
  Clock Net Delay (Destination): 1.464ns (routing 0.639ns, distribution 0.825ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.120     1.240    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X45Y146        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y146        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.279 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.066     1.345    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1]
    SLICE_X45Y148        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.464     2.812    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X45Y148        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.796%)  route 0.059ns (60.204%))
  Logic Levels:           0  
  Clock Path Skew:        1.540ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.800ns
    Source Clock Delay      (SCD):    1.260ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.140ns (routing 0.359ns, distribution 0.781ns)
  Clock Net Delay (Destination): 1.452ns (routing 0.639ns, distribution 0.813ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.140     1.260    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X58Y97         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y97         FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.299 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.059     1.358    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2]
    SLICE_X58Y97         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.452     2.800    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X58Y97         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.039ns (32.500%)  route 0.081ns (67.500%))
  Logic Levels:           0  
  Clock Path Skew:        1.566ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.806ns
    Source Clock Delay      (SCD):    1.240ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.120ns (routing 0.359ns, distribution 0.761ns)
  Clock Net Delay (Destination): 1.458ns (routing 0.639ns, distribution 0.819ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.120     1.240    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X45Y146        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y146        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     1.279 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.081     1.360    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3]
    SLICE_X44Y147        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.458     2.806    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X44Y147        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.097ns  (logic 0.039ns (40.168%)  route 0.058ns (59.832%))
  Logic Levels:           0  
  Clock Path Skew:        1.533ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.796ns
    Source Clock Delay      (SCD):    1.263ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.143ns (routing 0.359ns, distribution 0.784ns)
  Clock Net Delay (Destination): 1.448ns (routing 0.639ns, distribution 0.809ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.143     1.263    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X59Y97         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y97         FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.302 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.058     1.360    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X59Y98         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.448     2.796    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X59Y98         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.104ns  (logic 0.039ns (37.466%)  route 0.065ns (62.533%))
  Logic Levels:           0  
  Clock Path Skew:        1.551ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.815ns
    Source Clock Delay      (SCD):    1.264ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.144ns (routing 0.359ns, distribution 0.785ns)
  Clock Net Delay (Destination): 1.467ns (routing 0.639ns, distribution 0.828ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.144     1.264    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X53Y117        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y117        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.303 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.065     1.368    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X53Y118        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.467     2.815    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X53Y118        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.758%)  route 0.059ns (60.242%))
  Logic Levels:           0  
  Clock Path Skew:        1.538ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.810ns
    Source Clock Delay      (SCD):    1.273ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.153ns (routing 0.359ns, distribution 0.794ns)
  Clock Net Delay (Destination): 1.462ns (routing 0.639ns, distribution 0.823ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.153     1.273    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X58Y110        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y110        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.312 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.059     1.371    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X58Y111        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.462     2.810    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X58Y111        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.040ns (31.496%)  route 0.087ns (68.504%))
  Logic Levels:           0  
  Clock Path Skew:        1.540ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.800ns
    Source Clock Delay      (SCD):    1.260ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.140ns (routing 0.359ns, distribution 0.781ns)
  Clock Net Delay (Destination): 1.452ns (routing 0.639ns, distribution 0.813ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.140     1.260    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X58Y97         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y97         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     1.300 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.087     1.387    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3]
    SLICE_X58Y97         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.452     2.800    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X58Y97         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.148ns  (logic 0.039ns (26.351%)  route 0.109ns (73.649%))
  Logic Levels:           0  
  Clock Path Skew:        1.571ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.810ns
    Source Clock Delay      (SCD):    1.240ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.120ns (routing 0.359ns, distribution 0.761ns)
  Clock Net Delay (Destination): 1.462ns (routing 0.639ns, distribution 0.823ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.120     1.240    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X45Y146        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y146        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     1.279 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.109     1.388    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2]
    SLICE_X45Y148        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.462     2.810    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X45Y148        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.126ns  (logic 0.040ns (31.746%)  route 0.086ns (68.254%))
  Logic Levels:           0  
  Clock Path Skew:        1.543ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.805ns
    Source Clock Delay      (SCD):    1.262ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.142ns (routing 0.359ns, distribution 0.783ns)
  Clock Net Delay (Destination): 1.457ns (routing 0.639ns, distribution 0.818ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.142     1.262    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X57Y118        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y118        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.302 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.086     1.388    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3]
    SLICE_X57Y118        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.457     2.805    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X57Y118        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_pl_0

Max Delay           107 Endpoints
Min Delay           107 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.775ns  (logic 0.100ns (3.604%)  route 2.675ns (96.396%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.973ns (routing 0.599ns, distribution 1.374ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           2.033     2.033    d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X72Y284        LUT1 (Prop_A6LUT_SLICEM_I0_O)
                                                      0.100     2.133 r  d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.642     2.775    d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X74Y319        FDRE                                         r  d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.973     2.155    d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X74Y319        FDRE                                         r  d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_supplies_up_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.170ns  (logic 0.000ns (0.000%)  route 2.170ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.162ns (routing 0.599ns, distribution 1.563ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[1]
                         net (fo=2, routed)           2.170     2.170    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_supplies_up_i/src_in
    SLICE_X113Y165       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_supplies_up_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.162     2.344    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_supplies_up_i/dest_clk
    SLICE_X113Y165       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_supplies_up_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[0]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_clk_present_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.102ns  (logic 0.000ns (0.000%)  route 2.102ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.161ns (routing 0.599ns, distribution 1.562ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[0]
                         net (fo=2, routed)           2.102     2.102    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_clk_present_i/src_in
    SLICE_X112Y165       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_clk_present_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.161     2.343    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_clk_present_i/dest_clk
    SLICE_X112Y165       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_clk_present_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_powerup_state_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.854ns  (logic 0.000ns (0.000%)  route 1.854ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.155ns (routing 0.599ns, distribution 1.556ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[2]
                         net (fo=2, routed)           1.854     1.854    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_powerup_state_i/src_in
    SLICE_X115Y149       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_powerup_state_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.155     2.337    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_powerup_state_i/dest_clk
    SLICE_X115Y149       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_powerup_state_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC2[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.761ns  (logic 0.000ns (0.000%)  route 1.761ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.134ns (routing 0.599ns, distribution 1.535ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC2[14]
                         net (fo=1, routed)           1.761     1.761    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/src_in
    SLICE_X115Y213       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.134     2.316    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/dest_clk
    SLICE_X115Y213       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_powerup_state_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.709ns  (logic 0.000ns (0.000%)  route 1.709ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.149ns (routing 0.599ns, distribution 1.550ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[2]
                         net (fo=2, routed)           1.709     1.709    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_powerup_state_i/src_in
    SLICE_X114Y157       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_powerup_state_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.149     2.331    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_powerup_state_i/dest_clk
    SLICE_X114Y157       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_powerup_state_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_pll_lock_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.659ns  (logic 0.000ns (0.000%)  route 1.659ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.172ns (routing 0.599ns, distribution 1.573ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[3]
                         net (fo=2, routed)           1.659     1.659    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_pll_lock_i/src_in
    SLICE_X115Y166       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_pll_lock_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.172     2.354    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_pll_lock_i/dest_clk
    SLICE_X115Y166       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_pll_lock_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC3[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.480ns  (logic 0.000ns (0.000%)  route 1.480ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.199ns (routing 0.599ns, distribution 1.600ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC3[14]
                         net (fo=1, routed)           1.480     1.480    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/src_in
    SLICE_X116Y254       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.199     2.381    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/dest_clk
    SLICE_X116Y254       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_powerup_state_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.387ns  (logic 0.000ns (0.000%)  route 1.387ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.161ns (routing 0.599ns, distribution 1.562ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[2]
                         net (fo=2, routed)           1.387     1.387    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_powerup_state_i/src_in
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_powerup_state_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.161     2.343    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_powerup_state_i/dest_clk
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_powerup_state_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_pll_lock_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.378ns  (logic 0.000ns (0.000%)  route 1.378ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.169ns (routing 0.599ns, distribution 1.570ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[3]
                         net (fo=2, routed)           1.378     1.378    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_pll_lock_i/src_in
    SLICE_X114Y175       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_pll_lock_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.169     2.351    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_pll_lock_i/dest_clk
    SLICE_X114Y175       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_pll_lock_i/syncstages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC2[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.111ns  (logic 0.000ns (0.000%)  route 0.111ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.513ns (routing 0.405ns, distribution 1.108ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC2[15]
                         net (fo=1, routed)           0.111     0.111    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_fifo_irq/src_in
    SLICE_X118Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.513     1.660    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_fifo_irq/dest_clk
    SLICE_X118Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC3[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.112ns  (logic 0.000ns (0.000%)  route 0.112ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.514ns (routing 0.405ns, distribution 1.109ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC3[3]
                         net (fo=1, routed)           0.112     0.112    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_over_range/src_in
    SLICE_X118Y112       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_over_range/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.514     1.661    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_over_range/dest_clk
    SLICE_X118Y112       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_over_range/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_ADC1[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc31_over_vol/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.132ns  (logic 0.000ns (0.000%)  route 0.132ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.481ns (routing 0.405ns, distribution 1.076ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_ADC1[2]
                         net (fo=1, routed)           0.132     0.132    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc31_over_vol/src_in
    SLICE_X118Y191       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc31_over_vol/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.481     1.628    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc31_over_vol/dest_clk
    SLICE_X118Y191       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc31_over_vol/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC2[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.133ns  (logic 0.000ns (0.000%)  route 0.133ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.511ns (routing 0.405ns, distribution 1.106ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC2[3]
                         net (fo=1, routed)           0.133     0.133    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_over_range/src_in
    SLICE_X118Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_over_range/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.511     1.658    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_over_range/dest_clk
    SLICE_X118Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_over_range/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC2[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.140ns  (logic 0.000ns (0.000%)  route 0.140ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.513ns (routing 0.405ns, distribution 1.108ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC2[14]
                         net (fo=1, routed)           0.140     0.140    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_data_irq/src_in
    SLICE_X117Y108       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.513     1.660    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_data_irq/dest_clk
    SLICE_X117Y108       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC1[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.142ns  (logic 0.000ns (0.000%)  route 0.142ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.495ns (routing 0.405ns, distribution 1.090ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC1[15]
                         net (fo=1, routed)           0.142     0.142    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_fifo_irq/src_in
    SLICE_X118Y138       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.495     1.642    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_fifo_irq/dest_clk
    SLICE_X118Y138       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC3[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.145ns  (logic 0.000ns (0.000%)  route 0.145ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.495ns (routing 0.405ns, distribution 1.090ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC3[3]
                         net (fo=1, routed)           0.145     0.145    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_over_range/src_in
    SLICE_X118Y168       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_over_range/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.495     1.642    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_over_range/dest_clk
    SLICE_X118Y168       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_over_range/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC0[0]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc0_status_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.152ns  (logic 0.000ns (0.000%)  route 0.152ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.492ns (routing 0.405ns, distribution 1.087ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC0[0]
                         net (fo=1, routed)           0.152     0.152    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc0_status_i/src_in
    SLICE_X117Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc0_status_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.492     1.639    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc0_status_i/dest_clk
    SLICE_X117Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc0_status_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC0[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.157ns  (logic 0.000ns (0.000%)  route 0.157ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.499ns (routing 0.405ns, distribution 1.094ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC0[14]
                         net (fo=1, routed)           0.157     0.157    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_data_irq/src_in
    SLICE_X118Y129       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.499     1.646    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_data_irq/dest_clk
    SLICE_X118Y129       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC0[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.159ns  (logic 0.000ns (0.000%)  route 0.159ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.499ns (routing 0.405ns, distribution 1.094ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC0[3]
                         net (fo=1, routed)           0.159     0.159    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_over_range/src_in
    SLICE_X118Y125       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_over_range/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.499     1.646    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_over_range/dest_clk
    SLICE_X118Y125       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_over_range/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC0_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.064ns  (logic 1.162ns (37.924%)  route 1.902ns (62.076%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.341ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.341ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.159ns (routing 0.599ns, distribution 1.560ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           1.466     2.237    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[13]
    SLICE_X114Y108       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.123     2.360 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17/O
                         net (fo=1, routed)           0.093     2.453    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17_n_0
    SLICE_X114Y109       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.122     2.575 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4/O
                         net (fo=1, routed)           0.293     2.868    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4_n_0
    SLICE_X114Y122       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.146     3.014 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.050     3.064    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.159     2.341    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.752ns  (logic 0.979ns (35.574%)  route 1.773ns (64.426%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.343ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.343ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.161ns (routing 0.599ns, distribution 1.562ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           1.192     1.717    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[15]
    SLICE_X115Y109       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.125     1.842 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_36/O
                         net (fo=1, routed)           0.061     1.903    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_36_n_0
    SLICE_X115Y109       LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.149     2.052 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15/O
                         net (fo=1, routed)           0.252     2.304    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_n_0
    SLICE_X114Y112       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.090     2.394 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4/O
                         net (fo=1, routed)           0.217     2.611    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4_n_0
    SLICE_X114Y121       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.090     2.701 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.051     2.752    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.161     2.343    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.587ns  (logic 0.907ns (35.060%)  route 1.680ns (64.940%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           1.076     1.664    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[11]
    SLICE_X111Y107       LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.123     1.787 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_9/O
                         net (fo=1, routed)           0.213     2.000    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_9_n_0
    SLICE_X111Y115       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.050     2.050 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                         net (fo=1, routed)           0.341     2.391    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    SLICE_X111Y127       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.146     2.537 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.050     2.587    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.548ns  (logic 1.108ns (43.485%)  route 1.440ns (56.515%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.939     1.727    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[8]
    SLICE_X114Y109       LUT6 (Prop_E6LUT_SLICEL_I3_O)
                                                      0.099     1.826 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_13/O
                         net (fo=1, routed)           0.170     1.996    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_13_n_0
    SLICE_X111Y110       LUT6 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.123     2.119 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/O
                         net (fo=1, routed)           0.282     2.401    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3_n_0
    SLICE_X111Y127       LUT6 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.098     2.499 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.049     2.548    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.537ns  (logic 0.705ns (27.789%)  route 1.832ns (72.211%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           1.191     1.723    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[9]
    SLICE_X111Y107       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.049     1.772 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12/O
                         net (fo=1, routed)           0.231     2.003    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12_n_0
    SLICE_X111Y112       LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.089     2.092 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.362     2.454    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X111Y127       LUT6 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.035     2.489 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.048     2.537    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.475ns  (logic 0.930ns (37.576%)  route 1.545ns (62.424%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.341ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.341ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.159ns (routing 0.599ns, distribution 1.560ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           1.104     1.715    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[12]
    SLICE_X114Y109       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.123     1.838 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_13/O
                         net (fo=1, routed)           0.044     1.882    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_13_n_0
    SLICE_X114Y109       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.097     1.979 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4/O
                         net (fo=1, routed)           0.348     2.327    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4_n_0
    SLICE_X114Y122       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.099     2.426 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.049     2.475    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.159     2.341    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.441ns  (logic 0.920ns (37.689%)  route 1.521ns (62.311%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.860     1.558    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[14]
    SLICE_X115Y109       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.037     1.595 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_35/O
                         net (fo=1, routed)           0.040     1.635    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_35_n_0
    SLICE_X115Y109       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.037     1.672 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17/O
                         net (fo=1, routed)           0.140     1.812    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17_n_0
    SLICE_X114Y110       LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.097     1.909 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5/O
                         net (fo=1, routed)           0.430     2.339    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5_n_0
    SLICE_X114Y127       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.051     2.390 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.051     2.441    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.416ns  (logic 0.823ns (34.065%)  route 1.593ns (65.935%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           1.094     1.630    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[10]
    SLICE_X111Y107       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.122     1.752 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7/O
                         net (fo=1, routed)           0.141     1.893    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7_n_0
    SLICE_X111Y111       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.099     1.992 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2/O
                         net (fo=1, routed)           0.343     2.335    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2_n_0
    SLICE_X111Y127       LUT5 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.066     2.401 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.015     2.416    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.090ns  (logic 0.369ns (33.853%)  route 0.721ns (66.147%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.466     0.703    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[8]
    SLICE_X114Y109       LUT6 (Prop_E6LUT_SLICEL_I3_O)
                                                      0.041     0.744 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_13/O
                         net (fo=1, routed)           0.090     0.834    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_13_n_0
    SLICE_X111Y110       LUT6 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.050     0.884 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/O
                         net (fo=1, routed)           0.150     1.034    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3_n_0
    SLICE_X111Y127       LUT6 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.041     1.075 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.015     1.090    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.123ns  (logic 0.338ns (30.098%)  route 0.785ns (69.902%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.525     0.752    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[10]
    SLICE_X111Y107       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.050     0.802 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7/O
                         net (fo=1, routed)           0.077     0.879    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7_n_0
    SLICE_X111Y111       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.041     0.920 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2/O
                         net (fo=1, routed)           0.177     1.097    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2_n_0
    SLICE_X111Y127       LUT5 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.020     1.117 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.006     1.123    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.138ns  (logic 0.376ns (33.040%)  route 0.762ns (66.960%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.637ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.637ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.490ns (routing 0.405ns, distribution 1.085ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.425     0.710    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[14]
    SLICE_X115Y109       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.014     0.724 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_35/O
                         net (fo=1, routed)           0.022     0.746    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_35_n_0
    SLICE_X115Y109       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.014     0.760 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17/O
                         net (fo=1, routed)           0.073     0.833    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17_n_0
    SLICE_X114Y110       LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.040     0.873 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5/O
                         net (fo=1, routed)           0.225     1.098    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5_n_0
    SLICE_X114Y127       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.023     1.121 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.017     1.138    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.490     1.637    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.174ns  (logic 0.405ns (34.497%)  route 0.769ns (65.503%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.634ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.634ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.487ns (routing 0.405ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.549     0.823    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[12]
    SLICE_X114Y109       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.050     0.873 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_13/O
                         net (fo=1, routed)           0.025     0.898    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_13_n_0
    SLICE_X114Y109       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.040     0.938 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4/O
                         net (fo=1, routed)           0.179     1.117    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4_n_0
    SLICE_X114Y122       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.041     1.158 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.016     1.174    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.487     1.634    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.207ns  (logic 0.396ns (32.809%)  route 0.811ns (67.191%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.509     0.774    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[11]
    SLICE_X111Y107       LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.050     0.824 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_9/O
                         net (fo=1, routed)           0.109     0.933    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_9_n_0
    SLICE_X111Y115       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.022     0.955 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                         net (fo=1, routed)           0.176     1.131    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    SLICE_X111Y127       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.059     1.190 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.017     1.207    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.215ns  (logic 0.299ns (24.609%)  route 0.916ns (75.391%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.595     0.823    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[9]
    SLICE_X111Y107       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.022     0.845 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12/O
                         net (fo=1, routed)           0.119     0.964    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12_n_0
    SLICE_X111Y112       LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.035     0.999 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.186     1.185    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X111Y127       LUT6 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.014     1.199 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.016     1.215    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.316ns  (logic 0.431ns (32.751%)  route 0.885ns (67.249%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.638ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.638ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.491ns (routing 0.405ns, distribution 1.086ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.592     0.842    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[15]
    SLICE_X115Y109       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.051     0.893 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_36/O
                         net (fo=1, routed)           0.034     0.927    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_36_n_0
    SLICE_X115Y109       LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.060     0.987 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15/O
                         net (fo=1, routed)           0.127     1.114    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_n_0
    SLICE_X114Y112       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.035     1.149 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4/O
                         net (fo=1, routed)           0.115     1.264    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4_n_0
    SLICE_X114Y121       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.035     1.299 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.017     1.316    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.491     1.638    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.370ns  (logic 0.400ns (29.197%)  route 0.970ns (70.803%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.634ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.634ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.487ns (routing 0.405ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.748     0.989    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[13]
    SLICE_X114Y108       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.050     1.039 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17/O
                         net (fo=1, routed)           0.051     1.090    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17_n_0
    SLICE_X114Y109       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050     1.140 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4/O
                         net (fo=1, routed)           0.154     1.294    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4_n_0
    SLICE_X114Y122       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.059     1.353 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.017     1.370    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.487     1.634    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC1_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.570ns  (logic 1.121ns (43.619%)  route 1.449ns (56.381%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.483     1.181    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[14]
    SLICE_X117Y116       LUT6 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.035     1.216 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_41/O
                         net (fo=1, routed)           0.198     1.414    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_41_n_0
    SLICE_X116Y114       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.150     1.564 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_20/O
                         net (fo=1, routed)           0.390     1.954    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_20_n_0
    SLICE_X117Y125       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.088     2.042 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.327     2.369    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X114Y127       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.150     2.519 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.051     2.570    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.412ns  (logic 0.911ns (37.769%)  route 1.501ns (62.231%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.615     1.203    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[11]
    SLICE_X115Y113       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.037     1.240 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_25/O
                         net (fo=1, routed)           0.287     1.527    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_25_n_0
    SLICE_X114Y115       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.146     1.673 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13/O
                         net (fo=1, routed)           0.179     1.852    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13_n_0
    SLICE_X114Y115       LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.090     1.942 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/O
                         net (fo=1, routed)           0.370     2.312    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3_n_0
    SLICE_X111Y127       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.050     2.362 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.050     2.412    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.275ns  (logic 1.191ns (52.352%)  route 1.084ns (47.648%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.456     1.244    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[8]
    SLICE_X117Y113       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     1.279 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26/O
                         net (fo=1, routed)           0.220     1.499    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26_n_0
    SLICE_X114Y115       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.123     1.622 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16/O
                         net (fo=1, routed)           0.044     1.666    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16_n_0
    SLICE_X114Y115       LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.097     1.763 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4/O
                         net (fo=1, routed)           0.315     2.078    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4_n_0
    SLICE_X111Y127       LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.148     2.226 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.049     2.275    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.075ns  (logic 0.830ns (40.000%)  route 1.245ns (60.000%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.485     1.017    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[9]
    SLICE_X117Y113       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.049     1.066 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_23/O
                         net (fo=1, routed)           0.316     1.382    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_23_n_0
    SLICE_X114Y119       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.035     1.417 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15/O
                         net (fo=1, routed)           0.041     1.458    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15_n_0
    SLICE_X114Y119       LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.090     1.548 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4/O
                         net (fo=1, routed)           0.355     1.903    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4_n_0
    SLICE_X111Y127       LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.124     2.027 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.048     2.075    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.022ns  (logic 0.938ns (46.390%)  route 1.084ns (53.610%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.341ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.341ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.159ns (routing 0.599ns, distribution 1.560ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.549     1.320    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[13]
    SLICE_X114Y114       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.096     1.416 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21/O
                         net (fo=1, routed)           0.219     1.635    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21_n_0
    SLICE_X114Y114       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.036     1.671 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/O
                         net (fo=1, routed)           0.266     1.937    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5_n_0
    SLICE_X114Y122       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     1.972 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.050     2.022    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.159     2.341    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.937ns  (logic 0.888ns (45.844%)  route 1.049ns (54.156%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.343ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.343ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.161ns (routing 0.599ns, distribution 1.562ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.455     0.980    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[15]
    SLICE_X118Y113       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.125     1.105 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52/O
                         net (fo=1, routed)           0.182     1.287    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52_n_0
    SLICE_X116Y114       LUT5 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.090     1.377 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23/O
                         net (fo=1, routed)           0.261     1.638    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_n_0
    SLICE_X116Y121       LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.097     1.735 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.100     1.835    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X114Y121       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.051     1.886 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.051     1.937    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.161     2.343    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.889ns  (logic 0.757ns (40.074%)  route 1.132ns (59.926%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.606     1.142    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[10]
    SLICE_X114Y114       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.035     1.177 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_10/O
                         net (fo=1, routed)           0.141     1.318    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_10_n_0
    SLICE_X113Y114       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.090     1.408 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/O
                         net (fo=1, routed)           0.370     1.778    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3_n_0
    SLICE_X111Y127       LUT5 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.096     1.874 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.015     1.889    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.796ns  (logic 0.804ns (44.766%)  route 0.992ns (55.234%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.341ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.341ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.159ns (routing 0.599ns, distribution 1.560ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.501     1.112    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[12]
    SLICE_X116Y114       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.035     1.147 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_14/O
                         net (fo=1, routed)           0.275     1.422    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_14_n_0
    SLICE_X116Y118       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.036     1.458 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                         net (fo=1, routed)           0.167     1.625    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    SLICE_X114Y122       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.122     1.747 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.049     1.796    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.159     2.341    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.832ns  (logic 0.353ns (42.428%)  route 0.479ns (57.572%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.634ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.634ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.487ns (routing 0.405ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.237     0.511    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[12]
    SLICE_X116Y114       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.014     0.525 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_14/O
                         net (fo=1, routed)           0.138     0.663    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_14_n_0
    SLICE_X116Y118       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.015     0.678 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                         net (fo=1, routed)           0.088     0.766    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    SLICE_X114Y122       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.050     0.816 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.016     0.832    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.487     1.634    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.834ns  (logic 0.310ns (37.170%)  route 0.524ns (62.830%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.634ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.634ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.487ns (routing 0.405ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.261     0.502    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[13]
    SLICE_X114Y114       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.040     0.542 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21/O
                         net (fo=1, routed)           0.110     0.652    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21_n_0
    SLICE_X114Y114       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.015     0.667 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/O
                         net (fo=1, routed)           0.136     0.803    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5_n_0
    SLICE_X114Y122       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.014     0.817 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.017     0.834    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.487     1.634    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.871ns  (logic 0.309ns (35.476%)  route 0.562ns (64.524%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.294     0.521    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[10]
    SLICE_X114Y114       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.014     0.535 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_10/O
                         net (fo=1, routed)           0.070     0.605    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_10_n_0
    SLICE_X113Y114       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.035     0.640 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/O
                         net (fo=1, routed)           0.192     0.832    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3_n_0
    SLICE_X111Y127       LUT5 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.033     0.865 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.006     0.871    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.907ns  (logic 0.400ns (44.101%)  route 0.507ns (55.899%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.638ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.638ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.491ns (routing 0.405ns, distribution 1.086ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.213     0.463    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[15]
    SLICE_X118Y113       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.051     0.514 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52/O
                         net (fo=1, routed)           0.097     0.611    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52_n_0
    SLICE_X116Y114       LUT5 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.036     0.647 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23/O
                         net (fo=1, routed)           0.129     0.776    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_n_0
    SLICE_X116Y121       LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.040     0.816 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.051     0.867    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X114Y121       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.023     0.890 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.017     0.907    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.491     1.638    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.939ns  (logic 0.401ns (42.705%)  route 0.538ns (57.295%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.214     0.451    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[8]
    SLICE_X117Y113       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.014     0.465 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26/O
                         net (fo=1, routed)           0.115     0.580    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26_n_0
    SLICE_X114Y115       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.050     0.630 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16/O
                         net (fo=1, routed)           0.025     0.655    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16_n_0
    SLICE_X114Y115       LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.040     0.695 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4/O
                         net (fo=1, routed)           0.169     0.864    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4_n_0
    SLICE_X111Y127       LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.060     0.924 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.015     0.939    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.959ns  (logic 0.350ns (36.496%)  route 0.609ns (63.504%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.230     0.458    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[9]
    SLICE_X117Y113       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.022     0.480 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_23/O
                         net (fo=1, routed)           0.162     0.642    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_23_n_0
    SLICE_X114Y119       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.014     0.656 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15/O
                         net (fo=1, routed)           0.022     0.678    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15_n_0
    SLICE_X114Y119       LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.036     0.714 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4/O
                         net (fo=1, routed)           0.179     0.893    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4_n_0
    SLICE_X111Y127       LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.050     0.943 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.016     0.959    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.096ns  (logic 0.396ns (36.131%)  route 0.700ns (63.869%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.274     0.539    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[11]
    SLICE_X115Y113       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.014     0.553 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_25/O
                         net (fo=1, routed)           0.146     0.699    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_25_n_0
    SLICE_X114Y115       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.059     0.758 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13/O
                         net (fo=1, routed)           0.072     0.830    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13_n_0
    SLICE_X114Y115       LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.036     0.866 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/O
                         net (fo=1, routed)           0.191     1.057    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3_n_0
    SLICE_X111Y127       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.022     1.079 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.017     1.096    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.157ns  (logic 0.454ns (39.239%)  route 0.703ns (60.761%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.637ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.637ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.490ns (routing 0.405ns, distribution 1.085ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.230     0.515    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[14]
    SLICE_X117Y116       LUT6 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.014     0.529 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_41/O
                         net (fo=1, routed)           0.104     0.633    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_41_n_0
    SLICE_X116Y114       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.060     0.693 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_20/O
                         net (fo=1, routed)           0.202     0.895    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_20_n_0
    SLICE_X117Y125       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.035     0.930 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.150     1.080    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X114Y127       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.060     1.140 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.017     1.157    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.490     1.637    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC2_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.651ns  (logic 1.279ns (48.246%)  route 1.372ns (51.754%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.597     1.295    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[14]
    SLICE_X117Y123       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.124     1.419 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_63/O
                         net (fo=1, routed)           0.135     1.554    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_63_n_0
    SLICE_X116Y123       LUT5 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.122     1.676 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46/O
                         net (fo=1, routed)           0.178     1.854    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46_n_0
    SLICE_X117Y125       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.089     1.943 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_21/O
                         net (fo=1, routed)           0.084     2.027    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_21_n_0
    SLICE_X117Y125       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.096     2.123 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.327     2.450    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X114Y127       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.150     2.600 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.051     2.651    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.560ns  (logic 1.171ns (45.742%)  route 1.389ns (54.258%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.668     1.456    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[8]
    SLICE_X111Y125       LUT5 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     1.491 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31/O
                         net (fo=1, routed)           0.185     1.676    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31_n_0
    SLICE_X111Y125       LUT6 (Prop_E6LUT_SLICEL_I5_O)
                                                      0.051     1.727 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_29/O
                         net (fo=1, routed)           0.177     1.904    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_29_n_0
    SLICE_X114Y127       LUT5 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.123     2.027 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19/O
                         net (fo=1, routed)           0.220     2.247    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19_n_0
    SLICE_X111Y127       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.123     2.370 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6/O
                         net (fo=1, routed)           0.090     2.460    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6_n_0
    SLICE_X111Y127       LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.051     2.511 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.049     2.560    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.348ns  (logic 1.140ns (48.552%)  route 1.208ns (51.448%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.664     1.196    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[9]
    SLICE_X114Y126       LUT5 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.123     1.319 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29/O
                         net (fo=1, routed)           0.058     1.377    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29_n_0
    SLICE_X114Y126       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.148     1.525 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_26/O
                         net (fo=1, routed)           0.095     1.620    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_26_n_0
    SLICE_X114Y128       LUT5 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.099     1.719 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_18/O
                         net (fo=1, routed)           0.057     1.776    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_18_n_0
    SLICE_X114Y128       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.148     1.924 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/O
                         net (fo=1, routed)           0.286     2.210    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6_n_0
    SLICE_X111Y127       LUT6 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.090     2.300 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.048     2.348    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.323ns  (logic 0.971ns (41.799%)  route 1.352ns (58.201%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.341ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.341ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.159ns (routing 0.599ns, distribution 1.560ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.649     1.260    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[12]
    SLICE_X111Y125       LUT5 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.036     1.296 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20/O
                         net (fo=1, routed)           0.197     1.493    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20_n_0
    SLICE_X111Y125       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.124     1.617 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_15/O
                         net (fo=1, routed)           0.368     1.985    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_15_n_0
    SLICE_X115Y122       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.150     2.135 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6/O
                         net (fo=1, routed)           0.089     2.224    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6_n_0
    SLICE_X114Y122       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.050     2.274 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.049     2.323    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.159     2.341    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.200ns  (logic 1.079ns (49.045%)  route 1.121ns (50.955%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.738     1.326    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[11]
    SLICE_X114Y126       LUT5 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.146     1.472 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_41/O
                         net (fo=1, routed)           0.043     1.515    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_41_n_0
    SLICE_X114Y126       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.097     1.612 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_31/O
                         net (fo=1, routed)           0.086     1.698    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_31_n_0
    SLICE_X114Y127       LUT5 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.035     1.733 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19/O
                         net (fo=1, routed)           0.157     1.890    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19_n_0
    SLICE_X111Y127       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.090     1.980 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                         net (fo=1, routed)           0.047     2.027    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    SLICE_X111Y127       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.123     2.150 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.050     2.200    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.121ns  (logic 1.042ns (49.128%)  route 1.079ns (50.872%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.600     1.136    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[10]
    SLICE_X116Y127       LUT5 (Prop_E6LUT_SLICEL_I3_O)
                                                      0.123     1.259 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29/O
                         net (fo=1, routed)           0.101     1.360    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29_n_0
    SLICE_X115Y127       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.145     1.505 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24/O
                         net (fo=1, routed)           0.085     1.590    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24_n_0
    SLICE_X115Y128       LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.052     1.642 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16/O
                         net (fo=1, routed)           0.046     1.688    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16_n_0
    SLICE_X115Y128       LUT6 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.053     1.741 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4/O
                         net (fo=1, routed)           0.232     1.973    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4_n_0
    SLICE_X111Y127       LUT5 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.133     2.106 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.015     2.121    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.975ns  (logic 1.003ns (50.785%)  route 0.972ns (49.215%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.341ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.341ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.159ns (routing 0.599ns, distribution 1.560ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.688     1.459    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[13]
    SLICE_X116Y123       LUT5 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.096     1.555 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_60/O
                         net (fo=1, routed)           0.044     1.599    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_60_n_0
    SLICE_X116Y122       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.036     1.635 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_27/O
                         net (fo=1, routed)           0.038     1.673    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_27_n_0
    SLICE_X116Y122       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.050     1.723 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7/O
                         net (fo=1, routed)           0.152     1.875    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7_n_0
    SLICE_X114Y122       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.050     1.925 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.050     1.975    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.159     2.341    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.921ns  (logic 0.823ns (42.842%)  route 1.098ns (57.158%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.343ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.343ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.161ns (routing 0.599ns, distribution 1.562ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.616     1.141    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[15]
    SLICE_X117Y123       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.122     1.263 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_47/O
                         net (fo=1, routed)           0.184     1.447    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_47_n_0
    SLICE_X116Y123       LUT5 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.036     1.483 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22/O
                         net (fo=1, routed)           0.147     1.630    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_n_0
    SLICE_X116Y121       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.089     1.719 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.100     1.819    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X114Y121       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.051     1.870 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.051     1.921    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.161     2.343    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.807ns  (logic 0.340ns (42.131%)  route 0.467ns (57.869%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.634ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.634ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.487ns (routing 0.405ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.333     0.574    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[13]
    SLICE_X116Y123       LUT5 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.040     0.614 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_60/O
                         net (fo=1, routed)           0.021     0.635    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_60_n_0
    SLICE_X116Y122       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.015     0.650 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_27/O
                         net (fo=1, routed)           0.021     0.671    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_27_n_0
    SLICE_X116Y122       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.022     0.693 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7/O
                         net (fo=1, routed)           0.075     0.768    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7_n_0
    SLICE_X114Y122       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.022     0.790 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.017     0.807    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.487     1.634    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.911ns  (logic 0.373ns (40.944%)  route 0.538ns (59.056%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.638ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.638ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.491ns (routing 0.405ns, distribution 1.086ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.304     0.554    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[15]
    SLICE_X117Y123       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.050     0.604 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_47/O
                         net (fo=1, routed)           0.093     0.697    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_47_n_0
    SLICE_X116Y123       LUT5 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.015     0.712 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22/O
                         net (fo=1, routed)           0.073     0.785    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_n_0
    SLICE_X116Y121       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.035     0.820 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.051     0.871    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X114Y121       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.023     0.894 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.017     0.911    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.491     1.638    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.968ns  (logic 0.429ns (44.318%)  route 0.539ns (55.682%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.293     0.520    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[10]
    SLICE_X116Y127       LUT5 (Prop_E6LUT_SLICEL_I3_O)
                                                      0.050     0.570 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29/O
                         net (fo=1, routed)           0.052     0.622    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29_n_0
    SLICE_X115Y127       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.059     0.681 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24/O
                         net (fo=1, routed)           0.046     0.727    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24_n_0
    SLICE_X115Y128       LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.022     0.749 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16/O
                         net (fo=1, routed)           0.025     0.774    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16_n_0
    SLICE_X115Y128       LUT6 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.023     0.797 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4/O
                         net (fo=1, routed)           0.117     0.914    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4_n_0
    SLICE_X111Y127       LUT5 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.048     0.962 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.006     0.968    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.015ns  (logic 0.463ns (45.616%)  route 0.552ns (54.384%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.357     0.622    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[11]
    SLICE_X114Y126       LUT5 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.059     0.681 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_41/O
                         net (fo=1, routed)           0.023     0.704    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_41_n_0
    SLICE_X114Y126       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.040     0.744 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_31/O
                         net (fo=1, routed)           0.047     0.791    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_31_n_0
    SLICE_X114Y127       LUT5 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.014     0.805 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19/O
                         net (fo=1, routed)           0.082     0.887    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19_n_0
    SLICE_X111Y127       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.035     0.922 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                         net (fo=1, routed)           0.026     0.948    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    SLICE_X111Y127       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.050     0.998 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.017     1.015    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.060ns  (logic 0.420ns (39.623%)  route 0.640ns (60.377%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.634ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.634ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.487ns (routing 0.405ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.317     0.591    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[12]
    SLICE_X111Y125       LUT5 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.014     0.605 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20/O
                         net (fo=1, routed)           0.097     0.702    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20_n_0
    SLICE_X111Y125       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.050     0.752 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_15/O
                         net (fo=1, routed)           0.162     0.914    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_15_n_0
    SLICE_X115Y122       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.060     0.974 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6/O
                         net (fo=1, routed)           0.048     1.022    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6_n_0
    SLICE_X114Y122       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.022     1.044 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.016     1.060    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.487     1.634    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.067ns  (logic 0.472ns (44.236%)  route 0.595ns (55.764%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.320     0.548    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[9]
    SLICE_X114Y126       LUT5 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.050     0.598 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29/O
                         net (fo=1, routed)           0.030     0.628    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29_n_0
    SLICE_X114Y126       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.059     0.687 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_26/O
                         net (fo=1, routed)           0.050     0.737    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_26_n_0
    SLICE_X114Y128       LUT5 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.041     0.778 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_18/O
                         net (fo=1, routed)           0.031     0.809    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_18_n_0
    SLICE_X114Y128       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.059     0.868 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/O
                         net (fo=1, routed)           0.148     1.016    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6_n_0
    SLICE_X111Y127       LUT6 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.035     1.051 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.016     1.067    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.076ns  (logic 0.396ns (36.803%)  route 0.680ns (63.197%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.327     0.564    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[8]
    SLICE_X111Y125       LUT5 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.014     0.578 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31/O
                         net (fo=1, routed)           0.092     0.670    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31_n_0
    SLICE_X111Y125       LUT6 (Prop_E6LUT_SLICEL_I5_O)
                                                      0.022     0.692 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_29/O
                         net (fo=1, routed)           0.092     0.784    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_29_n_0
    SLICE_X114Y127       LUT5 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.050     0.834 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19/O
                         net (fo=1, routed)           0.110     0.944    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19_n_0
    SLICE_X111Y127       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.050     0.994 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6/O
                         net (fo=1, routed)           0.044     1.038    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6_n_0
    SLICE_X111Y127       LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.023     1.061 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.015     1.076    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.182ns  (logic 0.520ns (43.993%)  route 0.662ns (56.007%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        1.637ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.637ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.490ns (routing 0.405ns, distribution 1.085ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.287     0.572    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[14]
    SLICE_X117Y123       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.050     0.622 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_63/O
                         net (fo=1, routed)           0.072     0.694    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_63_n_0
    SLICE_X116Y123       LUT5 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.050     0.744 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46/O
                         net (fo=1, routed)           0.094     0.838    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46_n_0
    SLICE_X117Y125       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.035     0.873 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_21/O
                         net (fo=1, routed)           0.042     0.915    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_21_n_0
    SLICE_X117Y125       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.040     0.955 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.150     1.105    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X114Y127       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.060     1.165 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.017     1.182    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.490     1.637    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC3_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.930ns  (logic 1.098ns (37.474%)  route 1.832ns (62.526%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           1.135     1.833    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[14]
    SLICE_X117Y132       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.050     1.883 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_38/O
                         net (fo=1, routed)           0.109     1.992    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_38_n_0
    SLICE_X117Y130       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.150     2.142 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19/O
                         net (fo=1, routed)           0.210     2.352    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19_n_0
    SLICE_X117Y125       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.050     2.402 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.327     2.729    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X114Y127       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.150     2.879 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.051     2.930    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.907ns  (logic 1.098ns (37.771%)  route 1.809ns (62.229%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.343ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.343ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.161ns (routing 0.599ns, distribution 1.562ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.980     1.505    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[15]
    SLICE_X118Y131       LUT4 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.125     1.630 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_84/O
                         net (fo=1, routed)           0.091     1.721    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_84_n_0
    SLICE_X118Y131       LUT5 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.098     1.819 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55/O
                         net (fo=1, routed)           0.106     1.925    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_n_0
    SLICE_X117Y131       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.150     2.075 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_25/O
                         net (fo=1, routed)           0.481     2.556    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_25_n_0
    SLICE_X116Y121       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.149     2.705 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.100     2.805    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X114Y121       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.051     2.856 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.051     2.907    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.161     2.343    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.850ns  (logic 1.109ns (38.912%)  route 1.741ns (61.088%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.341ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.341ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.159ns (routing 0.599ns, distribution 1.560ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           1.083     1.854    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[13]
    SLICE_X117Y129       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.089     1.943 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_37/O
                         net (fo=1, routed)           0.209     2.152    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_37_n_0
    SLICE_X114Y128       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.124     2.276 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_12/O
                         net (fo=1, routed)           0.089     2.365    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_12_n_0
    SLICE_X115Y128       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.037     2.402 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3/O
                         net (fo=1, routed)           0.310     2.712    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3_n_0
    SLICE_X114Y122       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.088     2.800 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.050     2.850    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.159     2.341    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.822ns  (logic 1.098ns (38.909%)  route 1.724ns (61.091%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.899     1.687    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[8]
    SLICE_X118Y135       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.148     1.835 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_28/O
                         net (fo=1, routed)           0.342     2.177    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_28_n_0
    SLICE_X114Y133       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.036     2.213 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_18/O
                         net (fo=1, routed)           0.096     2.309    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_18_n_0
    SLICE_X114Y132       LUT5 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.090     2.399 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                         net (fo=1, routed)           0.338     2.737    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    SLICE_X111Y127       LUT6 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.036     2.773 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.049     2.822    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.756ns  (logic 0.975ns (35.377%)  route 1.781ns (64.623%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           1.048     1.636    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[11]
    SLICE_X116Y134       LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.124     1.760 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_29/O
                         net (fo=1, routed)           0.090     1.850    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_29_n_0
    SLICE_X116Y133       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.124     1.974 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18/O
                         net (fo=1, routed)           0.144     2.118    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18_n_0
    SLICE_X116Y132       LUT5 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.051     2.169 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4/O
                         net (fo=1, routed)           0.449     2.618    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4_n_0
    SLICE_X111Y127       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.088     2.706 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.050     2.756    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.751ns  (logic 1.018ns (37.005%)  route 1.733ns (62.995%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           1.083     1.619    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[10]
    SLICE_X115Y131       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.098     1.717 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23/O
                         net (fo=1, routed)           0.246     1.963    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23_n_0
    SLICE_X115Y131       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.101     2.064 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13/O
                         net (fo=1, routed)           0.157     2.221    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13_n_0
    SLICE_X115Y128       LUT6 (Prop_A6LUT_SLICEM_I0_O)
                                                      0.150     2.371 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4/O
                         net (fo=1, routed)           0.232     2.603    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4_n_0
    SLICE_X111Y127       LUT5 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.133     2.736 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.015     2.751    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.594ns  (logic 0.894ns (34.464%)  route 1.700ns (65.536%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.341ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.341ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.159ns (routing 0.599ns, distribution 1.560ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           1.073     1.684    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[12]
    SLICE_X117Y129       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.088     1.772 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18/O
                         net (fo=1, routed)           0.227     1.999    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18_n_0
    SLICE_X116Y129       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.124     2.123 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_10/O
                         net (fo=1, routed)           0.039     2.162    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_10_n_0
    SLICE_X116Y129       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.035     2.197 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3/O
                         net (fo=1, routed)           0.312     2.509    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3_n_0
    SLICE_X114Y122       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.036     2.545 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.049     2.594    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.159     2.341    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.490ns  (logic 0.828ns (33.253%)  route 1.662ns (66.747%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.926     1.458    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[9]
    SLICE_X117Y134       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.099     1.557 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_25/O
                         net (fo=1, routed)           0.309     1.866    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_25_n_0
    SLICE_X114Y131       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.049     1.915 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_17/O
                         net (fo=1, routed)           0.087     2.002    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_17_n_0
    SLICE_X114Y131       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.050     2.052 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/O
                         net (fo=1, routed)           0.292     2.344    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5_n_0
    SLICE_X111Y127       LUT6 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.098     2.442 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.048     2.490    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.148ns  (logic 0.354ns (30.836%)  route 0.794ns (69.164%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.454     0.682    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[9]
    SLICE_X117Y134       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.041     0.723 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_25/O
                         net (fo=1, routed)           0.156     0.879    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_25_n_0
    SLICE_X114Y131       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.022     0.901 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_17/O
                         net (fo=1, routed)           0.041     0.942    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_17_n_0
    SLICE_X114Y131       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.022     0.964 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/O
                         net (fo=1, routed)           0.127     1.091    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5_n_0
    SLICE_X111Y127       LUT6 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.041     1.132 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.016     1.148    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.213ns  (logic 0.362ns (29.843%)  route 0.851ns (70.157%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.446     0.683    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[8]
    SLICE_X118Y135       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.059     0.742 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_28/O
                         net (fo=1, routed)           0.171     0.913    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_28_n_0
    SLICE_X114Y133       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.015     0.928 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_18/O
                         net (fo=1, routed)           0.051     0.979    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_18_n_0
    SLICE_X114Y132       LUT5 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.036     1.015 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                         net (fo=1, routed)           0.168     1.183    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    SLICE_X111Y127       LUT6 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.015     1.198 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.015     1.213    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.224ns  (logic 0.387ns (31.618%)  route 0.837ns (68.382%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.634ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.634ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.487ns (routing 0.405ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.526     0.800    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[12]
    SLICE_X117Y129       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.035     0.835 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18/O
                         net (fo=1, routed)           0.118     0.953    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18_n_0
    SLICE_X116Y129       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.050     1.003 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_10/O
                         net (fo=1, routed)           0.021     1.024    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_10_n_0
    SLICE_X116Y129       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.014     1.038 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3/O
                         net (fo=1, routed)           0.156     1.194    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3_n_0
    SLICE_X114Y122       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.014     1.208 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.016     1.224    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.487     1.634    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.246ns  (logic 0.375ns (30.096%)  route 0.871ns (69.904%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.634ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.634ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.487ns (routing 0.405ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.541     0.782    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[13]
    SLICE_X117Y129       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.035     0.817 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_37/O
                         net (fo=1, routed)           0.108     0.925    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_37_n_0
    SLICE_X114Y128       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.050     0.975 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_12/O
                         net (fo=1, routed)           0.048     1.023    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_12_n_0
    SLICE_X115Y128       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.014     1.037 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3/O
                         net (fo=1, routed)           0.157     1.194    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3_n_0
    SLICE_X114Y122       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.035     1.229 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.017     1.246    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.487     1.634    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.280ns  (logic 0.416ns (32.500%)  route 0.864ns (67.500%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.547     0.774    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[10]
    SLICE_X115Y131       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.040     0.814 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23/O
                         net (fo=1, routed)           0.114     0.928    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23_n_0
    SLICE_X115Y131       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.041     0.969 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13/O
                         net (fo=1, routed)           0.080     1.049    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13_n_0
    SLICE_X115Y128       LUT6 (Prop_A6LUT_SLICEM_I0_O)
                                                      0.060     1.109 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4/O
                         net (fo=1, routed)           0.117     1.226    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4_n_0
    SLICE_X111Y127       LUT5 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.048     1.274 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.006     1.280    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.314ns  (logic 0.423ns (32.192%)  route 0.891ns (67.808%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.523     0.788    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[11]
    SLICE_X116Y134       LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.050     0.838 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_29/O
                         net (fo=1, routed)           0.048     0.886    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_29_n_0
    SLICE_X116Y133       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.050     0.936 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18/O
                         net (fo=1, routed)           0.073     1.009    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18_n_0
    SLICE_X116Y132       LUT5 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.023     1.032 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4/O
                         net (fo=1, routed)           0.230     1.262    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4_n_0
    SLICE_X111Y127       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.035     1.297 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.017     1.314    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.324ns  (logic 0.449ns (33.912%)  route 0.875ns (66.088%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.637ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.637ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.490ns (routing 0.405ns, distribution 1.085ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.546     0.831    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[14]
    SLICE_X117Y132       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.022     0.853 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_38/O
                         net (fo=1, routed)           0.056     0.909    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_38_n_0
    SLICE_X117Y130       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.060     0.969 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19/O
                         net (fo=1, routed)           0.106     1.075    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19_n_0
    SLICE_X117Y125       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.022     1.097 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.150     1.247    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X114Y127       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.060     1.307 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.017     1.324    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.490     1.637    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.390ns  (logic 0.483ns (34.748%)  route 0.907ns (65.252%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.638ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.638ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.491ns (routing 0.405ns, distribution 1.086ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.486     0.736    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[15]
    SLICE_X118Y131       LUT4 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.050     0.786 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_84/O
                         net (fo=1, routed)           0.044     0.830    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_84_n_0
    SLICE_X118Y131       LUT5 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.040     0.870 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55/O
                         net (fo=1, routed)           0.057     0.927    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_n_0
    SLICE_X117Y131       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.060     0.987 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_25/O
                         net (fo=1, routed)           0.252     1.239    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_25_n_0
    SLICE_X116Y121       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.060     1.299 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.051     1.350    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X114Y121       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.023     1.373 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.017     1.390    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.491     1.638    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  clk_pl_0

Max Delay            10 Endpoints
Min Delay            10 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.082ns  (logic 0.219ns (7.106%)  route 2.863ns (92.894%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -1.234ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.350ns
    Source Clock Delay      (SCD):    3.584ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.911ns (routing 1.381ns, distribution 1.530ns)
  Clock Net Delay (Destination): 2.168ns (routing 0.599ns, distribution 1.569ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.911     3.584    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.663 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.402     5.065    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.093 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       1.438     6.531    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/src_in
    SLICE_X115Y165       LUT1 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.112     6.643 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.023     6.666    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X115Y165       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.168     2.350    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/dest_clk
    SLICE_X115Y165       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.078ns  (logic 0.219ns (7.115%)  route 2.859ns (92.885%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -1.248ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.336ns
    Source Clock Delay      (SCD):    3.584ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.911ns (routing 1.381ns, distribution 1.530ns)
  Clock Net Delay (Destination): 2.154ns (routing 0.599ns, distribution 1.555ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.911     3.584    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.663 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.402     5.065    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.093 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       1.434     6.527    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/src_in
    SLICE_X113Y161       LUT1 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.112     6.639 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.023     6.662    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X113Y161       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.154     2.336    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/dest_clk
    SLICE_X113Y161       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.277ns  (logic 1.378ns (32.219%)  route 2.899ns (67.781%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.341ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.341ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.159ns (routing 0.599ns, distribution 1.560ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      1.059     1.059 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           1.861     2.920    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[13]
    SLICE_X105Y137       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.036     2.956 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_33/O
                         net (fo=1, routed)           0.043     2.999    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_33_n_0
    SLICE_X105Y137       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.097     3.096 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10/O
                         net (fo=1, routed)           0.559     3.655    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10_n_0
    SLICE_X109Y133       LUT5 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.090     3.745 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.386     4.131    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X114Y122       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     4.227 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.050     4.277    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.159     2.341    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.255ns  (logic 1.034ns (24.301%)  route 3.221ns (75.699%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           1.941     2.694    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[11]
    SLICE_X105Y137       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.036     2.730 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_48/O
                         net (fo=1, routed)           0.219     2.949    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_48_n_0
    SLICE_X102Y137       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.036     2.985 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39/O
                         net (fo=1, routed)           0.563     3.548    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39_n_0
    SLICE_X108Y137       LUT5 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.050     3.598 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_23/O
                         net (fo=1, routed)           0.217     3.815    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_23_n_0
    SLICE_X108Y129       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.124     3.939 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6/O
                         net (fo=1, routed)           0.231     4.170    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_n_0
    SLICE_X111Y127       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.035     4.205 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.050     4.255    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.183ns  (logic 1.176ns (28.114%)  route 3.007ns (71.886%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.343ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.343ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.161ns (routing 0.599ns, distribution 1.562ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.840     0.840 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           1.681     2.521    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[15]
    SLICE_X105Y137       LUT4 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.123     2.644 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_65/O
                         net (fo=1, routed)           0.130     2.774    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_65_n_0
    SLICE_X106Y137       LUT5 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     2.809 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31/O
                         net (fo=1, routed)           0.771     3.580    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_n_0
    SLICE_X113Y136       LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.051     3.631 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11/O
                         net (fo=1, routed)           0.042     3.673    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11_n_0
    SLICE_X113Y136       LUT6 (Prop_E6LUT_SLICEM_I5_O)
                                                      0.091     3.764 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.332     4.096    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X114Y121       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.036     4.132 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.051     4.183    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.161     2.343    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.130ns  (logic 1.261ns (30.533%)  route 2.869ns (69.467%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.731     0.731 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           1.711     2.442    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[8]
    SLICE_X108Y137       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.124     2.566 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_30/O
                         net (fo=1, routed)           0.396     2.962    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_30_n_0
    SLICE_X106Y137       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.149     3.111 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21/O
                         net (fo=1, routed)           0.044     3.155    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21_n_0
    SLICE_X106Y137       LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.097     3.252 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_8/O
                         net (fo=1, routed)           0.039     3.291    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_8_n_0
    SLICE_X106Y137       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.036     3.327 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.630     3.957    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X111Y127       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.124     4.081 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.049     4.130    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.950ns  (logic 1.194ns (30.228%)  route 2.756ns (69.772%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.674     0.674 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           1.702     2.376    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[9]
    SLICE_X105Y133       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.090     2.466 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27/O
                         net (fo=1, routed)           0.047     2.513    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27_n_0
    SLICE_X105Y133       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.123     2.636 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_19/O
                         net (fo=1, routed)           0.225     2.861    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_19_n_0
    SLICE_X106Y136       LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.123     2.984 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_9/O
                         net (fo=1, routed)           0.244     3.228    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_9_n_0
    SLICE_X106Y127       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.035     3.263 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.490     3.753    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X111Y127       LUT6 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.149     3.902 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.048     3.950    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.873ns  (logic 1.172ns (30.261%)  route 2.701ns (69.739%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.341ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.341ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.159ns (routing 0.599ns, distribution 1.560ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.759     0.759 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           1.470     2.229    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[12]
    SLICE_X109Y137       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.148     2.377 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_17/O
                         net (fo=1, routed)           0.451     2.828    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_17_n_0
    SLICE_X107Y134       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.053     2.881 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9/O
                         net (fo=1, routed)           0.192     3.073    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9_n_0
    SLICE_X105Y134       LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.123     3.196 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.539     3.735    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X114Y122       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.089     3.824 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.049     3.873    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.159     2.341    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.628ns  (logic 1.079ns (29.741%)  route 2.549ns (70.259%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           1.631     2.384    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[10]
    SLICE_X107Y137       LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.091     2.475 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_26/O
                         net (fo=1, routed)           0.220     2.695    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_26_n_0
    SLICE_X107Y137       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.039     2.734 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_17/O
                         net (fo=1, routed)           0.163     2.897    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_17_n_0
    SLICE_X107Y131       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     2.936 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.520     3.456    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X111Y127       LUT5 (Prop_D5LUT_SLICEL_I4_O)
                                                      0.157     3.613 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.015     3.628    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.205ns  (logic 1.027ns (32.044%)  route 2.178ns (67.956%))
  Logic Levels:           4  (LUT3=1 LUT6=3)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.779     0.779 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           1.579     2.358    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[14]
    SLICE_X108Y135       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.036     2.394 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_27/O
                         net (fo=1, routed)           0.037     2.431    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_27_n_0
    SLICE_X108Y135       LUT3 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.051     2.482 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9/O
                         net (fo=1, routed)           0.292     2.774    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9_n_0
    SLICE_X113Y135       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.125     2.899 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.219     3.118    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X114Y127       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.036     3.154 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.051     3.205    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.591ns  (logic 0.501ns (31.490%)  route 1.090ns (68.510%))
  Logic Levels:           4  (LUT3=1 LUT6=3)
  Clock Path Skew:        1.637ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.637ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.490ns (routing 0.405ns, distribution 1.085ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.398     0.398 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           0.793     1.191    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[14]
    SLICE_X108Y135       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.014     1.205 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_27/O
                         net (fo=1, routed)           0.021     1.226    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_27_n_0
    SLICE_X108Y135       LUT3 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.023     1.249 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9/O
                         net (fo=1, routed)           0.147     1.396    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9_n_0
    SLICE_X113Y135       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.051     1.447 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.112     1.559    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X114Y127       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.015     1.574 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.017     1.591    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.490     1.637    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.785ns  (logic 0.497ns (27.843%)  route 1.288ns (72.157%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.375     0.375 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           0.820     1.195    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[10]
    SLICE_X107Y137       LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.035     1.230 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_26/O
                         net (fo=1, routed)           0.111     1.341    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_26_n_0
    SLICE_X107Y137       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.015     1.356 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_17/O
                         net (fo=1, routed)           0.087     1.443    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_17_n_0
    SLICE_X107Y131       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.015     1.458 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.264     1.722    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X111Y127       LUT5 (Prop_D5LUT_SLICEL_I4_O)
                                                      0.057     1.779 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.006     1.785    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.913ns  (logic 0.553ns (28.907%)  route 1.360ns (71.093%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.634ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.634ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.487ns (routing 0.405ns, distribution 1.082ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.386     0.386 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           0.731     1.117    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[12]
    SLICE_X109Y137       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.059     1.176 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_17/O
                         net (fo=1, routed)           0.237     1.413    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_17_n_0
    SLICE_X107Y134       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.023     1.436 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9/O
                         net (fo=1, routed)           0.101     1.537    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9_n_0
    SLICE_X105Y134       LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.050     1.587 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.275     1.862    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X114Y122       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.035     1.897 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.016     1.913    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.487     1.634    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.915ns  (logic 0.547ns (28.564%)  route 1.368ns (71.436%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.338     0.338 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           0.856     1.194    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[9]
    SLICE_X105Y133       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.035     1.229 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27/O
                         net (fo=1, routed)           0.026     1.255    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27_n_0
    SLICE_X105Y133       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.050     1.305 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_19/O
                         net (fo=1, routed)           0.121     1.426    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_19_n_0
    SLICE_X106Y136       LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.050     1.476 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_9/O
                         net (fo=1, routed)           0.131     1.607    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_9_n_0
    SLICE_X106Y127       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.014     1.621 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.218     1.839    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X111Y127       LUT6 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.060     1.899 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.016     1.915    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.035ns  (logic 0.597ns (29.337%)  route 1.438ns (70.663%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.382     0.382 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           0.863     1.245    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[8]
    SLICE_X108Y137       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.050     1.295 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_30/O
                         net (fo=1, routed)           0.186     1.481    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_30_n_0
    SLICE_X106Y137       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.060     1.541 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21/O
                         net (fo=1, routed)           0.025     1.566    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21_n_0
    SLICE_X106Y137       LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.040     1.606 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_8/O
                         net (fo=1, routed)           0.021     1.627    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_8_n_0
    SLICE_X106Y137       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.015     1.642 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.328     1.970    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X111Y127       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.050     2.020 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.015     2.035    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.090ns  (logic 0.549ns (26.268%)  route 1.541ns (73.732%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.638ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.638ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.491ns (routing 0.405ns, distribution 1.086ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.413     0.413 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           0.856     1.269    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[15]
    SLICE_X105Y137       LUT4 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.050     1.319 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_65/O
                         net (fo=1, routed)           0.071     1.390    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_65_n_0
    SLICE_X106Y137       LUT5 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.014     1.404 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31/O
                         net (fo=1, routed)           0.403     1.807    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_n_0
    SLICE_X113Y136       LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.022     1.829 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11/O
                         net (fo=1, routed)           0.024     1.853    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11_n_0
    SLICE_X113Y136       LUT6 (Prop_E6LUT_SLICEM_I5_O)
                                                      0.035     1.888 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.170     2.058    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X114Y121       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.015     2.073 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.017     2.090    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.491     1.638    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.103ns  (logic 0.653ns (31.051%)  route 1.450ns (68.949%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.634ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.634ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.487ns (routing 0.405ns, distribution 1.082ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.524     0.524 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           0.938     1.462    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[13]
    SLICE_X105Y137       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.014     1.476 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_33/O
                         net (fo=1, routed)           0.023     1.499    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_33_n_0
    SLICE_X105Y137       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.040     1.539 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10/O
                         net (fo=1, routed)           0.272     1.811    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10_n_0
    SLICE_X109Y133       LUT5 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.035     1.846 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.200     2.046    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X114Y122       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.040     2.086 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.017     2.103    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.487     1.634    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.104ns  (logic 0.483ns (22.956%)  route 1.621ns (77.044%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.367     0.367 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           0.973     1.340    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[11]
    SLICE_X105Y137       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.015     1.355 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_48/O
                         net (fo=1, routed)           0.113     1.468    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_48_n_0
    SLICE_X102Y137       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.015     1.483 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39/O
                         net (fo=1, routed)           0.292     1.775    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39_n_0
    SLICE_X108Y137       LUT5 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.022     1.797 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_23/O
                         net (fo=1, routed)           0.110     1.907    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_23_n_0
    SLICE_X108Y129       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.050     1.957 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6/O
                         net (fo=1, routed)           0.116     2.073    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_n_0
    SLICE_X111Y127       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.014     2.087 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.017     2.104    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.629ns  (logic 0.095ns (5.832%)  route 1.534ns (94.168%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.309ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.634ns
    Source Clock Delay      (SCD):    1.943ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.594ns (routing 0.748ns, distribution 0.846ns)
  Clock Net Delay (Destination): 1.487ns (routing 0.405ns, distribution 1.082ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.594     1.943    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.982 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.730     2.712    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.729 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       0.797     3.526    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/src_in
    SLICE_X113Y161       LUT1 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.039     3.565 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.007     3.572    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X113Y161       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.487     1.634    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/dest_clk
    SLICE_X113Y161       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.631ns  (logic 0.095ns (5.825%)  route 1.536ns (94.175%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.299ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.644ns
    Source Clock Delay      (SCD):    1.943ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.594ns (routing 0.748ns, distribution 0.846ns)
  Clock Net Delay (Destination): 1.497ns (routing 0.405ns, distribution 1.092ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.594     1.943    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X74Y320        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.982 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.730     2.712    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y97         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.729 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29231, routed)       0.799     3.528    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/src_in
    SLICE_X115Y165       LUT1 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.039     3.567 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.007     3.574    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X115Y165       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.497     1.644    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/dest_clk
    SLICE_X115Y165       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC1_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.886ns  (logic 1.063ns (21.756%)  route 3.823ns (78.244%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.674     0.674 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           2.045     2.719    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[9]
    SLICE_X110Y133       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.051     2.770 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_28/O
                         net (fo=1, routed)           0.446     3.216    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_28_n_0
    SLICE_X106Y135       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.051     3.267 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20/O
                         net (fo=1, routed)           0.334     3.601    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20_n_0
    SLICE_X108Y136       LUT6 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.049     3.650 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_10/O
                         net (fo=1, routed)           0.460     4.110    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_10_n_0
    SLICE_X106Y127       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.089     4.199 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.490     4.689    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X111Y127       LUT6 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.149     4.838 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.048     4.886    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.675ns  (logic 1.382ns (29.561%)  route 3.293ns (70.439%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.341ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.341ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.159ns (routing 0.599ns, distribution 1.560ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.759     0.759 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           2.032     2.791    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[12]
    SLICE_X113Y138       LUT4 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.150     2.941 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21/O
                         net (fo=1, routed)           0.475     3.416    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21_n_0
    SLICE_X106Y134       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.089     3.505 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_16/O
                         net (fo=1, routed)           0.051     3.556    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_16_n_0
    SLICE_X106Y134       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.146     3.702 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_8/O
                         net (fo=1, routed)           0.147     3.849    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_8_n_0
    SLICE_X105Y134       LUT5 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.149     3.998 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.539     4.537    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X114Y122       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.089     4.626 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.049     4.675    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.159     2.341    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.308ns  (logic 1.081ns (25.093%)  route 3.227ns (74.907%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           2.207     2.960    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[11]
    SLICE_X106Y134       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.124     3.084 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_46/O
                         net (fo=1, routed)           0.083     3.167    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_46_n_0
    SLICE_X106Y133       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.036     3.203 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35/O
                         net (fo=1, routed)           0.453     3.656    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35_n_0
    SLICE_X108Y136       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.097     3.753 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22/O
                         net (fo=1, routed)           0.203     3.956    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22_n_0
    SLICE_X108Y129       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.036     3.992 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6/O
                         net (fo=1, routed)           0.231     4.223    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_n_0
    SLICE_X111Y127       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.035     4.258 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.050     4.308    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.298ns  (logic 1.433ns (33.341%)  route 2.865ns (66.659%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.341ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.341ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.159ns (routing 0.599ns, distribution 1.560ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      1.059     1.059 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           2.010     3.069    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[13]
    SLICE_X114Y134       LUT4 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.089     3.158 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_62/O
                         net (fo=1, routed)           0.285     3.443    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_62_n_0
    SLICE_X109Y134       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.051     3.494 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31/O
                         net (fo=1, routed)           0.045     3.539    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31_n_0
    SLICE_X109Y134       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.101     3.640 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_9/O
                         net (fo=1, routed)           0.089     3.729    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_9_n_0
    SLICE_X109Y133       LUT5 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.037     3.766 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.386     4.152    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X114Y122       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     4.248 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.050     4.298    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.159     2.341    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.271ns  (logic 1.236ns (28.939%)  route 3.035ns (71.061%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           1.918     2.671    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[10]
    SLICE_X108Y136       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.123     2.794 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_28/O
                         net (fo=1, routed)           0.108     2.902    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_28_n_0
    SLICE_X108Y136       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.150     3.052 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_18/O
                         net (fo=1, routed)           0.474     3.526    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_18_n_0
    SLICE_X107Y131       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.053     3.579 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.520     4.099    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X111Y127       LUT5 (Prop_D5LUT_SLICEL_I4_O)
                                                      0.157     4.256 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.015     4.271    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.255ns  (logic 1.130ns (26.557%)  route 3.125ns (73.443%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.731     0.731 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           1.842     2.573    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[8]
    SLICE_X113Y138       LUT4 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.148     2.721 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22/O
                         net (fo=1, routed)           0.512     3.233    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22_n_0
    SLICE_X107Y137       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.037     3.270 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_10/O
                         net (fo=1, routed)           0.092     3.362    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_10_n_0
    SLICE_X106Y137       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.090     3.452 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.630     4.082    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X111Y127       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.124     4.206 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.049     4.255    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.237ns  (logic 1.365ns (32.216%)  route 2.872ns (67.784%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        2.343ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.343ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.161ns (routing 0.599ns, distribution 1.562ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.840     0.840 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           2.039     2.879    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[15]
    SLICE_X109Y134       LUT5 (Prop_E6LUT_SLICEM_I1_O)
                                                      0.091     2.970 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_59/O
                         net (fo=1, routed)           0.059     3.029    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_59_n_0
    SLICE_X109Y134       LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.148     3.177 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28/O
                         net (fo=1, routed)           0.343     3.520    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_n_0
    SLICE_X113Y136       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.150     3.670 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_10/O
                         net (fo=1, routed)           0.048     3.718    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_10_n_0
    SLICE_X113Y136       LUT6 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.100     3.818 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.332     4.150    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X114Y121       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.036     4.186 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.051     4.237    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.161     2.343    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.196ns  (logic 1.177ns (28.051%)  route 3.019ns (71.949%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        2.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.779     0.779 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           1.976     2.755    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[14]
    SLICE_X114Y134       LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.149     2.904 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_50/O
                         net (fo=1, routed)           0.370     3.274    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_50_n_0
    SLICE_X109Y134       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.037     3.311 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24/O
                         net (fo=1, routed)           0.355     3.666    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24_n_0
    SLICE_X113Y135       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.123     3.789 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_8/O
                         net (fo=1, routed)           0.048     3.837    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_8_n_0
    SLICE_X113Y135       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.053     3.890 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.219     4.109    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X114Y127       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.036     4.145 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.051     4.196    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.073ns  (logic 0.622ns (30.005%)  route 1.451ns (69.995%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        1.638ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.638ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.491ns (routing 0.405ns, distribution 1.086ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.413     0.413 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           1.032     1.445    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[15]
    SLICE_X109Y134       LUT5 (Prop_E6LUT_SLICEM_I1_O)
                                                      0.035     1.480 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_59/O
                         net (fo=1, routed)           0.033     1.513    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_59_n_0
    SLICE_X109Y134       LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.059     1.572 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28/O
                         net (fo=1, routed)           0.173     1.745    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_n_0
    SLICE_X113Y136       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.060     1.805 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_10/O
                         net (fo=1, routed)           0.026     1.831    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_10_n_0
    SLICE_X113Y136       LUT6 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.040     1.871 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.170     2.041    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X114Y121       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.015     2.056 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.017     2.073    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.491     1.638    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.074ns  (logic 0.560ns (27.001%)  route 1.514ns (72.999%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        1.637ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.637ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.490ns (routing 0.405ns, distribution 1.085ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.398     0.398 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           0.997     1.395    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[14]
    SLICE_X114Y134       LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.060     1.455 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_50/O
                         net (fo=1, routed)           0.185     1.640    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_50_n_0
    SLICE_X109Y134       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.014     1.654 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24/O
                         net (fo=1, routed)           0.176     1.830    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24_n_0
    SLICE_X113Y135       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.050     1.880 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_8/O
                         net (fo=1, routed)           0.027     1.907    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_8_n_0
    SLICE_X113Y135       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.023     1.930 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.112     2.042    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X114Y127       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.015     2.057 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.017     2.074    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.490     1.637    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.100ns  (logic 0.565ns (26.905%)  route 1.535ns (73.095%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.375     0.375 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           0.963     1.338    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[10]
    SLICE_X108Y136       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.050     1.388 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_28/O
                         net (fo=1, routed)           0.053     1.441    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_28_n_0
    SLICE_X108Y136       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.060     1.501 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_18/O
                         net (fo=1, routed)           0.249     1.750    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_18_n_0
    SLICE_X107Y131       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.023     1.773 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.264     2.037    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X111Y127       LUT5 (Prop_D5LUT_SLICEL_I4_O)
                                                      0.057     2.094 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.006     2.100    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.107ns  (logic 0.676ns (32.084%)  route 1.431ns (67.916%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.634ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.634ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.487ns (routing 0.405ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.524     0.524 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           1.017     1.541    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[13]
    SLICE_X114Y134       LUT4 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     1.576 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_62/O
                         net (fo=1, routed)           0.124     1.700    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_62_n_0
    SLICE_X109Y134       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.022     1.722 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31/O
                         net (fo=1, routed)           0.025     1.747    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31_n_0
    SLICE_X109Y134       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.041     1.788 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_9/O
                         net (fo=1, routed)           0.048     1.836    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_9_n_0
    SLICE_X109Y133       LUT5 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.014     1.850 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.200     2.050    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X114Y122       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.040     2.090 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.017     2.107    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.487     1.634    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.118ns  (logic 0.501ns (23.654%)  route 1.617ns (76.346%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.367     0.367 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           1.117     1.484    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[11]
    SLICE_X106Y134       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.050     1.534 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_46/O
                         net (fo=1, routed)           0.045     1.579    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_46_n_0
    SLICE_X106Y133       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.015     1.594 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35/O
                         net (fo=1, routed)           0.217     1.811    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35_n_0
    SLICE_X108Y136       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.040     1.851 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22/O
                         net (fo=1, routed)           0.105     1.956    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22_n_0
    SLICE_X108Y129       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.015     1.971 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6/O
                         net (fo=1, routed)           0.116     2.087    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_n_0
    SLICE_X111Y127       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.014     2.101 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.017     2.118    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.124ns  (logic 0.540ns (25.424%)  route 1.584ns (74.576%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.382     0.382 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           0.929     1.311    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[8]
    SLICE_X113Y138       LUT4 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.059     1.370 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22/O
                         net (fo=1, routed)           0.263     1.633    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22_n_0
    SLICE_X107Y137       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.014     1.647 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_10/O
                         net (fo=1, routed)           0.049     1.696    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_10_n_0
    SLICE_X106Y137       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.035     1.731 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.328     2.059    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X111Y127       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.050     2.109 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.015     2.124    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.310ns  (logic 0.635ns (27.489%)  route 1.675ns (72.511%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.634ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.634ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.487ns (routing 0.405ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.386     0.386 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           1.023     1.409    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[12]
    SLICE_X113Y138       LUT4 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.060     1.469 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21/O
                         net (fo=1, routed)           0.255     1.724    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21_n_0
    SLICE_X106Y134       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.035     1.759 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_16/O
                         net (fo=1, routed)           0.029     1.788    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_16_n_0
    SLICE_X106Y134       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.059     1.847 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_8/O
                         net (fo=1, routed)           0.077     1.924    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_8_n_0
    SLICE_X105Y134       LUT5 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.060     1.984 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.275     2.259    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X114Y122       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.035     2.294 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.016     2.310    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.487     1.634    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.376ns  (logic 0.500ns (21.044%)  route 1.876ns (78.956%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.338     0.338 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           1.017     1.355    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[9]
    SLICE_X110Y133       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.022     1.377 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_28/O
                         net (fo=1, routed)           0.231     1.608    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_28_n_0
    SLICE_X106Y135       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.023     1.631 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20/O
                         net (fo=1, routed)           0.165     1.796    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20_n_0
    SLICE_X108Y136       LUT6 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.022     1.818 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_10/O
                         net (fo=1, routed)           0.229     2.047    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_10_n_0
    SLICE_X106Y127       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.035     2.082 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.218     2.300    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X111Y127       LUT6 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.060     2.360 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.016     2.376    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y127       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  clk_pl_0

Max Delay           269 Endpoints
Min Delay           269 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
                            (rising edge-triggered cell HSADC clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.626ns  (logic 0.678ns (25.819%)  route 1.948ns (74.181%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        -2.832ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    5.180ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.621ns (routing 0.878ns, distribution 1.743ns)
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.621     5.180    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m0_axis_aclk
    HSADC_X0Y0           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_FABRIC_CLK_STATUS_COMMON[5])
                                                      0.450     5.630 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[5]
                         net (fo=1, routed)           1.313     6.943    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[5]
    SLICE_X111Y113       LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.050     6.993 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_12/O
                         net (fo=1, routed)           0.147     7.140    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_12_n_0
    SLICE_X109Y113       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.090     7.230 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_4/O
                         net (fo=1, routed)           0.438     7.668    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_4_n_0
    SLICE_X111Y124       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.088     7.756 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.050     7.806    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X111Y124       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y124       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.951ns  (logic 0.076ns (3.895%)  route 1.875ns (96.105%))
  Logic Levels:           0  
  Clock Path Skew:        -2.514ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.336ns
    Source Clock Delay      (SCD):    4.850ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.291ns (routing 0.878ns, distribution 1.413ns)
  Clock Net Delay (Destination): 2.154ns (routing 0.599ns, distribution 1.555ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.291     4.850    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X78Y118        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y118        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.926 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           1.875     6.801    d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/src_in
    SLICE_X111Y137       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.154     2.336    d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/dest_clk
    SLICE_X111Y137       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.378ns  (logic 0.076ns (5.513%)  route 1.302ns (94.487%))
  Logic Levels:           0  
  Clock Path Skew:        -2.539ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.311ns
    Source Clock Delay      (SCD):    4.850ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.291ns (routing 0.878ns, distribution 1.413ns)
  Clock Net Delay (Destination): 2.129ns (routing 0.599ns, distribution 1.530ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.291     4.850    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X78Y118        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y118        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.926 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           1.302     6.228    d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/src_in
    SLICE_X105Y108       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.129     2.311    d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/dest_clk
    SLICE_X105Y108       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.352ns  (logic 0.081ns (23.011%)  route 0.271ns (76.989%))
  Logic Levels:           0  
  Clock Path Skew:        -2.693ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.128ns
    Source Clock Delay      (SCD):    4.821ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.262ns (routing 0.878ns, distribution 1.384ns)
  Clock Net Delay (Destination): 1.946ns (routing 0.599ns, distribution 1.347ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.262     4.821    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X73Y105        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y105        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     4.902 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.271     5.173    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X73Y105        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.946     2.128    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X73Y105        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.244ns  (logic 0.077ns (31.552%)  route 0.167ns (68.448%))
  Logic Levels:           0  
  Clock Path Skew:        -2.691ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.124ns
    Source Clock Delay      (SCD):    4.815ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.256ns (routing 0.878ns, distribution 1.378ns)
  Clock Net Delay (Destination): 1.942ns (routing 0.599ns, distribution 1.343ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.256     4.815    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X75Y89         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y89         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     4.892 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.167     5.059    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X75Y89         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.942     2.124    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X75Y89         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[47]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.029ns  (logic 0.307ns (29.835%)  route 0.722ns (70.165%))
  Logic Levels:           0  
  Clock Path Skew:        -2.913ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.043ns
    Source Clock Delay      (SCD):    4.956ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.397ns (routing 0.878ns, distribution 1.519ns)
  Clock Net Delay (Destination): 1.861ns (routing 0.599ns, distribution 1.262ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.397     4.956    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/WCLK
    SLICE_X53Y113        RAMD32                                       r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y113        RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.307     5.263 r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMC_D1/O
                         net (fo=1, routed)           0.722     5.985    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[47]
    SLICE_X55Y114        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[47]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.861     2.043    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X55Y114        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[47]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[58]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.029ns  (logic 0.292ns (28.377%)  route 0.737ns (71.623%))
  Logic Levels:           0  
  Clock Path Skew:        -2.901ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.047ns
    Source Clock Delay      (SCD):    4.948ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.389ns (routing 0.878ns, distribution 1.511ns)
  Clock Net Delay (Destination): 1.865ns (routing 0.599ns, distribution 1.266ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.389     4.948    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/WCLK
    SLICE_X54Y113        RAMD32                                       r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y113        RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292     5.240 r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMB/O
                         net (fo=1, routed)           0.737     5.977    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[58]
    SLICE_X54Y116        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[58]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.865     2.047    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X54Y116        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[58]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMC/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[60]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.989ns  (logic 0.288ns (29.120%)  route 0.701ns (70.880%))
  Logic Levels:           0  
  Clock Path Skew:        -2.892ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.033ns
    Source Clock Delay      (SCD):    4.925ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.366ns (routing 0.878ns, distribution 1.488ns)
  Clock Net Delay (Destination): 1.851ns (routing 0.599ns, distribution 1.252ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.366     4.925    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/WCLK
    SLICE_X56Y93         RAMD32                                       r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMC/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y93         RAMD32 (Prop_C5LUT_SLICEM_CLK_O)
                                                      0.288     5.213 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMC/O
                         net (fo=1, routed)           0.701     5.914    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[60]
    SLICE_X56Y95         FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[60]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.851     2.033    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X56Y95         FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[60]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[44]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.924ns  (logic 0.292ns (31.602%)  route 0.632ns (68.398%))
  Logic Levels:           0  
  Clock Path Skew:        -2.909ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.047ns
    Source Clock Delay      (SCD):    4.956ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.397ns (routing 0.878ns, distribution 1.519ns)
  Clock Net Delay (Destination): 1.865ns (routing 0.599ns, distribution 1.266ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.397     4.956    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/WCLK
    SLICE_X53Y113        RAMD32                                       r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y113        RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292     5.248 r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMB/O
                         net (fo=1, routed)           0.632     5.880    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[44]
    SLICE_X54Y116        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[44]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.865     2.047    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X54Y116        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[44]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMD/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[62]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.889ns  (logic 0.287ns (32.283%)  route 0.602ns (67.717%))
  Logic Levels:           0  
  Clock Path Skew:        -2.902ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.046ns
    Source Clock Delay      (SCD):    4.948ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.389ns (routing 0.878ns, distribution 1.511ns)
  Clock Net Delay (Destination): 1.864ns (routing 0.599ns, distribution 1.265ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.389     4.948    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/WCLK
    SLICE_X54Y113        RAMD32                                       r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMD/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y113        RAMD32 (Prop_D5LUT_SLICEM_CLK_O)
                                                      0.287     5.235 r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMD/O
                         net (fo=1, routed)           0.602     5.837    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[62]
    SLICE_X54Y114        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[62]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.864     2.046    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X54Y114        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[62]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.038ns (38.453%)  route 0.061ns (61.547%))
  Logic Levels:           0  
  Clock Path Skew:        -1.432ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.502ns
    Source Clock Delay      (SCD):    2.934ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.249ns (routing 0.484ns, distribution 0.765ns)
  Clock Net Delay (Destination): 1.355ns (routing 0.405ns, distribution 0.950ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.249     2.934    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X75Y89         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y89         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.972 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.061     3.033    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X75Y89         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.355     1.502    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X75Y89         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.158ns  (logic 0.040ns (25.316%)  route 0.118ns (74.684%))
  Logic Levels:           0  
  Clock Path Skew:        -1.433ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.503ns
    Source Clock Delay      (SCD):    2.936ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.251ns (routing 0.484ns, distribution 0.767ns)
  Clock Net Delay (Destination): 1.356ns (routing 0.405ns, distribution 0.951ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.251     2.936    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X73Y105        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y105        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     2.976 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.118     3.094    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X73Y105        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.356     1.503    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X73Y105        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.689ns  (logic 0.038ns (5.515%)  route 0.651ns (94.485%))
  Logic Levels:           0  
  Clock Path Skew:        -1.326ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.623ns
    Source Clock Delay      (SCD):    2.949ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.264ns (routing 0.484ns, distribution 0.780ns)
  Clock Net Delay (Destination): 1.476ns (routing 0.405ns, distribution 1.071ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.264     2.949    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X78Y118        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y118        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.987 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           0.651     3.638    d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/src_in
    SLICE_X105Y108       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.476     1.623    d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/dest_clk
    SLICE_X105Y108       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.983ns  (logic 0.038ns (3.866%)  route 0.945ns (96.134%))
  Logic Levels:           0  
  Clock Path Skew:        -1.316ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.632ns
    Source Clock Delay      (SCD):    2.949ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.264ns (routing 0.484ns, distribution 0.780ns)
  Clock Net Delay (Destination): 1.485ns (routing 0.405ns, distribution 1.080ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.264     2.949    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X78Y118        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y118        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.987 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           0.945     3.931    d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/src_in
    SLICE_X111Y137       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.485     1.632    d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/dest_clk
    SLICE_X111Y137       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
                            (rising edge-triggered cell HSADC clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.090ns  (logic 0.454ns (41.651%)  route 0.636ns (58.349%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        -1.449ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.640ns
    Source Clock Delay      (SCD):    3.089ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.404ns (routing 0.484ns, distribution 0.920ns)
  Clock Net Delay (Destination): 1.493ns (routing 0.405ns, distribution 1.088ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.404     3.089    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m2_axis_aclk
    HSADC_X0Y2           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_FABRIC_CLK_STATUS_COMMON[5])
                                                      0.228     3.317 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[5]
                         net (fo=1, routed)           0.356     3.673    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[5]
    SLICE_X114Y123       LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.050     3.723 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_28/O
                         net (fo=1, routed)           0.027     3.750    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_28_n_0
    SLICE_X114Y123       LUT6 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.050     3.800 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_25/O
                         net (fo=1, routed)           0.024     3.824    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_25_n_0
    SLICE_X114Y123       LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.036     3.860 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_16/O
                         net (fo=1, routed)           0.087     3.947    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_16_n_0
    SLICE_X114Y117       LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.050     3.997 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_6/O
                         net (fo=1, routed)           0.125     4.122    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_6_n_0
    SLICE_X111Y124       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.040     4.162 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.017     4.179    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X111Y124       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.493     1.640    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y124       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.131ns  (logic 0.039ns (29.822%)  route 0.092ns (70.178%))
  Logic Levels:           0  
  Clock Path Skew:        -1.569ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.413ns
    Source Clock Delay      (SCD):    2.983ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.298ns (routing 0.484ns, distribution 0.814ns)
  Clock Net Delay (Destination): 1.266ns (routing 0.405ns, distribution 0.861ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.298     2.983    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X50Y147        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y147        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     3.022 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/Q
                         net (fo=83, routed)          0.092     3.113    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/Q[1]
    SLICE_X49Y146        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.266     1.413    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X49Y146        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.151ns  (logic 0.039ns (25.866%)  route 0.112ns (74.134%))
  Logic Levels:           0  
  Clock Path Skew:        -1.546ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.436ns
    Source Clock Delay      (SCD):    2.983ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.298ns (routing 0.484ns, distribution 0.814ns)
  Clock Net Delay (Destination): 1.289ns (routing 0.405ns, distribution 0.884ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.298     2.983    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X59Y96         FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y96         FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     3.022 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/Q
                         net (fo=83, routed)          0.112     3.133    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/Q[1]
    SLICE_X60Y96         FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.289     1.436    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X60Y96         FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.173ns  (logic 0.053ns (30.598%)  route 0.120ns (69.402%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -1.546ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.436ns
    Source Clock Delay      (SCD):    2.983ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.298ns (routing 0.484ns, distribution 0.814ns)
  Clock Net Delay (Destination): 1.289ns (routing 0.405ns, distribution 0.884ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.298     2.983    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X59Y96         FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y96         FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     3.022 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/Q
                         net (fo=83, routed)          0.033     3.055    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/Q[1]
    SLICE_X59Y96         LUT2 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.014     3.069 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/wptr[1]_i_1__1/O
                         net (fo=2, routed)           0.087     3.156    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/D[0]
    SLICE_X60Y96         FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.289     1.436    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X60Y96         FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_28_41/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[41]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.161ns  (logic 0.105ns (65.217%)  route 0.056ns (34.783%))
  Logic Levels:           0  
  Clock Path Skew:        -1.591ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.410ns
    Source Clock Delay      (SCD):    3.001ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.316ns (routing 0.484ns, distribution 0.832ns)
  Clock Net Delay (Destination): 1.263ns (routing 0.405ns, distribution 0.858ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.316     3.001    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_28_41/WCLK
    SLICE_X48Y148        RAMD32                                       r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_28_41/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y148        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.105     3.106 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_28_41/RAMG_D1/O
                         net (fo=1, routed)           0.056     3.162    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[41]
    SLICE_X47Y148        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[41]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.263     1.410    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X47Y148        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[41]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_28_41/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[33]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.167ns  (logic 0.110ns (65.868%)  route 0.057ns (34.132%))
  Logic Levels:           0  
  Clock Path Skew:        -1.591ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.410ns
    Source Clock Delay      (SCD):    3.001ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.316ns (routing 0.484ns, distribution 0.832ns)
  Clock Net Delay (Destination): 1.263ns (routing 0.405ns, distribution 0.858ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.316     3.001    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_28_41/WCLK
    SLICE_X48Y148        RAMD32                                       r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_28_41/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y148        RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.110     3.111 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_28_41/RAMC_D1/O
                         net (fo=1, routed)           0.057     3.168    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[33]
    SLICE_X47Y148        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[33]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.263     1.410    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X47Y148        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[33]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  clk_pl_0

Max Delay          1759 Endpoints
Min Delay          1759 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.221ns  (logic 0.228ns (18.669%)  route 0.993ns (81.331%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -2.786ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.030ns
    Source Clock Delay      (SCD):    4.816ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.302ns (routing 1.037ns, distribution 1.265ns)
  Clock Net Delay (Destination): 1.848ns (routing 0.599ns, distribution 1.249ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.302     4.816    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X59Y144        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y144        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.895 f  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=4, routed)           0.660     5.555    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X59Y110        LUT1 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.149     5.704 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.333     6.037    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X59Y98         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.848     2.030    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X59Y98         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.126ns  (logic 0.240ns (21.309%)  route 0.886ns (78.691%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -2.774ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.042ns
    Source Clock Delay      (SCD):    4.816ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.302ns (routing 1.037ns, distribution 1.265ns)
  Clock Net Delay (Destination): 1.860ns (routing 0.599ns, distribution 1.261ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.302     4.816    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X59Y144        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y144        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.895 f  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=4, routed)           0.660     5.555    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X59Y110        LUT1 (Prop_A5LUT_SLICEL_I0_O)
                                                      0.161     5.716 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.226     5.942    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X59Y110        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.860     2.042    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X59Y110        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.931ns  (logic 0.227ns (24.375%)  route 0.704ns (75.625%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -2.779ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.037ns
    Source Clock Delay      (SCD):    4.816ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.302ns (routing 1.037ns, distribution 1.265ns)
  Clock Net Delay (Destination): 1.855ns (routing 0.599ns, distribution 1.256ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.302     4.816    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X59Y144        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y144        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.895 f  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=4, routed)           0.483     5.378    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X53Y116        LUT1 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.148     5.526 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.221     5.747    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X53Y116        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.855     2.037    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X53Y116        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.739ns  (logic 0.130ns (17.601%)  route 0.609ns (82.399%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -2.823ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.993ns
    Source Clock Delay      (SCD):    4.816ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.302ns (routing 1.037ns, distribution 1.265ns)
  Clock Net Delay (Destination): 1.811ns (routing 0.599ns, distribution 1.212ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.302     4.816    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X59Y144        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y144        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.895 f  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=4, routed)           0.311     5.206    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X44Y144        LUT1 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.051     5.257 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.298     5.555    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X44Y144        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.811     1.993    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X44Y144        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.518ns  (logic 0.078ns (15.069%)  route 0.440ns (84.931%))
  Logic Levels:           0  
  Clock Path Skew:        -2.867ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.000ns
    Source Clock Delay      (SCD):    4.867ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.353ns (routing 1.037ns, distribution 1.316ns)
  Clock Net Delay (Destination): 1.818ns (routing 0.599ns, distribution 1.219ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.353     4.867    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X45Y144        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y144        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     4.945 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.440     5.385    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X45Y146        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.818     2.000    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X45Y146        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.481ns  (logic 0.079ns (16.421%)  route 0.402ns (83.579%))
  Logic Levels:           0  
  Clock Path Skew:        -2.800ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.030ns
    Source Clock Delay      (SCD):    4.830ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.316ns (routing 1.037ns, distribution 1.279ns)
  Clock Net Delay (Destination): 1.848ns (routing 0.599ns, distribution 1.249ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.316     4.830    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X59Y98         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y98         FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     4.909 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.402     5.311    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X59Y98         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.848     2.030    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X59Y98         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.330ns  (logic 0.079ns (23.906%)  route 0.251ns (76.094%))
  Logic Levels:           0  
  Clock Path Skew:        -2.815ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.042ns
    Source Clock Delay      (SCD):    4.857ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.343ns (routing 1.037ns, distribution 1.306ns)
  Clock Net Delay (Destination): 1.860ns (routing 0.599ns, distribution 1.261ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.343     4.857    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X58Y111        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y111        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     4.936 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.251     5.187    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X59Y110        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.860     2.042    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X59Y110        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.305ns  (logic 0.076ns (24.915%)  route 0.229ns (75.085%))
  Logic Levels:           0  
  Clock Path Skew:        -2.828ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.037ns
    Source Clock Delay      (SCD):    4.865ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.351ns (routing 1.037ns, distribution 1.314ns)
  Clock Net Delay (Destination): 1.855ns (routing 0.599ns, distribution 1.256ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.351     4.865    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X53Y118        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y118        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     4.941 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.229     5.170    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X53Y116        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.855     2.037    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X53Y116        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/ENARDEN
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.386ns  (logic 0.373ns (8.505%)  route 4.013ns (91.495%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -2.707ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.165ns
    Source Clock Delay      (SCD):    4.872ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.358ns (routing 1.037ns, distribution 1.321ns)
  Clock Net Delay (Destination): 1.983ns (routing 0.599ns, distribution 1.384ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.358     4.872    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X39Y151        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y151        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     4.951 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[4]/Q
                         net (fo=63, routed)          1.041     5.992    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_12[3]
    SLICE_X45Y174        LUT5 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.145     6.137 r  d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_14_i_2/O
                         net (fo=35, routed)          2.261     8.397    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/ext_mem_addr[3]
    SLICE_X65Y267        LUT4 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.149     8.546 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/RAM_reg_bram_11_i_3/O
                         net (fo=1, routed)           0.711     9.258    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11_2
    RAMB36_X6Y60         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/ENARDEN
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.983     2.165    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ps_clk_i
    RAMB36_X6Y60         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/CLKARDCLK

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/WEA[0]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.293ns  (logic 0.365ns (8.502%)  route 3.928ns (91.498%))
  Logic Levels:           2  (LUT3=1 LUT5=1)
  Clock Path Skew:        -2.707ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.165ns
    Source Clock Delay      (SCD):    4.872ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.358ns (routing 1.037ns, distribution 1.321ns)
  Clock Net Delay (Destination): 1.983ns (routing 0.599ns, distribution 1.384ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.358     4.872    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X39Y151        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y151        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     4.951 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[4]/Q
                         net (fo=63, routed)          1.041     5.992    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_12[3]
    SLICE_X45Y174        LUT5 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.145     6.137 r  d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_14_i_2/O
                         net (fo=35, routed)          2.206     8.343    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/TPROC_CFG_reg[1]_1
    SLICE_X65Y270        LUT3 (Prop_B5LUT_SLICEL_I1_O)
                                                      0.141     8.484 r  d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_11_i_5/O
                         net (fo=4, routed)           0.681     9.165    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11_4[0]
    RAMB36_X6Y60         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/WEA[0]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.983     2.165    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ps_clk_i
    RAMB36_X6Y60         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/CLKARDCLK





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.394%)  route 0.060ns (60.606%))
  Logic Levels:           0  
  Clock Path Skew:        -1.569ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.416ns
    Source Clock Delay      (SCD):    2.985ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.299ns (routing 0.571ns, distribution 0.728ns)
  Clock Net Delay (Destination): 1.269ns (routing 0.405ns, distribution 0.864ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.299     2.985    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X44Y149        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y149        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.024 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.060     3.084    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X44Y148        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.269     1.416    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X44Y148        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.039ns (39.000%)  route 0.061ns (61.000%))
  Logic Levels:           0  
  Clock Path Skew:        -1.543ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.444ns
    Source Clock Delay      (SCD):    2.988ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.302ns (routing 0.571ns, distribution 0.731ns)
  Clock Net Delay (Destination): 1.297ns (routing 0.405ns, distribution 0.892ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.302     2.988    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X56Y119        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y119        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     3.027 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.061     3.088    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0]
    SLICE_X55Y119        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.297     1.444    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X55Y119        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.123ns  (logic 0.039ns (31.707%)  route 0.084ns (68.293%))
  Logic Levels:           0  
  Clock Path Skew:        -1.536ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.437ns
    Source Clock Delay      (SCD):    2.973ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.287ns (routing 0.571ns, distribution 0.716ns)
  Clock Net Delay (Destination): 1.290ns (routing 0.405ns, distribution 0.885ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.287     2.973    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X60Y99         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y99         FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     3.012 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.084     3.096    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X60Y98         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.290     1.437    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X60Y98         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.123ns  (logic 0.039ns (31.707%)  route 0.084ns (68.293%))
  Logic Levels:           0  
  Clock Path Skew:        -1.539ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.437ns
    Source Clock Delay      (SCD):    2.976ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.290ns (routing 0.571ns, distribution 0.719ns)
  Clock Net Delay (Destination): 1.290ns (routing 0.405ns, distribution 0.885ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.290     2.976    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X58Y97         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y97         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.015 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.084     3.099    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X58Y97         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.290     1.437    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X58Y97         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.132ns  (logic 0.039ns (29.545%)  route 0.093ns (70.455%))
  Logic Levels:           0  
  Clock Path Skew:        -1.537ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.436ns
    Source Clock Delay      (SCD):    2.973ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.287ns (routing 0.571ns, distribution 0.716ns)
  Clock Net Delay (Destination): 1.289ns (routing 0.405ns, distribution 0.884ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.287     2.973    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X60Y99         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y99         FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     3.012 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.093     3.105    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X60Y99         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.289     1.436    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X60Y99         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.134ns  (logic 0.039ns (29.104%)  route 0.095ns (70.896%))
  Logic Levels:           0  
  Clock Path Skew:        -1.537ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.436ns
    Source Clock Delay      (SCD):    2.973ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.287ns (routing 0.571ns, distribution 0.716ns)
  Clock Net Delay (Destination): 1.289ns (routing 0.405ns, distribution 0.884ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.287     2.973    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X60Y99         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y99         FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     3.012 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.095     3.107    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X60Y99         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.289     1.436    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X60Y99         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.039ns (30.709%)  route 0.088ns (69.291%))
  Logic Levels:           0  
  Clock Path Skew:        -1.547ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.436ns
    Source Clock Delay      (SCD):    2.983ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.297ns (routing 0.571ns, distribution 0.726ns)
  Clock Net Delay (Destination): 1.289ns (routing 0.405ns, distribution 0.884ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.297     2.983    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X59Y118        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y118        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     3.022 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.088     3.110    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X59Y118        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.289     1.436    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X59Y118        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.131ns  (logic 0.041ns (31.298%)  route 0.090ns (68.702%))
  Logic Levels:           0  
  Clock Path Skew:        -1.570ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.413ns
    Source Clock Delay      (SCD):    2.983ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.297ns (routing 0.571ns, distribution 0.726ns)
  Clock Net Delay (Destination): 1.266ns (routing 0.405ns, distribution 0.861ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.297     2.983    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X44Y147        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y147        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     3.024 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.090     3.114    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X45Y146        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.266     1.413    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X45Y146        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.143ns  (logic 0.039ns (27.273%)  route 0.104ns (72.727%))
  Logic Levels:           0  
  Clock Path Skew:        -1.536ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.437ns
    Source Clock Delay      (SCD):    2.973ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.287ns (routing 0.571ns, distribution 0.716ns)
  Clock Net Delay (Destination): 1.290ns (routing 0.405ns, distribution 0.885ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.287     2.973    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X60Y99         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y99         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     3.012 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.104     3.116    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0]
    SLICE_X60Y98         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.290     1.437    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X60Y98         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.037ns (28.753%)  route 0.092ns (71.247%))
  Logic Levels:           0  
  Clock Path Skew:        -1.546ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.444ns
    Source Clock Delay      (SCD):    2.990ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.304ns (routing 0.571ns, distribution 0.733ns)
  Clock Net Delay (Destination): 1.297ns (routing 0.405ns, distribution 0.892ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.304     2.990    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X53Y118        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y118        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     3.027 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.092     3.119    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X53Y116        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.297     1.444    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X53Y116        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Max Delay           175 Endpoints
Min Delay           175 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/syncstages_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_intc_0/U0/INTC_CORE_I/INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.470ns  (logic 0.477ns (10.671%)  route 3.993ns (89.329%))
  Logic Levels:           4  (LUT3=1 LUT5=2 LUT6=1)
  Clock Path Skew:        -0.555ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.138ns
    Source Clock Delay      (SCD):    2.693ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.467ns (routing 0.662ns, distribution 1.805ns)
  Clock Net Delay (Destination): 1.956ns (routing 0.599ns, distribution 1.357ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.467     2.693    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/dest_clk
    SLICE_X116Y254       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/syncstages_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X116Y254       FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.774 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/syncstages_ff_reg[4]/Q
                         net (fo=2, routed)           1.532     4.306    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/dac13_irq_sync[0]
    SLICE_X114Y136       LUT5 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.146     4.452 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/irq_INST_0_i_31/O
                         net (fo=2, routed)           0.397     4.849    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/dac13_irq_en_reg
    SLICE_X109Y135       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.051     4.900 f  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/irq_INST_0_i_10/O
                         net (fo=2, routed)           0.266     5.166    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/dac1_irq_en_reg
    SLICE_X108Y127       LUT3 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.051     5.217 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/irq_INST_0_i_3/O
                         net (fo=1, routed)           0.057     5.274    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/irq_INST_0_i_3_n_0
    SLICE_X108Y127       LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.148     5.422 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/irq_INST_0/O
                         net (fo=1, routed)           1.741     7.163    d_1_i/axi_intc_0/U0/INTC_CORE_I/intr[6]
    SLICE_X74Y73         FDRE                                         r  d_1_i/axi_intc_0/U0/INTC_CORE_I/INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.956     2.138    d_1_i/axi_intc_0/U0/INTC_CORE_I/s_axi_aclk
    SLICE_X74Y73         FDRE                                         r  d_1_i/axi_intc_0/U0/INTC_CORE_I/INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.430ns  (logic 0.079ns (1.783%)  route 4.351ns (98.217%))
  Logic Levels:           0  
  Clock Path Skew:        -0.286ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.094ns
    Source Clock Delay      (SCD):    2.380ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.154ns (routing 0.662ns, distribution 1.492ns)
  Clock Net Delay (Destination): 1.912ns (routing 0.599ns, distribution 1.313ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.154     2.380    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X77Y239        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y239        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.459 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=154, routed)         4.351     6.810    d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X35Y52         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.912     2.094    d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X35Y52         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.241ns  (logic 0.079ns (1.863%)  route 4.162ns (98.137%))
  Logic Levels:           0  
  Clock Path Skew:        -0.257ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.123ns
    Source Clock Delay      (SCD):    2.380ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.154ns (routing 0.662ns, distribution 1.492ns)
  Clock Net Delay (Destination): 1.941ns (routing 0.599ns, distribution 1.342ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.154     2.380    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X77Y239        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y239        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.459 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=154, routed)         4.162     6.621    d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST_OUT/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X63Y15         FDRE                                         r  d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.941     2.123    d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST_OUT/s_axi_lite_aclk
    SLICE_X63Y15         FDRE                                         r  d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.958ns  (logic 0.079ns (1.996%)  route 3.879ns (98.004%))
  Logic Levels:           0  
  Clock Path Skew:        -0.241ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.139ns
    Source Clock Delay      (SCD):    2.380ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.154ns (routing 0.662ns, distribution 1.492ns)
  Clock Net Delay (Destination): 1.957ns (routing 0.599ns, distribution 1.358ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.154     2.380    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X77Y239        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y239        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.459 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=154, routed)         3.879     6.338    d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X74Y74         FDRE                                         r  d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.957     2.139    d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X74Y74         FDRE                                         r  d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.952ns  (logic 0.079ns (1.999%)  route 3.873ns (98.001%))
  Logic Levels:           0  
  Clock Path Skew:        -0.320ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.060ns
    Source Clock Delay      (SCD):    2.380ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.154ns (routing 0.662ns, distribution 1.492ns)
  Clock Net Delay (Destination): 1.878ns (routing 0.599ns, distribution 1.279ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.154     2.380    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X77Y239        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y239        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.459 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=154, routed)         3.873     6.332    d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X33Y128        FDRE                                         r  d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.878     2.060    d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X33Y128        FDRE                                         r  d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.929ns  (logic 0.079ns (2.011%)  route 3.850ns (97.989%))
  Logic Levels:           0  
  Clock Path Skew:        -0.250ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.130ns
    Source Clock Delay      (SCD):    2.380ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.154ns (routing 0.662ns, distribution 1.492ns)
  Clock Net Delay (Destination): 1.948ns (routing 0.599ns, distribution 1.349ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.154     2.380    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X77Y239        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y239        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.459 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=154, routed)         3.850     6.309    d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X66Y51         FDRE                                         r  d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.948     2.130    d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X66Y51         FDRE                                         r  d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.845ns  (logic 0.079ns (2.055%)  route 3.766ns (97.945%))
  Logic Levels:           0  
  Clock Path Skew:        -0.286ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.094ns
    Source Clock Delay      (SCD):    2.380ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.154ns (routing 0.662ns, distribution 1.492ns)
  Clock Net Delay (Destination): 1.912ns (routing 0.599ns, distribution 1.313ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.154     2.380    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X77Y239        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y239        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.459 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=154, routed)         3.766     6.225    d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST_OUT/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X62Y79         FDRE                                         r  d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.912     2.094    d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST_OUT/s_axi_lite_aclk
    SLICE_X62Y79         FDRE                                         r  d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.751ns  (logic 0.079ns (2.106%)  route 3.672ns (97.894%))
  Logic Levels:           0  
  Clock Path Skew:        -0.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.038ns
    Source Clock Delay      (SCD):    2.380ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.154ns (routing 0.662ns, distribution 1.492ns)
  Clock Net Delay (Destination): 1.856ns (routing 0.599ns, distribution 1.257ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.154     2.380    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X77Y239        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y239        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.459 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=154, routed)         3.672     6.131    d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X59Y80         FDRE                                         r  d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.856     2.038    d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X59Y80         FDRE                                         r  d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.617ns  (logic 0.079ns (2.184%)  route 3.538ns (97.816%))
  Logic Levels:           0  
  Clock Path Skew:        -0.317ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.063ns
    Source Clock Delay      (SCD):    2.380ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.154ns (routing 0.662ns, distribution 1.492ns)
  Clock Net Delay (Destination): 1.881ns (routing 0.599ns, distribution 1.282ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.154     2.380    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X77Y239        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y239        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.459 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=154, routed)         3.538     5.997    d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST_OUT/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X35Y104        FDRE                                         r  d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.881     2.063    d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST_OUT/s_axi_lite_aclk
    SLICE_X35Y104        FDRE                                         r  d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.413ns  (logic 0.105ns (3.076%)  route 3.308ns (96.924%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.378ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.093ns
    Source Clock Delay      (SCD):    2.471ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.245ns (routing 0.662ns, distribution 1.583ns)
  Clock Net Delay (Destination): 1.911ns (routing 0.599ns, distribution 1.312ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.245     2.471    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X76Y335        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y335        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.548 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.184     3.732    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y146        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.760 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14833, routed)       2.124     5.884    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst
    SLICE_X26Y39         FDPE                                         f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.911     2.093    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk
    SLICE_X26Y39         FDPE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_start_router_config/ctrl_soft_reset_r_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.091ns  (logic 0.039ns (42.857%)  route 0.052ns (57.143%))
  Logic Levels:           0  
  Clock Path Skew:        0.166ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.388ns
    Source Clock Delay      (SCD):    1.223ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.103ns (routing 0.359ns, distribution 0.744ns)
  Clock Net Delay (Destination): 1.241ns (routing 0.405ns, distribution 0.836ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.103     1.223    d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_start_router_config/s_axi_ctrl_aclk
    SLICE_X40Y239        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_start_router_config/ctrl_soft_reset_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y239        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.262 r  d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_start_router_config/ctrl_soft_reset_r_reg/Q
                         net (fo=1, routed)           0.052     1.314    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/src_in
    SLICE_X40Y239        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.241     1.388    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/dest_clk
    SLICE_X40Y239        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.095ns  (logic 0.039ns (41.053%)  route 0.056ns (58.947%))
  Logic Levels:           0  
  Clock Path Skew:        0.166ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.388ns
    Source Clock Delay      (SCD):    1.223ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.103ns (routing 0.359ns, distribution 0.744ns)
  Clock Net Delay (Destination): 1.241ns (routing 0.405ns, distribution 0.836ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.103     1.223    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X38Y238        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y238        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.262 r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.056     1.318    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X38Y239        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.241     1.388    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X38Y239        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.039ns (33.025%)  route 0.079ns (66.975%))
  Logic Levels:           0  
  Clock Path Skew:        0.163ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.388ns
    Source Clock Delay      (SCD):    1.226ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.106ns (routing 0.359ns, distribution 0.747ns)
  Clock Net Delay (Destination): 1.241ns (routing 0.405ns, distribution 0.836ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.106     1.226    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X38Y239        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y239        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.265 r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.079     1.344    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X38Y238        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.241     1.388    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X38Y238        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.114ns  (logic 0.039ns (34.183%)  route 0.075ns (65.817%))
  Logic Levels:           0  
  Clock Path Skew:        0.173ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.439ns
    Source Clock Delay      (SCD):    1.266ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.146ns (routing 0.359ns, distribution 0.787ns)
  Clock Net Delay (Destination): 1.292ns (routing 0.405ns, distribution 0.887ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.146     1.266    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X58Y95         FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y95         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.305 r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.075     1.380    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X58Y94         FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.292     1.439    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X58Y94         FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.161ns  (logic 0.038ns (23.551%)  route 0.123ns (76.449%))
  Logic Levels:           0  
  Clock Path Skew:        0.186ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.440ns
    Source Clock Delay      (SCD):    1.254ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.134ns (routing 0.359ns, distribution 0.775ns)
  Clock Net Delay (Destination): 1.293ns (routing 0.405ns, distribution 0.888ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.134     1.254    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X60Y90         FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y90         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.292 r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.123     1.415    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X58Y95         FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.293     1.440    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X58Y95         FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.038ns (30.513%)  route 0.087ns (69.486%))
  Logic Levels:           0  
  Clock Path Skew:        0.190ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.505ns
    Source Clock Delay      (SCD):    1.315ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.195ns (routing 0.359ns, distribution 0.836ns)
  Clock Net Delay (Destination): 1.358ns (routing 0.405ns, distribution 0.953ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.195     1.315    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X72Y104        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y104        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.353 r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.087     1.440    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X71Y105        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.358     1.505    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X71Y105        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.151ns  (logic 0.039ns (25.882%)  route 0.112ns (74.118%))
  Logic Levels:           0  
  Clock Path Skew:        0.174ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.498ns
    Source Clock Delay      (SCD):    1.324ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.204ns (routing 0.359ns, distribution 0.845ns)
  Clock Net Delay (Destination): 1.351ns (routing 0.405ns, distribution 0.946ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.204     1.324    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X71Y105        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y105        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.363 r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.112     1.474    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X72Y104        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.351     1.498    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X72Y104        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s04_entry_pipeline/s04_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.278ns  (logic 0.038ns (13.678%)  route 0.240ns (86.322%))
  Logic Levels:           0  
  Clock Path Skew:        0.167ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.426ns
    Source Clock Delay      (SCD):    1.260ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.140ns (routing 0.359ns, distribution 0.781ns)
  Clock Net Delay (Destination): 1.279ns (routing 0.405ns, distribution 0.874ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.140     1.260    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X46Y106        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y106        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.298 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=120, routed)         0.240     1.537    d_1_i/axi_smc/inst/s04_entry_pipeline/s04_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X44Y82         FDCE                                         f  d_1_i/axi_smc/inst/s04_entry_pipeline/s04_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.279     1.426    d_1_i/axi_smc/inst/s04_entry_pipeline/s04_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X44Y82         FDCE                                         r  d_1_i/axi_smc/inst/s04_entry_pipeline/s04_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s04_entry_pipeline/s04_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.278ns  (logic 0.038ns (13.678%)  route 0.240ns (86.322%))
  Logic Levels:           0  
  Clock Path Skew:        0.167ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.426ns
    Source Clock Delay      (SCD):    1.260ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.140ns (routing 0.359ns, distribution 0.781ns)
  Clock Net Delay (Destination): 1.279ns (routing 0.405ns, distribution 0.874ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.140     1.260    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X46Y106        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y106        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.298 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=120, routed)         0.240     1.537    d_1_i/axi_smc/inst/s04_entry_pipeline/s04_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X44Y82         FDCE                                         f  d_1_i/axi_smc/inst/s04_entry_pipeline/s04_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.279     1.426    d_1_i/axi_smc/inst/s04_entry_pipeline/s04_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X44Y82         FDCE                                         r  d_1_i/axi_smc/inst/s04_entry_pipeline/s04_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s04_entry_pipeline/s04_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.278ns  (logic 0.038ns (13.678%)  route 0.240ns (86.322%))
  Logic Levels:           0  
  Clock Path Skew:        0.167ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.426ns
    Source Clock Delay      (SCD):    1.260ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.140ns (routing 0.359ns, distribution 0.781ns)
  Clock Net Delay (Destination): 1.279ns (routing 0.405ns, distribution 0.874ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.140     1.260    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X46Y106        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y106        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.298 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=120, routed)         0.240     1.537    d_1_i/axi_smc/inst/s04_entry_pipeline/s04_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X44Y82         FDCE                                         f  d_1_i/axi_smc/inst/s04_entry_pipeline/s04_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.279     1.426    d_1_i/axi_smc/inst/s04_entry_pipeline/s04_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X44Y82         FDCE                                         r  d_1_i/axi_smc/inst/s04_entry_pipeline/s04_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout5
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Max Delay            94 Endpoints
Min Delay           102 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[10]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.283ns  (logic 0.076ns (5.924%)  route 1.207ns (94.076%))
  Logic Levels:           0  
  Clock Path Skew:        2.143ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.480ns
    Source Clock Delay      (SCD):    3.337ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 2.644ns (routing 1.525ns, distribution 1.119ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.136     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.207     4.620    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[0]_0
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[10]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.644     5.480    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[10]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[11]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.283ns  (logic 0.076ns (5.924%)  route 1.207ns (94.076%))
  Logic Levels:           0  
  Clock Path Skew:        2.143ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.480ns
    Source Clock Delay      (SCD):    3.337ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 2.644ns (routing 1.525ns, distribution 1.119ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.136     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.207     4.620    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[0]_0
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[11]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.644     5.480    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[11]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[12]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.283ns  (logic 0.076ns (5.924%)  route 1.207ns (94.076%))
  Logic Levels:           0  
  Clock Path Skew:        2.143ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.480ns
    Source Clock Delay      (SCD):    3.337ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 2.644ns (routing 1.525ns, distribution 1.119ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.136     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.207     4.620    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[0]_0
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[12]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.644     5.480    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[12]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[13]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.283ns  (logic 0.076ns (5.924%)  route 1.207ns (94.076%))
  Logic Levels:           0  
  Clock Path Skew:        2.143ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.480ns
    Source Clock Delay      (SCD):    3.337ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 2.644ns (routing 1.525ns, distribution 1.119ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.136     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.207     4.620    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[0]_0
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[13]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.644     5.480    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[13]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.283ns  (logic 0.076ns (5.924%)  route 1.207ns (94.076%))
  Logic Levels:           0  
  Clock Path Skew:        2.143ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.480ns
    Source Clock Delay      (SCD):    3.337ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 2.644ns (routing 1.525ns, distribution 1.119ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.136     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.207     4.620    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[0]_0
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.644     5.480    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[3]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.283ns  (logic 0.076ns (5.924%)  route 1.207ns (94.076%))
  Logic Levels:           0  
  Clock Path Skew:        2.143ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.480ns
    Source Clock Delay      (SCD):    3.337ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 2.644ns (routing 1.525ns, distribution 1.119ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.136     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.207     4.620    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[0]_0
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[3]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.644     5.480    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[3]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[4]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.283ns  (logic 0.076ns (5.924%)  route 1.207ns (94.076%))
  Logic Levels:           0  
  Clock Path Skew:        2.143ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.480ns
    Source Clock Delay      (SCD):    3.337ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 2.644ns (routing 1.525ns, distribution 1.119ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.136     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.207     4.620    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[0]_0
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[4]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.644     5.480    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[4]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[5]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.283ns  (logic 0.076ns (5.924%)  route 1.207ns (94.076%))
  Logic Levels:           0  
  Clock Path Skew:        2.143ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.480ns
    Source Clock Delay      (SCD):    3.337ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 2.644ns (routing 1.525ns, distribution 1.119ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.136     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.207     4.620    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[0]_0
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[5]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.644     5.480    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[5]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[14]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.282ns  (logic 0.076ns (5.929%)  route 1.206ns (94.071%))
  Logic Levels:           0  
  Clock Path Skew:        2.145ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.482ns
    Source Clock Delay      (SCD):    3.337ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 2.646ns (routing 1.525ns, distribution 1.121ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.136     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.206     4.619    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[0]_0
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[14]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.646     5.482    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[14]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[15]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.282ns  (logic 0.076ns (5.929%)  route 1.206ns (94.071%))
  Logic Levels:           0  
  Clock Path Skew:        2.145ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.482ns
    Source Clock Delay      (SCD):    3.337ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 2.646ns (routing 1.525ns, distribution 1.121ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.201 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.136     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.206     4.619    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[0]_0
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[15]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.646     5.482    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[15]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.101ns  (logic 0.040ns (39.604%)  route 0.061ns (60.396%))
  Logic Levels:           0  
  Clock Path Skew:        6.376ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.571ns
    Source Clock Delay      (SCD):    2.196ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.647ns (routing 0.096ns, distribution 0.551ns)
  Clock Net Delay (Destination): 1.800ns (routing 1.028ns, distribution 0.772ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.647     2.196    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
    SLICE_X102Y293       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y293       FDCE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     2.236 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.061     2.297    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[1]
    SLICE_X100Y293       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.800     8.571    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/wr_clk
    SLICE_X100Y293       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.103ns  (logic 0.039ns (37.864%)  route 0.064ns (62.136%))
  Logic Levels:           0  
  Clock Path Skew:        6.380ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.575ns
    Source Clock Delay      (SCD):    2.196ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.647ns (routing 0.096ns, distribution 0.551ns)
  Clock Net Delay (Destination): 1.804ns (routing 1.028ns, distribution 0.776ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.647     2.196    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
    SLICE_X102Y293       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y293       FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.235 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.064     2.299    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[0]
    SLICE_X100Y293       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.804     8.575    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/wr_clk
    SLICE_X100Y293       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        6.388ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.571ns
    Source Clock Delay      (SCD):    2.183ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.634ns (routing 0.096ns, distribution 0.538ns)
  Clock Net Delay (Destination): 1.800ns (routing 1.028ns, distribution 0.772ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.634     2.183    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/clk
    SLICE_X102Y296       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y296       FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.223 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[0]/Q
                         net (fo=1, routed)           0.079     2.302    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg[0]
    SLICE_X102Y297       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.800     8.571    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/m_bscan_tck[0]
    SLICE_X102Y297       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        6.380ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.567ns
    Source Clock Delay      (SCD):    2.187ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.638ns (routing 0.096ns, distribution 0.542ns)
  Clock Net Delay (Destination): 1.796ns (routing 1.028ns, distribution 0.768ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.638     2.187    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/clk
    SLICE_X102Y298       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y298       FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.227 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[2]/Q
                         net (fo=1, routed)           0.079     2.306    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg[2]
    SLICE_X102Y299       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.796     8.567    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/m_bscan_tck[0]
    SLICE_X102Y299       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        6.383ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.571ns
    Source Clock Delay      (SCD):    2.188ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.639ns (routing 0.096ns, distribution 0.543ns)
  Clock Net Delay (Destination): 1.800ns (routing 1.028ns, distribution 0.772ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.639     2.188    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/clk
    SLICE_X103Y298       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y298       FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.227 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[0]/Q
                         net (fo=1, routed)           0.085     2.312    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg[0]
    SLICE_X103Y299       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.800     8.571    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/m_bscan_tck[0]
    SLICE_X103Y299       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        6.375ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.570ns
    Source Clock Delay      (SCD):    2.195ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.646ns (routing 0.096ns, distribution 0.550ns)
  Clock Net Delay (Destination): 1.799ns (routing 1.028ns, distribution 0.771ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.646     2.195    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/clk
    SLICE_X105Y296       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y296       FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.235 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/Q
                         net (fo=1, routed)           0.079     2.314    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg[0]
    SLICE_X105Y297       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.799     8.570    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X105Y297       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        6.376ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.571ns
    Source Clock Delay      (SCD):    2.195ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.646ns (routing 0.096ns, distribution 0.550ns)
  Clock Net Delay (Destination): 1.800ns (routing 1.028ns, distribution 0.772ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.646     2.195    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/clk
    SLICE_X104Y298       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y298       FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.234 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[1]/Q
                         net (fo=1, routed)           0.085     2.319    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg[1]
    SLICE_X104Y299       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.800     8.571    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/m_bscan_tck[0]
    SLICE_X104Y299       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.039ns (31.200%)  route 0.086ns (68.800%))
  Logic Levels:           0  
  Clock Path Skew:        6.377ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.575ns
    Source Clock Delay      (SCD):    2.198ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.649ns (routing 0.096ns, distribution 0.553ns)
  Clock Net Delay (Destination): 1.804ns (routing 1.028ns, distribution 0.776ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.649     2.198    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/clk
    SLICE_X104Y296       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y296       FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[2]/Q
                         net (fo=1, routed)           0.086     2.323    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg[2]
    SLICE_X104Y297       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.804     8.575    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X104Y297       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.142ns  (logic 0.038ns (26.782%)  route 0.104ns (73.218%))
  Logic Levels:           0  
  Clock Path Skew:        6.381ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.570ns
    Source Clock Delay      (SCD):    2.189ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.640ns (routing 0.096ns, distribution 0.544ns)
  Clock Net Delay (Destination): 1.799ns (routing 1.028ns, distribution 0.771ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.640     2.189    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.227 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.104     2.331    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/out
    SLICE_X105Y295       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.799     8.570    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/m_bscan_tck[0]
    SLICE_X105Y295       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.142ns  (logic 0.038ns (26.782%)  route 0.104ns (73.218%))
  Logic Levels:           0  
  Clock Path Skew:        6.381ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.570ns
    Source Clock Delay      (SCD):    2.189ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.640ns (routing 0.096ns, distribution 0.544ns)
  Clock Net Delay (Destination): 1.799ns (routing 1.028ns, distribution 0.771ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.640     2.189    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y293       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.227 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.104     2.331    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/out
    SLICE_X105Y295       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[1]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.799     8.570    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/m_bscan_tck[0]
    SLICE_X105Y295       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  mmcm_clkout0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.811ns  (logic 0.079ns (9.738%)  route 0.732ns (90.262%))
  Logic Levels:           0  
  Clock Path Skew:        1.052ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.546ns
    Source Clock Delay      (SCD):    3.494ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.821ns (routing 1.381ns, distribution 1.440ns)
  Clock Net Delay (Destination): 1.899ns (routing 0.716ns, distribution 1.183ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       2.821     3.494    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X73Y217        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y217        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     3.573 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/Q
                         net (fo=2, routed)           0.732     4.305    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/trigger
    SLICE_X66Y217        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.899     4.546    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/aclk
    SLICE_X66Y217        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.396ns  (logic 0.039ns (9.846%)  route 0.357ns (90.154%))
  Logic Levels:           0  
  Clock Path Skew:        0.716ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.610ns
    Source Clock Delay      (SCD):    1.894ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.545ns (routing 0.748ns, distribution 0.797ns)
  Clock Net Delay (Destination): 1.318ns (routing 0.485ns, distribution 0.833ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89295, routed)       1.545     1.894    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X73Y217        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y217        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.933 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/Q
                         net (fo=2, routed)           0.357     2.290    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/trigger
    SLICE_X66Y217        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.318     2.610    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/aclk
    SLICE_X66Y217        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  mmcm_clkout0

Max Delay           518 Endpoints
Min Delay           518 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[55]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.864ns  (logic 0.295ns (34.144%)  route 0.569ns (65.856%))
  Logic Levels:           0  
  Clock Path Skew:        -0.294ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.657ns
    Source Clock Delay      (SCD):    4.951ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.392ns (routing 0.878ns, distribution 1.514ns)
  Clock Net Delay (Destination): 2.010ns (routing 0.716ns, distribution 1.294ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.392     4.951    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X41Y219        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y219        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.295     5.246 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMG_D1/O
                         net (fo=1, routed)           0.569     5.815    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[55]
    SLICE_X42Y218        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[55]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.010     4.657    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X42Y218        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[55]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_294_307/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[294]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.870ns  (logic 0.289ns (33.218%)  route 0.581ns (66.782%))
  Logic Levels:           0  
  Clock Path Skew:        -0.284ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.659ns
    Source Clock Delay      (SCD):    4.943ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.384ns (routing 0.878ns, distribution 1.506ns)
  Clock Net Delay (Destination): 2.012ns (routing 0.716ns, distribution 1.296ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.384     4.943    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_294_307/WCLK
    SLICE_X41Y213        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_294_307/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y213        RAMD32 (Prop_A5LUT_SLICEM_CLK_O)
                                                      0.289     5.232 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_294_307/RAMA/O
                         net (fo=1, routed)           0.581     5.813    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[294]
    SLICE_X42Y213        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[294]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.012     4.659    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X42Y213        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[294]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[50]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.857ns  (logic 0.288ns (33.606%)  route 0.569ns (66.394%))
  Logic Levels:           0  
  Clock Path Skew:        -0.294ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.657ns
    Source Clock Delay      (SCD):    4.951ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.392ns (routing 0.878ns, distribution 1.514ns)
  Clock Net Delay (Destination): 2.010ns (routing 0.716ns, distribution 1.294ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.392     4.951    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X41Y219        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y219        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.288     5.239 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAME/O
                         net (fo=1, routed)           0.569     5.808    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[50]
    SLICE_X42Y218        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[50]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.010     4.657    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X42Y218        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[50]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/RAMC/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[200]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.866ns  (logic 0.288ns (33.256%)  route 0.578ns (66.744%))
  Logic Levels:           0  
  Clock Path Skew:        -0.281ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.652ns
    Source Clock Delay      (SCD):    4.933ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.374ns (routing 0.878ns, distribution 1.496ns)
  Clock Net Delay (Destination): 2.005ns (routing 0.716ns, distribution 1.289ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.374     4.933    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/WCLK
    SLICE_X48Y226        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/RAMC/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y226        RAMD32 (Prop_C5LUT_SLICEM_CLK_O)
                                                      0.288     5.221 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/RAMC/O
                         net (fo=1, routed)           0.578     5.799    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[200]
    SLICE_X48Y225        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[200]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.005     4.652    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X48Y225        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[200]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_294_307/RAMC/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[298]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.849ns  (logic 0.288ns (33.922%)  route 0.561ns (66.078%))
  Logic Levels:           0  
  Clock Path Skew:        -0.296ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.647ns
    Source Clock Delay      (SCD):    4.943ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.384ns (routing 0.878ns, distribution 1.506ns)
  Clock Net Delay (Destination): 2.000ns (routing 0.716ns, distribution 1.284ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.384     4.943    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_294_307/WCLK
    SLICE_X41Y213        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_294_307/RAMC/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y213        RAMD32 (Prop_C5LUT_SLICEM_CLK_O)
                                                      0.288     5.231 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_294_307/RAMC/O
                         net (fo=1, routed)           0.561     5.792    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[298]
    SLICE_X43Y212        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[298]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.000     4.647    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X43Y212        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[298]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[134]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.834ns  (logic 0.288ns (34.532%)  route 0.546ns (65.468%))
  Logic Levels:           0  
  Clock Path Skew:        -0.302ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.655ns
    Source Clock Delay      (SCD):    4.957ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.398ns (routing 0.878ns, distribution 1.520ns)
  Clock Net Delay (Destination): 2.008ns (routing 0.716ns, distribution 1.292ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.398     4.957    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/WCLK
    SLICE_X42Y231        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X42Y231        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.288     5.245 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAME/O
                         net (fo=1, routed)           0.546     5.791    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[134]
    SLICE_X44Y231        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[134]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.008     4.655    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X44Y231        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[134]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[139]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.830ns  (logic 0.295ns (35.542%)  route 0.535ns (64.458%))
  Logic Levels:           0  
  Clock Path Skew:        -0.301ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.656ns
    Source Clock Delay      (SCD):    4.957ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.398ns (routing 0.878ns, distribution 1.520ns)
  Clock Net Delay (Destination): 2.009ns (routing 0.716ns, distribution 1.293ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.398     4.957    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/WCLK
    SLICE_X42Y231        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X42Y231        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.295     5.252 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMG_D1/O
                         net (fo=1, routed)           0.535     5.787    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[139]
    SLICE_X45Y233        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[139]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.009     4.656    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X45Y233        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[139]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_434_447/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[436]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.860ns  (logic 0.292ns (33.953%)  route 0.568ns (66.047%))
  Logic Levels:           0  
  Clock Path Skew:        -0.282ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.638ns
    Source Clock Delay      (SCD):    4.920ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.361ns (routing 0.878ns, distribution 1.483ns)
  Clock Net Delay (Destination): 1.991ns (routing 0.716ns, distribution 1.275ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.361     4.920    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_434_447/WCLK
    SLICE_X48Y214        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_434_447/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y214        RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292     5.212 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_434_447/RAMB/O
                         net (fo=1, routed)           0.568     5.780    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[436]
    SLICE_X49Y213        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[436]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.991     4.638    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X49Y213        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[436]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMF/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[52]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.826ns  (logic 0.295ns (35.714%)  route 0.531ns (64.286%))
  Logic Levels:           0  
  Clock Path Skew:        -0.294ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.657ns
    Source Clock Delay      (SCD):    4.951ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.392ns (routing 0.878ns, distribution 1.514ns)
  Clock Net Delay (Destination): 2.010ns (routing 0.716ns, distribution 1.294ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.392     4.951    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X41Y219        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMF/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y219        RAMD32 (Prop_F5LUT_SLICEM_CLK_O)
                                                      0.295     5.246 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMF/O
                         net (fo=1, routed)           0.531     5.777    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[52]
    SLICE_X42Y218        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[52]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.010     4.657    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X42Y218        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[52]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[71]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.844ns  (logic 0.305ns (36.137%)  route 0.539ns (63.863%))
  Logic Levels:           0  
  Clock Path Skew:        -0.280ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.653ns
    Source Clock Delay      (SCD):    4.933ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.374ns (routing 0.878ns, distribution 1.496ns)
  Clock Net Delay (Destination): 2.006ns (routing 0.716ns, distribution 1.290ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.886     2.413    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.286 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.531    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.374     4.933    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83/WCLK
    SLICE_X46Y221        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y221        RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.305     5.238 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83/RAMA_D1/O
                         net (fo=1, routed)           0.539     5.777    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[71]
    SLICE_X47Y222        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[71]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.006     4.653    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X47Y222        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[71]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.041ns (32.283%)  route 0.086ns (67.716%))
  Logic Levels:           0  
  Clock Path Skew:        -0.299ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.685ns
    Source Clock Delay      (SCD):    2.984ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.299ns (routing 0.484ns, distribution 0.815ns)
  Clock Net Delay (Destination): 1.393ns (routing 0.485ns, distribution 0.908ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.299     2.984    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X40Y216        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y216        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     3.025 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.086     3.111    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1]
    SLICE_X40Y216        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.393     2.685    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X40Y216        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.130ns  (logic 0.039ns (30.073%)  route 0.091ns (69.927%))
  Logic Levels:           0  
  Clock Path Skew:        -0.300ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.683ns
    Source Clock Delay      (SCD):    2.983ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.298ns (routing 0.484ns, distribution 0.814ns)
  Clock Net Delay (Destination): 1.391ns (routing 0.485ns, distribution 0.906ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.298     2.983    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X44Y196        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y196        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     3.022 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.091     3.112    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X45Y196        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.391     2.683    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X45Y196        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.149ns  (logic 0.039ns (26.175%)  route 0.110ns (73.826%))
  Logic Levels:           0  
  Clock Path Skew:        -0.291ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.692ns
    Source Clock Delay      (SCD):    2.984ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.299ns (routing 0.484ns, distribution 0.815ns)
  Clock Net Delay (Destination): 1.401ns (routing 0.485ns, distribution 0.916ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.299     2.984    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X40Y216        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y216        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.023 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.110     3.133    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[0]
    SLICE_X40Y215        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.401     2.692    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X40Y215        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_350_363/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[355]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.163ns  (logic 0.110ns (67.485%)  route 0.053ns (32.515%))
  Logic Levels:           0  
  Clock Path Skew:        -0.325ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.646ns
    Source Clock Delay      (SCD):    2.971ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.286ns (routing 0.484ns, distribution 0.802ns)
  Clock Net Delay (Destination): 1.354ns (routing 0.485ns, distribution 0.869ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.286     2.971    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_350_363/WCLK
    SLICE_X54Y211        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_350_363/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y211        RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.110     3.081 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_350_363/RAMC_D1/O
                         net (fo=1, routed)           0.053     3.134    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[355]
    SLICE_X55Y211        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[355]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.354     2.646    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X55Y211        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[355]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.160ns  (logic 0.039ns (24.375%)  route 0.121ns (75.625%))
  Logic Levels:           0  
  Clock Path Skew:        -0.299ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.680ns
    Source Clock Delay      (SCD):    2.979ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.294ns (routing 0.484ns, distribution 0.810ns)
  Clock Net Delay (Destination): 1.388ns (routing 0.485ns, distribution 0.903ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.294     2.979    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X40Y214        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y214        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.018 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.121     3.139    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2]
    SLICE_X39Y214        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.388     2.680    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X39Y214        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.157ns  (logic 0.038ns (24.204%)  route 0.119ns (75.796%))
  Logic Levels:           0  
  Clock Path Skew:        -0.300ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.686ns
    Source Clock Delay      (SCD):    2.986ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.301ns (routing 0.484ns, distribution 0.817ns)
  Clock Net Delay (Destination): 1.394ns (routing 0.485ns, distribution 0.909ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.301     2.986    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X39Y216        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y216        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     3.024 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.119     3.143    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[4]
    SLICE_X39Y216        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.394     2.686    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X39Y216        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_350_363/RAME_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[359]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.172ns  (logic 0.108ns (62.791%)  route 0.064ns (37.209%))
  Logic Levels:           0  
  Clock Path Skew:        -0.325ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.646ns
    Source Clock Delay      (SCD):    2.971ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.286ns (routing 0.484ns, distribution 0.802ns)
  Clock Net Delay (Destination): 1.354ns (routing 0.485ns, distribution 0.869ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.286     2.971    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_350_363/WCLK
    SLICE_X54Y211        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_350_363/RAME_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y211        RAMD32 (Prop_E6LUT_SLICEM_CLK_O)
                                                      0.108     3.079 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_350_363/RAME_D1/O
                         net (fo=1, routed)           0.064     3.143    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[359]
    SLICE_X55Y211        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[359]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.354     2.646    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X55Y211        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[359]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_406_419/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[419]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.163ns  (logic 0.105ns (64.417%)  route 0.058ns (35.583%))
  Logic Levels:           0  
  Clock Path Skew:        -0.317ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.668ns
    Source Clock Delay      (SCD):    2.985ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.300ns (routing 0.484ns, distribution 0.816ns)
  Clock Net Delay (Destination): 1.376ns (routing 0.485ns, distribution 0.891ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.300     2.985    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_406_419/WCLK
    SLICE_X53Y194        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_406_419/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y194        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.105     3.090 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_406_419/RAMG_D1/O
                         net (fo=1, routed)           0.058     3.148    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[419]
    SLICE_X52Y194        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[419]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.376     2.668    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X52Y194        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[419]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAME_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[401]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.170ns  (logic 0.108ns (63.529%)  route 0.062ns (36.471%))
  Logic Levels:           0  
  Clock Path Skew:        -0.318ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.665ns
    Source Clock Delay      (SCD):    2.983ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.298ns (routing 0.484ns, distribution 0.814ns)
  Clock Net Delay (Destination): 1.373ns (routing 0.485ns, distribution 0.888ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.298     2.983    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/WCLK
    SLICE_X53Y198        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAME_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y198        RAMD32 (Prop_E6LUT_SLICEM_CLK_O)
                                                      0.108     3.091 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAME_D1/O
                         net (fo=1, routed)           0.062     3.153    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[401]
    SLICE_X53Y199        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[401]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.373     2.665    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X53Y199        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[401]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_434_447/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[445]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.165ns  (logic 0.111ns (67.273%)  route 0.054ns (32.727%))
  Logic Levels:           0  
  Clock Path Skew:        -0.320ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.668ns
    Source Clock Delay      (SCD):    2.988ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.303ns (routing 0.484ns, distribution 0.819ns)
  Clock Net Delay (Destination): 1.376ns (routing 0.485ns, distribution 0.891ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.029     1.292    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.522 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.668    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.685 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.303     2.988    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_434_447/WCLK
    SLICE_X48Y214        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_434_447/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y214        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.111     3.099 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_434_447/RAMF_D1/O
                         net (fo=1, routed)           0.054     3.153    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[445]
    SLICE_X49Y214        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[445]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.376     2.668    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X49Y214        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[445]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  mmcm_clkout0

Max Delay           106 Endpoints
Min Delay           106 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[18]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[18]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.745ns  (logic 0.077ns (10.339%)  route 0.668ns (89.661%))
  Logic Levels:           0  
  Clock Path Skew:        2.315ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.638ns
    Source Clock Delay      (SCD):    2.323ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.097ns (routing 0.662ns, distribution 1.435ns)
  Clock Net Delay (Destination): 1.991ns (routing 0.716ns, distribution 1.275ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.097     2.323    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X56Y104        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[18]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y104        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     2.400 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[18]/Q
                         net (fo=2, routed)           0.668     3.068    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[18]
    SLICE_X56Y104        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[18]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.991     4.638    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X56Y104        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[18]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.730ns  (logic 0.078ns (10.688%)  route 0.652ns (89.312%))
  Logic Levels:           0  
  Clock Path Skew:        2.346ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.678ns
    Source Clock Delay      (SCD):    2.332ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.106ns (routing 0.662ns, distribution 1.444ns)
  Clock Net Delay (Destination): 2.031ns (routing 0.716ns, distribution 1.315ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.106     2.332    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X54Y106        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y106        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     2.410 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[9]/Q
                         net (fo=2, routed)           0.652     3.062    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[9]
    SLICE_X50Y106        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.031     4.678    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X50Y106        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.677ns  (logic 0.079ns (11.669%)  route 0.598ns (88.332%))
  Logic Levels:           0  
  Clock Path Skew:        2.335ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.667ns
    Source Clock Delay      (SCD):    2.332ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.106ns (routing 0.662ns, distribution 1.444ns)
  Clock Net Delay (Destination): 2.020ns (routing 0.716ns, distribution 1.304ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.106     2.332    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X54Y106        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y106        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     2.411 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[13]/Q
                         net (fo=2, routed)           0.598     3.009    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[13]
    SLICE_X50Y104        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.020     4.667    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X50Y104        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg3_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/start_reg_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.696ns  (logic 0.079ns (11.350%)  route 0.617ns (88.650%))
  Logic Levels:           0  
  Clock Path Skew:        2.328ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.634ns
    Source Clock Delay      (SCD):    2.306ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.080ns (routing 0.662ns, distribution 1.418ns)
  Clock Net Delay (Destination): 1.987ns (routing 0.716ns, distribution 1.271ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.080     2.306    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X52Y104        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg3_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y104        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.385 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg3_reg[0]/Q
                         net (fo=2, routed)           0.617     3.002    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/start_reg_resync_i/WSTART_REG
    SLICE_X56Y127        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/start_reg_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.987     4.634    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/start_reg_resync_i/aclk
    SLICE_X56Y127        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/start_reg_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.672ns  (logic 0.079ns (11.755%)  route 0.593ns (88.245%))
  Logic Levels:           0  
  Clock Path Skew:        2.359ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.667ns
    Source Clock Delay      (SCD):    2.308ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.082ns (routing 0.662ns, distribution 1.420ns)
  Clock Net Delay (Destination): 2.020ns (routing 0.716ns, distribution 1.304ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.082     2.308    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X50Y104        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y104        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.387 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[6]/Q
                         net (fo=2, routed)           0.593     2.980    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[6]
    SLICE_X50Y104        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.020     4.667    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X50Y104        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.635ns  (logic 0.079ns (12.443%)  route 0.556ns (87.557%))
  Logic Levels:           0  
  Clock Path Skew:        2.335ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.667ns
    Source Clock Delay      (SCD):    2.332ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.106ns (routing 0.662ns, distribution 1.444ns)
  Clock Net Delay (Destination): 2.020ns (routing 0.716ns, distribution 1.304ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.106     2.332    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X54Y106        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y106        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     2.411 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[8]/Q
                         net (fo=2, routed)           0.556     2.967    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[8]
    SLICE_X50Y104        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.020     4.667    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X50Y104        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[28]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.656ns  (logic 0.079ns (12.042%)  route 0.577ns (87.958%))
  Logic Levels:           0  
  Clock Path Skew:        2.331ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.641ns
    Source Clock Delay      (SCD):    2.310ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.084ns (routing 0.662ns, distribution 1.422ns)
  Clock Net Delay (Destination): 1.994ns (routing 0.716ns, distribution 1.278ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.084     2.310    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X59Y105        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y105        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     2.389 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[28]/Q
                         net (fo=2, routed)           0.577     2.966    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[28]
    SLICE_X57Y116        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[28]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.994     4.641    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X57Y116        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[28]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[18]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[18]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.646ns  (logic 0.076ns (11.764%)  route 0.570ns (88.236%))
  Logic Levels:           0  
  Clock Path Skew:        2.339ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.636ns
    Source Clock Delay      (SCD):    2.297ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.071ns (routing 0.662ns, distribution 1.409ns)
  Clock Net Delay (Destination): 1.989ns (routing 0.716ns, distribution 1.273ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.071     2.297    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X54Y103        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[18]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y103        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     2.373 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[18]/Q
                         net (fo=2, routed)           0.570     2.943    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[18]
    SLICE_X60Y119        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[18]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.989     4.636    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X60Y119        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[18]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.597ns  (logic 0.076ns (12.730%)  route 0.521ns (87.270%))
  Logic Levels:           0  
  Clock Path Skew:        2.335ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.667ns
    Source Clock Delay      (SCD):    2.332ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.106ns (routing 0.662ns, distribution 1.444ns)
  Clock Net Delay (Destination): 2.020ns (routing 0.716ns, distribution 1.304ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.106     2.332    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X54Y106        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y106        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.408 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[10]/Q
                         net (fo=2, routed)           0.521     2.929    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[10]
    SLICE_X50Y104        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.020     4.667    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X50Y104        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.629ns  (logic 0.078ns (12.405%)  route 0.551ns (87.595%))
  Logic Levels:           0  
  Clock Path Skew:        2.339ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.636ns
    Source Clock Delay      (SCD):    2.297ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.071ns (routing 0.662ns, distribution 1.409ns)
  Clock Net Delay (Destination): 1.989ns (routing 0.716ns, distribution 1.273ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.071     2.297    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X54Y103        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y103        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     2.375 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[20]/Q
                         net (fo=2, routed)           0.551     2.926    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[20]
    SLICE_X60Y119        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.989     4.636    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X60Y119        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[20]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.111ns  (logic 0.040ns (36.139%)  route 0.071ns (63.861%))
  Logic Levels:           0  
  Clock Path Skew:        1.458ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.717ns
    Source Clock Delay      (SCD):    1.259ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.139ns (routing 0.359ns, distribution 0.780ns)
  Clock Net Delay (Destination): 1.425ns (routing 0.485ns, distribution 0.940ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.139     1.259    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X50Y104        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y104        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.299 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[1]/Q
                         net (fo=2, routed)           0.071     1.370    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[1]
    SLICE_X50Y106        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.425     2.717    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X50Y106        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[16]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.038ns (31.550%)  route 0.082ns (68.450%))
  Logic Levels:           0  
  Clock Path Skew:        1.445ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.702ns
    Source Clock Delay      (SCD):    1.257ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.137ns (routing 0.359ns, distribution 0.778ns)
  Clock Net Delay (Destination): 1.410ns (routing 0.485ns, distribution 0.925ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.137     1.257    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X54Y103        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y103        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.295 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[16]/Q
                         net (fo=2, routed)           0.082     1.377    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[16]
    SLICE_X54Y103        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[16]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.410     2.702    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X54Y103        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[16]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.041ns (33.973%)  route 0.080ns (66.027%))
  Logic Levels:           0  
  Clock Path Skew:        1.449ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.708ns
    Source Clock Delay      (SCD):    1.259ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.139ns (routing 0.359ns, distribution 0.780ns)
  Clock Net Delay (Destination): 1.416ns (routing 0.485ns, distribution 0.931ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.139     1.259    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X50Y105        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y105        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.300 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[7]/Q
                         net (fo=2, routed)           0.080     1.380    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RLENGTH_REG[7]
    SLICE_X50Y105        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.416     2.708    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X50Y105        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.040ns (32.370%)  route 0.084ns (67.630%))
  Logic Levels:           0  
  Clock Path Skew:        1.435ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.693ns
    Source Clock Delay      (SCD):    1.258ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.138ns (routing 0.359ns, distribution 0.779ns)
  Clock Net Delay (Destination): 1.401ns (routing 0.485ns, distribution 0.916ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.138     1.258    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X57Y110        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y110        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     1.298 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[15]/Q
                         net (fo=2, routed)           0.084     1.382    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[15]
    SLICE_X57Y110        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.401     2.693    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X57Y110        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.041ns (32.883%)  route 0.084ns (67.117%))
  Logic Levels:           0  
  Clock Path Skew:        1.435ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.693ns
    Source Clock Delay      (SCD):    1.258ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.138ns (routing 0.359ns, distribution 0.779ns)
  Clock Net Delay (Destination): 1.401ns (routing 0.485ns, distribution 0.916ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.138     1.258    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X57Y110        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y110        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.299 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[9]/Q
                         net (fo=2, routed)           0.084     1.383    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[9]
    SLICE_X57Y110        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.401     2.693    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X57Y110        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[23]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.041ns (31.861%)  route 0.088ns (68.139%))
  Logic Levels:           0  
  Clock Path Skew:        1.449ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.706ns
    Source Clock Delay      (SCD):    1.257ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.137ns (routing 0.359ns, distribution 0.778ns)
  Clock Net Delay (Destination): 1.414ns (routing 0.485ns, distribution 0.929ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.137     1.257    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X50Y101        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y101        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.298 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[23]/Q
                         net (fo=2, routed)           0.088     1.386    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[23]
    SLICE_X50Y101        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[23]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.414     2.706    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X50Y101        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[23]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.128ns  (logic 0.041ns (32.075%)  route 0.087ns (67.925%))
  Logic Levels:           0  
  Clock Path Skew:        1.449ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.707ns
    Source Clock Delay      (SCD):    1.258ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.138ns (routing 0.359ns, distribution 0.779ns)
  Clock Net Delay (Destination): 1.415ns (routing 0.485ns, distribution 0.930ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.138     1.258    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X50Y102        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y102        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.299 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[31]/Q
                         net (fo=2, routed)           0.087     1.386    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[31]
    SLICE_X50Y102        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.415     2.707    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X50Y102        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[31]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[25]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.131ns  (logic 0.040ns (30.548%)  route 0.091ns (69.452%))
  Logic Levels:           0  
  Clock Path Skew:        1.435ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.690ns
    Source Clock Delay      (SCD):    1.255ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.135ns (routing 0.359ns, distribution 0.776ns)
  Clock Net Delay (Destination): 1.398ns (routing 0.485ns, distribution 0.913ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.135     1.255    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X57Y103        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y103        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.295 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[25]/Q
                         net (fo=2, routed)           0.091     1.386    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[25]
    SLICE_X57Y103        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[25]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.398     2.690    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X57Y103        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[25]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.122ns  (logic 0.038ns (31.229%)  route 0.084ns (68.771%))
  Logic Levels:           0  
  Clock Path Skew:        1.427ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.692ns
    Source Clock Delay      (SCD):    1.265ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.145ns (routing 0.359ns, distribution 0.786ns)
  Clock Net Delay (Destination): 1.400ns (routing 0.485ns, distribution 0.915ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.145     1.265    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X56Y105        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y105        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.303 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[10]/Q
                         net (fo=2, routed)           0.084     1.387    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[10]
    SLICE_X56Y105        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.400     2.692    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X56Y105        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.130ns  (logic 0.039ns (29.957%)  route 0.091ns (70.043%))
  Logic Levels:           0  
  Clock Path Skew:        1.449ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.706ns
    Source Clock Delay      (SCD):    1.257ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.137ns (routing 0.359ns, distribution 0.778ns)
  Clock Net Delay (Destination): 1.414ns (routing 0.485ns, distribution 0.929ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.137     1.257    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X50Y101        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y101        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.296 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[20]/Q
                         net (fo=2, routed)           0.091     1.387    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[20]
    SLICE_X50Y101        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.414     2.706    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X50Y101        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[20]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout0

Max Delay            68 Endpoints
Min Delay            68 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.797ns  (logic 0.079ns (2.825%)  route 2.718ns (97.175%))
  Logic Levels:           0  
  Clock Path Skew:        0.281ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.773ns
    Source Clock Delay      (SCD):    4.492ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.282ns (routing 0.788ns, distribution 1.494ns)
  Clock Net Delay (Destination): 2.126ns (routing 0.716ns, distribution 1.410ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.282     4.492    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X40Y176        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y176        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.571 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.718     7.288    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X28Y108        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.126     4.773    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X28Y108        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.797ns  (logic 0.079ns (2.825%)  route 2.718ns (97.175%))
  Logic Levels:           0  
  Clock Path Skew:        0.281ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.773ns
    Source Clock Delay      (SCD):    4.492ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.282ns (routing 0.788ns, distribution 1.494ns)
  Clock Net Delay (Destination): 2.126ns (routing 0.716ns, distribution 1.410ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.282     4.492    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X40Y176        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y176        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.571 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.718     7.288    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X28Y108        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.126     4.773    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X28Y108        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.797ns  (logic 0.079ns (2.825%)  route 2.718ns (97.175%))
  Logic Levels:           0  
  Clock Path Skew:        0.281ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.773ns
    Source Clock Delay      (SCD):    4.492ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.282ns (routing 0.788ns, distribution 1.494ns)
  Clock Net Delay (Destination): 2.126ns (routing 0.716ns, distribution 1.410ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.282     4.492    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X40Y176        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y176        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.571 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.718     7.288    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X28Y108        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.126     4.773    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X28Y108        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.608ns  (logic 0.079ns (3.030%)  route 2.529ns (96.970%))
  Logic Levels:           0  
  Clock Path Skew:        0.293ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.785ns
    Source Clock Delay      (SCD):    4.492ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.282ns (routing 0.788ns, distribution 1.494ns)
  Clock Net Delay (Destination): 2.138ns (routing 0.716ns, distribution 1.422ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.282     4.492    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X40Y176        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y176        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.571 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.529     7.099    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X28Y114        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.138     4.785    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X28Y114        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.608ns  (logic 0.079ns (3.030%)  route 2.529ns (96.970%))
  Logic Levels:           0  
  Clock Path Skew:        0.293ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.785ns
    Source Clock Delay      (SCD):    4.492ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.282ns (routing 0.788ns, distribution 1.494ns)
  Clock Net Delay (Destination): 2.138ns (routing 0.716ns, distribution 1.422ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.282     4.492    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X40Y176        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y176        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.571 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.529     7.099    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X28Y114        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.138     4.785    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X28Y114        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.608ns  (logic 0.079ns (3.030%)  route 2.529ns (96.970%))
  Logic Levels:           0  
  Clock Path Skew:        0.293ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.785ns
    Source Clock Delay      (SCD):    4.492ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.282ns (routing 0.788ns, distribution 1.494ns)
  Clock Net Delay (Destination): 2.138ns (routing 0.716ns, distribution 1.422ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.282     4.492    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X40Y176        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y176        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.571 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.529     7.099    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X28Y114        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.138     4.785    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X28Y114        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.493ns  (logic 0.079ns (3.169%)  route 2.414ns (96.831%))
  Logic Levels:           0  
  Clock Path Skew:        0.079ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.571ns
    Source Clock Delay      (SCD):    4.492ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.282ns (routing 0.788ns, distribution 1.494ns)
  Clock Net Delay (Destination): 1.924ns (routing 0.716ns, distribution 1.208ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.282     4.492    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X40Y176        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y176        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.571 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.414     6.985    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X74Y107        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.924     4.571    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X74Y107        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.493ns  (logic 0.079ns (3.169%)  route 2.414ns (96.831%))
  Logic Levels:           0  
  Clock Path Skew:        0.079ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.571ns
    Source Clock Delay      (SCD):    4.492ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.282ns (routing 0.788ns, distribution 1.494ns)
  Clock Net Delay (Destination): 1.924ns (routing 0.716ns, distribution 1.208ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.282     4.492    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X40Y176        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y176        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.571 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.414     6.985    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X74Y107        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.924     4.571    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X74Y107        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.493ns  (logic 0.079ns (3.169%)  route 2.414ns (96.831%))
  Logic Levels:           0  
  Clock Path Skew:        0.079ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.571ns
    Source Clock Delay      (SCD):    4.492ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.282ns (routing 0.788ns, distribution 1.494ns)
  Clock Net Delay (Destination): 1.924ns (routing 0.716ns, distribution 1.208ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.282     4.492    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X40Y176        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y176        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.571 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.414     6.985    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X74Y107        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.924     4.571    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X74Y107        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.243ns  (logic 0.079ns (3.521%)  route 2.164ns (96.479%))
  Logic Levels:           0  
  Clock Path Skew:        0.191ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.683ns
    Source Clock Delay      (SCD):    4.492ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.282ns (routing 0.788ns, distribution 1.494ns)
  Clock Net Delay (Destination): 2.036ns (routing 0.716ns, distribution 1.320ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.282     4.492    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X40Y176        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y176        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.571 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.164     6.735    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X50Y110        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.036     4.683    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X50Y110        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.325ns  (logic 0.039ns (11.984%)  route 0.286ns (88.016%))
  Logic Levels:           0  
  Clock Path Skew:        -0.138ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.675ns
    Source Clock Delay      (SCD):    2.813ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.258ns (routing 0.435ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.383ns (routing 0.485ns, distribution 0.898ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.258     2.813    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X40Y176        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y176        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.852 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.286     3.138    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X50Y180        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.383     2.675    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X50Y180        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.325ns  (logic 0.039ns (11.984%)  route 0.286ns (88.016%))
  Logic Levels:           0  
  Clock Path Skew:        -0.138ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.675ns
    Source Clock Delay      (SCD):    2.813ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.258ns (routing 0.435ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.383ns (routing 0.485ns, distribution 0.898ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.258     2.813    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X40Y176        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y176        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.852 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.286     3.138    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X50Y180        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.383     2.675    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X50Y180        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.325ns  (logic 0.039ns (11.984%)  route 0.286ns (88.016%))
  Logic Levels:           0  
  Clock Path Skew:        -0.138ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.675ns
    Source Clock Delay      (SCD):    2.813ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.258ns (routing 0.435ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.383ns (routing 0.485ns, distribution 0.898ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.258     2.813    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X40Y176        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y176        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.852 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.286     3.138    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X50Y180        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.383     2.675    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X50Y180        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/div_clk_rst_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.453ns  (logic 0.039ns (8.609%)  route 0.414ns (91.391%))
  Logic Levels:           0  
  Clock Path Skew:        -0.046ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.644ns
    Source Clock Delay      (SCD):    2.690ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.135ns (routing 0.435ns, distribution 0.700ns)
  Clock Net Delay (Destination): 1.352ns (routing 0.485ns, distribution 0.867ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.135     2.690    d_1_i/ddr4/ddr4_0/inst/c0_ddr4_ui_clk
    SLICE_X82Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/div_clk_rst_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y316        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     2.729 r  d_1_i/ddr4/ddr4_0/inst/div_clk_rst_r1_reg/Q
                         net (fo=1, routed)           0.414     3.143    d_1_i/ddr4/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/ext_reset_in
    SLICE_X78Y316        FDRE                                         r  d_1_i/ddr4/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.352     2.644    d_1_i/ddr4/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/slowest_sync_clk
    SLICE_X78Y316        FDRE                                         r  d_1_i/ddr4/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.407ns  (logic 0.039ns (9.592%)  route 0.368ns (90.408%))
  Logic Levels:           0  
  Clock Path Skew:        -0.073ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.740ns
    Source Clock Delay      (SCD):    2.813ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.258ns (routing 0.435ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.448ns (routing 0.485ns, distribution 0.963ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.258     2.813    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X40Y176        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y176        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.852 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.368     3.219    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X36Y160        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.448     2.740    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X36Y160        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.407ns  (logic 0.039ns (9.592%)  route 0.368ns (90.408%))
  Logic Levels:           0  
  Clock Path Skew:        -0.073ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.740ns
    Source Clock Delay      (SCD):    2.813ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.258ns (routing 0.435ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.448ns (routing 0.485ns, distribution 0.963ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.258     2.813    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X40Y176        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y176        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.852 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.368     3.219    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X36Y160        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.448     2.740    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X36Y160        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.407ns  (logic 0.039ns (9.592%)  route 0.368ns (90.408%))
  Logic Levels:           0  
  Clock Path Skew:        -0.073ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.740ns
    Source Clock Delay      (SCD):    2.813ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.258ns (routing 0.435ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.448ns (routing 0.485ns, distribution 0.963ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.258     2.813    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X40Y176        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y176        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.852 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.368     3.219    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X36Y160        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.448     2.740    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X36Y160        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.574ns  (logic 0.061ns (10.627%)  route 0.513ns (89.373%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -0.044ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.692ns
    Source Clock Delay      (SCD):    2.736ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.181ns (routing 0.435ns, distribution 0.746ns)
  Clock Net Delay (Destination): 1.400ns (routing 0.485ns, distribution 0.915ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.181     2.736    d_1_i/ddr4/rst_ddr4/U0/slowest_sync_clk
    SLICE_X62Y223        FDRE                                         r  d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y223        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.775 f  d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           0.376     3.151    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/aresetn
    SLICE_X44Y194        LUT1 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.022     3.173 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.137     3.310    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/asr_d1
    SLICE_X42Y192        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.400     2.692    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/aclk
    SLICE_X42Y192        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.561ns  (logic 0.039ns (6.951%)  route 0.522ns (93.049%))
  Logic Levels:           0  
  Clock Path Skew:        -0.130ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.683ns
    Source Clock Delay      (SCD):    2.813ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.258ns (routing 0.435ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.391ns (routing 0.485ns, distribution 0.906ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.258     2.813    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X40Y176        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y176        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.852 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.522     3.374    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X38Y225        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.391     2.683    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X38Y225        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.561ns  (logic 0.039ns (6.951%)  route 0.522ns (93.049%))
  Logic Levels:           0  
  Clock Path Skew:        -0.130ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.683ns
    Source Clock Delay      (SCD):    2.813ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.258ns (routing 0.435ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.391ns (routing 0.485ns, distribution 0.906ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.258     2.813    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X40Y176        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y176        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.852 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.522     3.374    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X38Y225        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.391     2.683    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X38Y225        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout0

Max Delay             0 Endpoints
Min Delay            28 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[10].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.097ns  (logic 0.039ns (40.206%)  route 0.058ns (59.794%))
  Logic Levels:           0  
  Clock Path Skew:        0.393ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.561ns
    Source Clock Delay      (SCD):    2.168ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.619ns (routing 0.096ns, distribution 0.523ns)
  Clock Net Delay (Destination): 1.270ns (routing 0.485ns, distribution 0.785ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.619     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X96Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y313        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     2.207 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[10]/Q
                         net (fo=1, routed)           0.058     2.265    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[10]
    SLICE_X95Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[10].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.270     2.561    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[1]_0
    SLICE_X95Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[10].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_en_lvl_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.037ns (37.755%)  route 0.061ns (62.245%))
  Logic Levels:           0  
  Clock Path Skew:        0.387ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.554ns
    Source Clock Delay      (SCD):    2.167ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.618ns (routing 0.096ns, distribution 0.522ns)
  Clock Net Delay (Destination): 1.262ns (routing 0.485ns, distribution 0.777ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.618     2.167    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X96Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_en_lvl_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y315        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.204 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_en_lvl_reg/Q
                         net (fo=2, routed)           0.061     2.265    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/D[0]
    SLICE_X96Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.262     2.554    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/SYNC[0].sync_reg_reg[0]_0
    SLICE_X96Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.394%)  route 0.060ns (60.606%))
  Logic Levels:           0  
  Clock Path Skew:        0.393ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.561ns
    Source Clock Delay      (SCD):    2.168ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.619ns (routing 0.096ns, distribution 0.523ns)
  Clock Net Delay (Destination): 1.270ns (routing 0.485ns, distribution 0.785ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.619     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X96Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y313        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     2.207 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[2]/Q
                         net (fo=1, routed)           0.060     2.267    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[2]
    SLICE_X95Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.270     2.561    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[1]_0
    SLICE_X95Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[2].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.039ns (32.231%)  route 0.082ns (67.769%))
  Logic Levels:           0  
  Clock Path Skew:        0.398ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.565ns
    Source Clock Delay      (SCD):    2.167ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.618ns (routing 0.096ns, distribution 0.522ns)
  Clock Net Delay (Destination): 1.274ns (routing 0.485ns, distribution 0.789ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.618     2.167    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X96Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y315        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     2.206 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[3]/Q
                         net (fo=1, routed)           0.082     2.288    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[3]
    SLICE_X95Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.274     2.565    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[1]_0
    SLICE_X95Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[3].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.038ns (29.921%)  route 0.089ns (70.079%))
  Logic Levels:           0  
  Clock Path Skew:        0.394ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.564ns
    Source Clock Delay      (SCD):    2.171ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.622ns (routing 0.096ns, distribution 0.526ns)
  Clock Net Delay (Destination): 1.273ns (routing 0.485ns, distribution 0.788ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.622     2.171    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X94Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y314        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.209 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[8]/Q
                         net (fo=1, routed)           0.089     2.298    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[8]
    SLICE_X94Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.273     2.564    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[1]_0
    SLICE_X94Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[8].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.128ns  (logic 0.039ns (30.469%)  route 0.089ns (69.531%))
  Logic Levels:           0  
  Clock Path Skew:        0.393ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.563ns
    Source Clock Delay      (SCD):    2.171ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.622ns (routing 0.096ns, distribution 0.526ns)
  Clock Net Delay (Destination): 1.272ns (routing 0.485ns, distribution 0.787ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.622     2.171    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X94Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y314        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[15]/Q
                         net (fo=1, routed)           0.089     2.299    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[15]
    SLICE_X94Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.272     2.563    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[1]_0
    SLICE_X94Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[12].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.128ns  (logic 0.040ns (31.250%)  route 0.088ns (68.750%))
  Logic Levels:           0  
  Clock Path Skew:        0.393ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.563ns
    Source Clock Delay      (SCD):    2.171ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.622ns (routing 0.096ns, distribution 0.526ns)
  Clock Net Delay (Destination): 1.272ns (routing 0.485ns, distribution 0.787ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.622     2.171    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X94Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y314        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.040     2.211 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[12]/Q
                         net (fo=1, routed)           0.088     2.299    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[12]
    SLICE_X94Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[12].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.272     2.563    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[1]_0
    SLICE_X94Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[12].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.134ns  (logic 0.039ns (29.104%)  route 0.095ns (70.896%))
  Logic Levels:           0  
  Clock Path Skew:        0.397ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.566ns
    Source Clock Delay      (SCD):    2.169ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.620ns (routing 0.096ns, distribution 0.524ns)
  Clock Net Delay (Destination): 1.275ns (routing 0.485ns, distribution 0.790ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.620     2.169    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X93Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y312        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     2.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[6]/Q
                         net (fo=1, routed)           0.095     2.303    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[6]
    SLICE_X94Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.275     2.566    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[1]_0
    SLICE_X94Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[6].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.132ns  (logic 0.039ns (29.545%)  route 0.093ns (70.455%))
  Logic Levels:           0  
  Clock Path Skew:        0.381ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.555ns
    Source Clock Delay      (SCD):    2.174ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.625ns (routing 0.096ns, distribution 0.529ns)
  Clock Net Delay (Destination): 1.263ns (routing 0.485ns, distribution 0.778ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.625     2.174    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X94Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y312        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     2.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[0]/Q
                         net (fo=1, routed)           0.093     2.306    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[0]
    SLICE_X94Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.263     2.555    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[1]_0
    SLICE_X94Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.132ns  (logic 0.039ns (29.545%)  route 0.093ns (70.455%))
  Logic Levels:           0  
  Clock Path Skew:        0.380ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.555ns
    Source Clock Delay      (SCD):    2.175ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.626ns (routing 0.096ns, distribution 0.530ns)
  Clock Net Delay (Destination): 1.263ns (routing 0.485ns, distribution 0.778ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.626     2.175    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X94Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y311        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     2.214 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[1]/Q
                         net (fo=1, routed)           0.093     2.307    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[1]
    SLICE_X94Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.263     2.555    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[1]_0
    SLICE_X94Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[1].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout0

Max Delay             0 Endpoints
Min Delay           129 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_low_riuclk_int_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.107ns  (logic 0.038ns (35.614%)  route 0.069ns (64.386%))
  Logic Levels:           0  
  Clock Path Skew:        -0.139ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.531ns
    Source Clock Delay      (SCD):    2.670ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.105ns (routing 0.439ns, distribution 0.666ns)
  Clock Net Delay (Destination): 1.239ns (routing 0.485ns, distribution 0.754ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.105     2.670    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y180        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_low_riuclk_int_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y180        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.708 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_low_riuclk_int_reg[0]/Q
                         net (fo=2, routed)           0.069     2.777    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/phy2clb_fixdly_rdy_low_riuclk[0]
    SLICE_X81Y180        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.239     2.531    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[19].sync_reg_reg[1]_0
    SLICE_X81Y180        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_low_riuclk_int_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.122ns  (logic 0.039ns (32.051%)  route 0.083ns (67.950%))
  Logic Levels:           0  
  Clock Path Skew:        -0.139ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.517ns
    Source Clock Delay      (SCD):    2.656ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.091ns (routing 0.439ns, distribution 0.652ns)
  Clock Net Delay (Destination): 1.225ns (routing 0.485ns, distribution 0.740ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.091     2.656    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y211        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_low_riuclk_int_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y211        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     2.695 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_low_riuclk_int_reg[1]/Q
                         net (fo=2, routed)           0.083     2.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/phy2clb_phy_rdy_low_riuclk[1]
    SLICE_X81Y212        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.225     2.517    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[19].sync_reg_reg[1]_0
    SLICE_X81Y212        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[1].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.039ns (32.475%)  route 0.081ns (67.525%))
  Logic Levels:           0  
  Clock Path Skew:        -0.146ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.525ns
    Source Clock Delay      (SCD):    2.671ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.106ns (routing 0.439ns, distribution 0.667ns)
  Clock Net Delay (Destination): 1.233ns (routing 0.485ns, distribution 0.748ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.106     2.671    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y191        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y191        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.710 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[0]/Q
                         net (fo=2, routed)           0.081     2.791    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/phy2clb_fixdly_rdy_upp_riuclk[0]
    SLICE_X81Y191        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.233     2.525    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[19].sync_reg_reg[1]_0
    SLICE_X81Y191        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.394%)  route 0.060ns (60.606%))
  Logic Levels:           0  
  Clock Path Skew:        -0.131ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.562ns
    Source Clock Delay      (SCD):    2.693ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.128ns (routing 0.439ns, distribution 0.689ns)
  Clock Net Delay (Destination): 1.271ns (routing 0.485ns, distribution 0.786ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.128     2.693    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X84Y295        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y295        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.732 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[4]/Q
                         net (fo=1, routed)           0.060     2.792    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[4]
    SLICE_X84Y294        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.271     2.562    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X84Y294        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[4].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[17].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.114ns  (logic 0.039ns (34.211%)  route 0.075ns (65.790%))
  Logic Levels:           0  
  Clock Path Skew:        -0.143ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.539ns
    Source Clock Delay      (SCD):    2.682ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.117ns (routing 0.439ns, distribution 0.678ns)
  Clock Net Delay (Destination): 1.247ns (routing 0.485ns, distribution 0.762ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.117     2.682    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y288        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y288        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.721 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[17]/Q
                         net (fo=1, routed)           0.075     2.796    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[17]
    SLICE_X88Y288        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[17].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.247     2.539    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X88Y288        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[17].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[10].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.109ns  (logic 0.038ns (34.862%)  route 0.071ns (65.138%))
  Logic Levels:           0  
  Clock Path Skew:        -0.124ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.563ns
    Source Clock Delay      (SCD):    2.687ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.122ns (routing 0.439ns, distribution 0.683ns)
  Clock Net Delay (Destination): 1.272ns (routing 0.485ns, distribution 0.787ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.122     2.687    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X89Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y337        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.725 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[10]/Q
                         net (fo=1, routed)           0.071     2.796    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[10]
    SLICE_X87Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[10].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.272     2.563    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X87Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[10].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.130ns  (logic 0.040ns (30.769%)  route 0.090ns (69.231%))
  Logic Levels:           0  
  Clock Path Skew:        -0.146ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.525ns
    Source Clock Delay      (SCD):    2.671ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.106ns (routing 0.439ns, distribution 0.667ns)
  Clock Net Delay (Destination): 1.233ns (routing 0.485ns, distribution 0.748ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.106     2.671    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y191        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y191        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.711 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[1]/Q
                         net (fo=2, routed)           0.090     2.801    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/phy2clb_fixdly_rdy_upp_riuclk[1]
    SLICE_X81Y191        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.233     2.525    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[19].sync_reg_reg[1]_0
    SLICE_X81Y191        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[1].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[16].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.113ns  (logic 0.039ns (34.513%)  route 0.074ns (65.487%))
  Logic Levels:           0  
  Clock Path Skew:        -0.147ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.541ns
    Source Clock Delay      (SCD):    2.688ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.123ns (routing 0.439ns, distribution 0.684ns)
  Clock Net Delay (Destination): 1.249ns (routing 0.485ns, distribution 0.764ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.123     2.688    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X85Y291        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y291        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.727 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[16]/Q
                         net (fo=1, routed)           0.074     2.801    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[16]
    SLICE_X85Y291        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[16].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.249     2.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X85Y291        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[16].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.097ns  (logic 0.039ns (40.046%)  route 0.058ns (59.954%))
  Logic Levels:           0  
  Clock Path Skew:        -0.139ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.567ns
    Source Clock Delay      (SCD):    2.706ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.141ns (routing 0.439ns, distribution 0.702ns)
  Clock Net Delay (Destination): 1.275ns (routing 0.485ns, distribution 0.790ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.141     2.706    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y310        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y310        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     2.745 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[6]/Q
                         net (fo=2, routed)           0.058     2.803    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/phy2clb_fixdly_rdy_upp_riuclk[6]
    SLICE_X81Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.275     2.567    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[19].sync_reg_reg[1]_0
    SLICE_X81Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[6].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.116ns  (logic 0.040ns (34.483%)  route 0.076ns (65.517%))
  Logic Levels:           0  
  Clock Path Skew:        -0.147ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.542ns
    Source Clock Delay      (SCD):    2.689ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.124ns (routing 0.439ns, distribution 0.685ns)
  Clock Net Delay (Destination): 1.250ns (routing 0.485ns, distribution 0.765ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.124     2.689    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X85Y297        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y297        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.729 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[6]/Q
                         net (fo=1, routed)           0.076     2.805    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[6]
    SLICE_X85Y297        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.250     2.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X85Y297        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[6].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  sys_clk_ddr4_clk_p
  To Clock:  mmcm_clkout0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.286ns  (logic 0.081ns (28.318%)  route 0.205ns (71.682%))
  Logic Levels:           0  
  Clock Path Skew:        2.260ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.481ns
    Source Clock Delay      (SCD):    2.221ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.135ns (routing 0.171ns, distribution 0.964ns)
  Clock Net Delay (Destination): 1.834ns (routing 0.716ns, distribution 1.118ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.135     2.221    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y343        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.302 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.205     2.507    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X81Y344        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.834     4.481    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk_0
    SLICE_X81Y344        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.123ns  (logic 0.040ns (32.604%)  route 0.083ns (67.396%))
  Logic Levels:           0  
  Clock Path Skew:        1.312ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.575ns
    Source Clock Delay      (SCD):    1.263ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.646ns (routing 0.096ns, distribution 0.550ns)
  Clock Net Delay (Destination): 1.284ns (routing 0.485ns, distribution 0.799ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.646     1.263    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y343        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.083     1.386    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X81Y344        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.292 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.284     2.575    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk_0
    SLICE_X81Y344        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  mmcm_clkout5

Max Delay            78 Endpoints
Min Delay            86 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.869ns  (logic 0.305ns (35.098%)  route 0.564ns (64.902%))
  Logic Levels:           0  
  Clock Path Skew:        -7.323ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.570ns
    Source Clock Delay      (SCD):    10.893ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.958ns (routing 1.680ns, distribution 1.278ns)
  Clock Net Delay (Destination): 0.931ns (routing 0.155ns, distribution 0.776ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.958    10.893    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X99Y296        RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y296        RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.305    11.198 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/O
                         net (fo=1, routed)           0.564    11.762    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[1]
    SLICE_X96Y296        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.639 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.931     3.570    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X96Y296        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMF/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.827ns  (logic 0.295ns (35.671%)  route 0.532ns (64.329%))
  Logic Levels:           0  
  Clock Path Skew:        -7.323ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.570ns
    Source Clock Delay      (SCD):    10.893ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.958ns (routing 1.680ns, distribution 1.278ns)
  Clock Net Delay (Destination): 0.931ns (routing 0.155ns, distribution 0.776ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.958    10.893    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X99Y296        RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMF/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y296        RAMD32 (Prop_F5LUT_SLICEM_CLK_O)
                                                      0.295    11.188 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMF/O
                         net (fo=1, routed)           0.532    11.720    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[10]
    SLICE_X96Y296        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.639 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.931     3.570    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X96Y296        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[10]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.804ns  (logic 0.295ns (36.692%)  route 0.509ns (63.308%))
  Logic Levels:           0  
  Clock Path Skew:        -7.273ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.620ns
    Source Clock Delay      (SCD):    10.893ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.958ns (routing 1.680ns, distribution 1.278ns)
  Clock Net Delay (Destination): 0.981ns (routing 0.155ns, distribution 0.826ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.958    10.893    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X99Y296        RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y296        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.295    11.188 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMG_D1/O
                         net (fo=1, routed)           0.509    11.697    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[13]
    SLICE_X100Y298       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.639 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.981     3.620    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X100Y298       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[13]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.789ns  (logic 0.301ns (38.150%)  route 0.488ns (61.850%))
  Logic Levels:           0  
  Clock Path Skew:        -7.322ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.571ns
    Source Clock Delay      (SCD):    10.893ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.958ns (routing 1.680ns, distribution 1.278ns)
  Clock Net Delay (Destination): 0.932ns (routing 0.155ns, distribution 0.777ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.958    10.893    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X99Y296        RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y296        RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.301    11.194 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD_D1/O
                         net (fo=1, routed)           0.488    11.682    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[7]
    SLICE_X96Y296        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.639 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.932     3.571    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X96Y296        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[7]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_en_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.797ns  (logic 0.081ns (10.167%)  route 0.716ns (89.833%))
  Logic Levels:           0  
  Clock Path Skew:        -7.188ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.673ns
    Source Clock Delay      (SCD):    10.861ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.926ns (routing 1.680ns, distribution 1.246ns)
  Clock Net Delay (Destination): 1.034ns (routing 0.155ns, distribution 0.879ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.926    10.861    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y298       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y298       FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081    10.942 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/Q
                         net (fo=19, routed)          0.716    11.658    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp
    SLICE_X103Y302       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_en_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.639 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.034     3.673    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X103Y302       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_en_1_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.729ns  (logic 0.292ns (40.055%)  route 0.437ns (59.945%))
  Logic Levels:           0  
  Clock Path Skew:        -7.322ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.571ns
    Source Clock Delay      (SCD):    10.893ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.958ns (routing 1.680ns, distribution 1.278ns)
  Clock Net Delay (Destination): 0.932ns (routing 0.155ns, distribution 0.777ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.958    10.893    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X99Y296        RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y296        RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292    11.185 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/O
                         net (fo=1, routed)           0.437    11.622    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[2]
    SLICE_X96Y296        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.639 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.932     3.571    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X96Y296        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[23]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.715ns  (logic 0.079ns (11.052%)  route 0.636ns (88.948%))
  Logic Levels:           0  
  Clock Path Skew:        -7.209ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.677ns
    Source Clock Delay      (SCD):    10.885ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.950ns (routing 1.680ns, distribution 1.270ns)
  Clock Net Delay (Destination): 1.038ns (routing 0.155ns, distribution 0.883ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.950    10.885    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X102Y303       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y303       FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079    10.964 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/Q
                         net (fo=2, routed)           0.636    11.600    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[23]
    SLICE_X104Y303       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[23]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.639 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         1.038     3.677    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X104Y303       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[23]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.703ns  (logic 0.288ns (40.967%)  route 0.415ns (59.033%))
  Logic Levels:           0  
  Clock Path Skew:        -7.322ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.571ns
    Source Clock Delay      (SCD):    10.893ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.958ns (routing 1.680ns, distribution 1.278ns)
  Clock Net Delay (Destination): 0.932ns (routing 0.155ns, distribution 0.777ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.958    10.893    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X99Y296        RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y296        RAMD32 (Prop_C5LUT_SLICEM_CLK_O)
                                                      0.288    11.181 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/O
                         net (fo=1, routed)           0.415    11.596    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[4]
    SLICE_X96Y296        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.639 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.932     3.571    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X96Y296        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[4]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.691ns  (logic 0.307ns (44.428%)  route 0.384ns (55.572%))
  Logic Levels:           0  
  Clock Path Skew:        -7.322ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.571ns
    Source Clock Delay      (SCD):    10.893ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.958ns (routing 1.680ns, distribution 1.278ns)
  Clock Net Delay (Destination): 0.932ns (routing 0.155ns, distribution 0.777ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.958    10.893    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X99Y296        RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y296        RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.307    11.200 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC_D1/O
                         net (fo=1, routed)           0.384    11.584    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[5]
    SLICE_X96Y296        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.639 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.932     3.571    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X96Y296        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[5]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/DP/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.686ns  (logic 0.281ns (40.962%)  route 0.405ns (59.038%))
  Logic Levels:           0  
  Clock Path Skew:        -7.321ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.571ns
    Source Clock Delay      (SCD):    10.892ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.957ns (routing 1.680ns, distribution 1.277ns)
  Clock Net Delay (Destination): 0.932ns (routing 0.155ns, distribution 0.777ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.607     7.907    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.935 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.957    10.892    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/WCLK
    SLICE_X99Y295        RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/DP/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y295        RAMD32 (Prop_G5LUT_SLICEM_CLK_O)
                                                      0.281    11.173 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/DP/O
                         net (fo=1, routed)           0.405    11.578    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[15]
    SLICE_X96Y296        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.639 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.932     3.571    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X96Y296        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[15]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/shift_reg_in_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.105ns  (logic 0.039ns (37.143%)  route 0.066ns (62.857%))
  Logic Levels:           0  
  Clock Path Skew:        -1.936ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.017ns
    Source Clock Delay      (SCD):    3.953ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.603ns (routing 0.916ns, distribution 0.687ns)
  Clock Net Delay (Destination): 0.732ns (routing 0.108ns, distribution 0.624ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.603     3.953    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/m_bscan_tck[0]
    SLICE_X104Y292       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/shift_reg_in_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y292       FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     3.992 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/shift_reg_in_reg[1]/Q
                         net (fo=2, routed)           0.066     4.058    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/shift_reg_in[1]
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.732     2.017    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y293       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.041ns (40.841%)  route 0.059ns (59.159%))
  Logic Levels:           0  
  Clock Path Skew:        -1.924ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.041ns
    Source Clock Delay      (SCD):    3.965ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.615ns (routing 0.916ns, distribution 0.699ns)
  Clock Net Delay (Destination): 0.756ns (routing 0.108ns, distribution 0.648ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.615     3.965    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X102Y303       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y303       FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     4.006 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[15]/Q
                         net (fo=2, routed)           0.059     4.065    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[15]
    SLICE_X102Y302       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.756     2.041    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X102Y302       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[15]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.102ns  (logic 0.041ns (40.022%)  route 0.061ns (59.978%))
  Logic Levels:           0  
  Clock Path Skew:        -1.920ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.044ns
    Source Clock Delay      (SCD):    3.965ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.615ns (routing 0.916ns, distribution 0.699ns)
  Clock Net Delay (Destination): 0.759ns (routing 0.108ns, distribution 0.651ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.615     3.965    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X102Y304       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y304       FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     4.006 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[1]/Q
                         net (fo=2, routed)           0.061     4.067    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[1]
    SLICE_X102Y305       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.759     2.044    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X102Y305       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.103ns  (logic 0.040ns (38.955%)  route 0.063ns (61.045%))
  Logic Levels:           0  
  Clock Path Skew:        -1.928ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.040ns
    Source Clock Delay      (SCD):    3.968ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.618ns (routing 0.916ns, distribution 0.702ns)
  Clock Net Delay (Destination): 0.755ns (routing 0.108ns, distribution 0.647ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.618     3.968    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y301       FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     4.008 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[11]/Q
                         net (fo=2, routed)           0.063     4.071    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[11]
    SLICE_X100Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.755     2.040    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X100Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[11]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_ld_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.038ns (31.751%)  route 0.082ns (68.249%))
  Logic Levels:           0  
  Clock Path Skew:        -1.932ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.022ns
    Source Clock Delay      (SCD):    3.954ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.604ns (routing 0.916ns, distribution 0.688ns)
  Clock Net Delay (Destination): 0.737ns (routing 0.108ns, distribution 0.629ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.604     3.954    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X104Y297       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y297       FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     3.992 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_en_temp_reg/Q
                         net (fo=5, routed)           0.082     4.073    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_en_temp
    SLICE_X105Y297       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_ld_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.737     2.022    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/clk
    SLICE_X105Y297       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_ld_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[16]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.103ns  (logic 0.040ns (38.955%)  route 0.063ns (61.045%))
  Logic Levels:           0  
  Clock Path Skew:        -1.935ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.036ns
    Source Clock Delay      (SCD):    3.971ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.621ns (routing 0.916ns, distribution 0.705ns)
  Clock Net Delay (Destination): 0.751ns (routing 0.108ns, distribution 0.643ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.621     3.971    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X101Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y301       FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     4.011 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[16]/Q
                         net (fo=2, routed)           0.063     4.074    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[16]
    SLICE_X100Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[16]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.751     2.036    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X100Y301       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[16]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.041ns (32.283%)  route 0.086ns (67.716%))
  Logic Levels:           0  
  Clock Path Skew:        -1.928ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.019ns
    Source Clock Delay      (SCD):    3.947ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.597ns (routing 0.916ns, distribution 0.681ns)
  Clock Net Delay (Destination): 0.734ns (routing 0.108ns, distribution 0.626ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.597     3.947    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
    SLICE_X101Y292       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y292       FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     3.988 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.086     4.074    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[1]
    SLICE_X102Y292       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.734     2.019    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X102Y292       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.038ns (31.405%)  route 0.083ns (68.595%))
  Logic Levels:           0  
  Clock Path Skew:        -1.937ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.017ns
    Source Clock Delay      (SCD):    3.954ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.604ns (routing 0.916ns, distribution 0.688ns)
  Clock Net Delay (Destination): 0.732ns (routing 0.108ns, distribution 0.624ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.604     3.954    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
    SLICE_X104Y295       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y295       FDCE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     3.992 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.083     4.075    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[2]
    SLICE_X104Y295       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.732     2.017    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/wr_clk
    SLICE_X104Y295       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.111ns  (logic 0.040ns (36.139%)  route 0.071ns (63.861%))
  Logic Levels:           0  
  Clock Path Skew:        -1.924ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.041ns
    Source Clock Delay      (SCD):    3.965ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.615ns (routing 0.916ns, distribution 0.699ns)
  Clock Net Delay (Destination): 0.756ns (routing 0.108ns, distribution 0.648ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.615     3.965    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X102Y303       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y303       FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     4.005 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[12]/Q
                         net (fo=2, routed)           0.071     4.075    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[12]
    SLICE_X102Y302       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.756     2.041    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X102Y302       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[12]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.128ns  (logic 0.038ns (29.761%)  route 0.090ns (70.239%))
  Logic Levels:           0  
  Clock Path Skew:        -1.930ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.018ns
    Source Clock Delay      (SCD):    3.948ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.598ns (routing 0.916ns, distribution 0.682ns)
  Clock Net Delay (Destination): 0.733ns (routing 0.108ns, distribution 0.625ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.868     2.333    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.350 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.598     3.948    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/m_bscan_tck[0]
    SLICE_X104Y291       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y291       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     3.986 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/icn_cmd_en_temp_reg/Q
                         net (fo=3, routed)           0.090     4.076    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/icn_cmd_en_temp
    SLICE_X104Y291       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.733     2.018    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X104Y291       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_1_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout5

Max Delay             0 Endpoints
Min Delay            10 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.102ns  (logic 0.041ns (40.321%)  route 0.061ns (59.679%))
  Logic Levels:           0  
  Clock Path Skew:        -0.672ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.997ns
    Source Clock Delay      (SCD):    2.669ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.114ns (routing 0.435ns, distribution 0.679ns)
  Clock Net Delay (Destination): 0.712ns (routing 0.108ns, distribution 0.604ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.114     2.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X95Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y314        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     2.710 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/Q
                         net (fo=2, routed)           0.061     2.771    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/D[0]
    SLICE_X94Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.712     1.997    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/CLK
    SLICE_X94Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.123ns  (logic 0.038ns (30.894%)  route 0.085ns (69.106%))
  Logic Levels:           0  
  Clock Path Skew:        -0.671ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.002ns
    Source Clock Delay      (SCD):    2.673ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.118ns (routing 0.435ns, distribution 0.683ns)
  Clock Net Delay (Destination): 0.717ns (routing 0.108ns, distribution 0.609ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.118     2.673    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X94Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y311        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     2.711 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/Q
                         net (fo=1, routed)           0.085     2.796    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[4]
    SLICE_X94Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.717     2.002    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X94Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.126ns  (logic 0.039ns (30.952%)  route 0.087ns (69.048%))
  Logic Levels:           0  
  Clock Path Skew:        -0.681ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.993ns
    Source Clock Delay      (SCD):    2.674ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.119ns (routing 0.435ns, distribution 0.684ns)
  Clock Net Delay (Destination): 0.708ns (routing 0.108ns, distribution 0.600ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.119     2.674    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X96Y301        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y301        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     2.713 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/Q
                         net (fo=1, routed)           0.087     2.800    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[3]
    SLICE_X95Y303        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.708     1.993    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X95Y303        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.128ns  (logic 0.039ns (30.469%)  route 0.089ns (69.531%))
  Logic Levels:           0  
  Clock Path Skew:        -0.676ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.998ns
    Source Clock Delay      (SCD):    2.674ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.119ns (routing 0.435ns, distribution 0.684ns)
  Clock Net Delay (Destination): 0.713ns (routing 0.108ns, distribution 0.605ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.119     2.674    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X96Y301        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y301        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     2.713 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/Q
                         net (fo=1, routed)           0.089     2.802    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[7]
    SLICE_X96Y301        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.713     1.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X96Y301        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.039ns (32.500%)  route 0.081ns (67.500%))
  Logic Levels:           0  
  Clock Path Skew:        -0.688ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.996ns
    Source Clock Delay      (SCD):    2.684ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.129ns (routing 0.435ns, distribution 0.694ns)
  Clock Net Delay (Destination): 0.711ns (routing 0.108ns, distribution 0.603ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.129     2.684    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X94Y306        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y306        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     2.723 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/Q
                         net (fo=1, routed)           0.081     2.804    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[2]
    SLICE_X95Y308        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.711     1.996    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X95Y308        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.139ns  (logic 0.038ns (27.338%)  route 0.101ns (72.662%))
  Logic Levels:           0  
  Clock Path Skew:        -0.678ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.995ns
    Source Clock Delay      (SCD):    2.673ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.118ns (routing 0.435ns, distribution 0.683ns)
  Clock Net Delay (Destination): 0.710ns (routing 0.108ns, distribution 0.602ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.118     2.673    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X94Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y311        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     2.711 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/Q
                         net (fo=1, routed)           0.101     2.812    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[1]
    SLICE_X95Y310        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.710     1.995    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X95Y310        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.139ns  (logic 0.039ns (28.058%)  route 0.100ns (71.942%))
  Logic Levels:           0  
  Clock Path Skew:        -0.676ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.998ns
    Source Clock Delay      (SCD):    2.674ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.119ns (routing 0.435ns, distribution 0.684ns)
  Clock Net Delay (Destination): 0.713ns (routing 0.108ns, distribution 0.605ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.119     2.674    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X96Y302        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y302        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     2.713 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/Q
                         net (fo=1, routed)           0.100     2.813    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[8]
    SLICE_X96Y302        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.713     1.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X96Y302        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.159ns  (logic 0.039ns (24.528%)  route 0.120ns (75.472%))
  Logic Levels:           0  
  Clock Path Skew:        -0.673ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.000ns
    Source Clock Delay      (SCD):    2.673ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.118ns (routing 0.435ns, distribution 0.683ns)
  Clock Net Delay (Destination): 0.715ns (routing 0.108ns, distribution 0.607ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.118     2.673    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X94Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y311        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.712 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/Q
                         net (fo=1, routed)           0.120     2.832    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[0]
    SLICE_X96Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.715     2.000    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X96Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.189ns  (logic 0.039ns (20.635%)  route 0.150ns (79.365%))
  Logic Levels:           0  
  Clock Path Skew:        -0.684ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.999ns
    Source Clock Delay      (SCD):    2.684ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.129ns (routing 0.435ns, distribution 0.694ns)
  Clock Net Delay (Destination): 0.714ns (routing 0.108ns, distribution 0.606ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.129     2.684    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X94Y306        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y306        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     2.723 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/Q
                         net (fo=1, routed)           0.150     2.873    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[5]
    SLICE_X95Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.714     1.999    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X95Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.219ns  (logic 0.040ns (18.265%)  route 0.179ns (81.735%))
  Logic Levels:           0  
  Clock Path Skew:        -0.683ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.001ns
    Source Clock Delay      (SCD):    2.684ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.129ns (routing 0.435ns, distribution 0.694ns)
  Clock Net Delay (Destination): 0.716ns (routing 0.108ns, distribution 0.608ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.129     2.684    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X94Y306        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y306        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.040     2.724 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/Q
                         net (fo=1, routed)           0.179     2.903    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[6]
    SLICE_X96Y308        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y4 (CLOCK_ROOT)    net (fo=568, routed)         0.716     2.001    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X96Y308        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout6

Max Delay             0 Endpoints
Min Delay            35 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/en_vtc_in_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_en_vtc_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.040ns (40.816%)  route 0.058ns (59.184%))
  Logic Levels:           0  
  Clock Path Skew:        -0.096ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.591ns
    Source Clock Delay      (SCD):    2.687ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.132ns (routing 0.435ns, distribution 0.697ns)
  Clock Net Delay (Destination): 1.288ns (routing 0.492ns, distribution 0.796ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.132     2.687    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/SYNC[19].sync_reg_reg[1]
    SLICE_X81Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/en_vtc_in_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y323        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.727 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/en_vtc_in_reg/Q
                         net (fo=1, routed)           0.058     2.785    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_en_vtc_sync/D[0]
    SLICE_X81Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_en_vtc_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.288     2.591    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_en_vtc_sync/CLK
    SLICE_X81Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_en_vtc_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.126ns  (logic 0.039ns (30.952%)  route 0.087ns (69.048%))
  Logic Levels:           0  
  Clock Path Skew:        -0.095ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.575ns
    Source Clock Delay      (SCD):    2.670ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.115ns (routing 0.435ns, distribution 0.680ns)
  Clock Net Delay (Destination): 1.272ns (routing 0.492ns, distribution 0.780ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.115     2.670    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X89Y325        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y325        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.709 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[31]/Q
                         net (fo=1, routed)           0.087     2.796    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[31]
    SLICE_X89Y326        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.272     2.575    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X89Y326        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[23].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.130ns  (logic 0.038ns (29.231%)  route 0.092ns (70.769%))
  Logic Levels:           0  
  Clock Path Skew:        -0.094ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.573ns
    Source Clock Delay      (SCD):    2.667ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.112ns (routing 0.435ns, distribution 0.677ns)
  Clock Net Delay (Destination): 1.270ns (routing 0.492ns, distribution 0.778ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.112     2.667    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X89Y335        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y335        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.705 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[23]/Q
                         net (fo=1, routed)           0.092     2.797    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[23]
    SLICE_X89Y335        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[23].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.270     2.573    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X89Y335        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[23].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[20].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.040ns (33.333%)  route 0.080ns (66.667%))
  Logic Levels:           0  
  Clock Path Skew:        -0.102ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.578ns
    Source Clock Delay      (SCD):    2.680ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.125ns (routing 0.435ns, distribution 0.690ns)
  Clock Net Delay (Destination): 1.275ns (routing 0.492ns, distribution 0.783ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.125     2.680    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X88Y317        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y317        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     2.720 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[20]/Q
                         net (fo=1, routed)           0.080     2.800    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[20]
    SLICE_X88Y317        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[20].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.275     2.578    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X88Y317        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[20].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.123ns  (logic 0.039ns (31.707%)  route 0.084ns (68.293%))
  Logic Levels:           0  
  Clock Path Skew:        -0.092ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.585ns
    Source Clock Delay      (SCD):    2.677ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.122ns (routing 0.435ns, distribution 0.687ns)
  Clock Net Delay (Destination): 1.282ns (routing 0.492ns, distribution 0.790ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.122     2.677    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X86Y319        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y319        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     2.716 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[7]/Q
                         net (fo=1, routed)           0.084     2.800    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[7]
    SLICE_X86Y319        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.282     2.585    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X86Y319        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[7].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.040ns (32.000%)  route 0.085ns (68.000%))
  Logic Levels:           0  
  Clock Path Skew:        -0.099ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.577ns
    Source Clock Delay      (SCD):    2.676ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.121ns (routing 0.435ns, distribution 0.686ns)
  Clock Net Delay (Destination): 1.274ns (routing 0.492ns, distribution 0.782ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.121     2.676    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X85Y325        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y325        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     2.716 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[5]/Q
                         net (fo=1, routed)           0.085     2.801    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[5]
    SLICE_X85Y325        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.274     2.577    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X85Y325        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[5].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[27]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[27].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.133ns  (logic 0.041ns (30.827%)  route 0.092ns (69.173%))
  Logic Levels:           0  
  Clock Path Skew:        -0.088ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.581ns
    Source Clock Delay      (SCD):    2.669ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.114ns (routing 0.435ns, distribution 0.679ns)
  Clock Net Delay (Destination): 1.278ns (routing 0.492ns, distribution 0.786ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.114     2.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X89Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[27]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y337        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     2.710 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[27]/Q
                         net (fo=1, routed)           0.092     2.802    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[27]
    SLICE_X89Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[27].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.278     2.581    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X89Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[27].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.131ns  (logic 0.039ns (29.771%)  route 0.092ns (70.229%))
  Logic Levels:           0  
  Clock Path Skew:        -0.093ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.581ns
    Source Clock Delay      (SCD):    2.674ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.119ns (routing 0.435ns, distribution 0.684ns)
  Clock Net Delay (Destination): 1.278ns (routing 0.492ns, distribution 0.786ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.119     2.674    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X86Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y324        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     2.713 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[3]/Q
                         net (fo=1, routed)           0.092     2.805    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[3]
    SLICE_X86Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.278     2.581    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X86Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[3].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[10].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.132ns  (logic 0.041ns (31.061%)  route 0.091ns (68.939%))
  Logic Levels:           0  
  Clock Path Skew:        -0.102ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.572ns
    Source Clock Delay      (SCD):    2.674ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.119ns (routing 0.435ns, distribution 0.684ns)
  Clock Net Delay (Destination): 1.269ns (routing 0.492ns, distribution 0.777ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.119     2.674    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X86Y331        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y331        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     2.715 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[10]/Q
                         net (fo=1, routed)           0.091     2.806    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[10]
    SLICE_X87Y331        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[10].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.269     2.572    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X87Y331        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[10].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[29]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[29].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.139ns  (logic 0.040ns (28.777%)  route 0.099ns (71.223%))
  Logic Levels:           0  
  Clock Path Skew:        -0.086ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.581ns
    Source Clock Delay      (SCD):    2.667ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.112ns (routing 0.435ns, distribution 0.677ns)
  Clock Net Delay (Destination): 1.278ns (routing 0.492ns, distribution 0.786ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.112     2.667    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X89Y335        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[29]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y335        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.040     2.707 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[29]/Q
                         net (fo=1, routed)           0.099     2.806    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[29]
    SLICE_X89Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[29].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.278     2.581    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X89Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[29].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout6

Max Delay             2 Endpoints
Min Delay           486 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.821ns  (logic 0.079ns (9.627%)  route 0.742ns (90.373%))
  Logic Levels:           0  
  Clock Path Skew:        0.156ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.486ns
    Source Clock Delay      (SCD):    4.330ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.103ns (routing 0.799ns, distribution 1.304ns)
  Clock Net Delay (Destination): 1.827ns (routing 0.726ns, distribution 1.101ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.103     4.330    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X84Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y358        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/Q
                         net (fo=5, routed)           0.742     5.150    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/ext_reset_in
    SLICE_X88Y344        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     2.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.827     4.486    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/slowest_sync_clk
    SLICE_X88Y344        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.464ns  (logic 0.079ns (17.026%)  route 0.385ns (82.974%))
  Logic Levels:           0  
  Clock Path Skew:        0.193ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.504ns
    Source Clock Delay      (SCD):    4.311ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.084ns (routing 0.799ns, distribution 1.285ns)
  Clock Net Delay (Destination): 1.845ns (routing 0.726ns, distribution 1.119ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.227 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.084     4.311    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/slowest_sync_clk
    SLICE_X87Y352        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y352        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     4.390 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/Q
                         net (fo=1, routed)           0.385     4.775    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Reset
    SLICE_X87Y352        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     2.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.845     4.504    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Clk
    SLICE_X87Y352        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.203ns  (logic 0.039ns (19.212%)  route 0.164ns (80.788%))
  Logic Levels:           0  
  Clock Path Skew:        -0.110ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.595ns
    Source Clock Delay      (SCD):    2.706ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.141ns (routing 0.439ns, distribution 0.702ns)
  Clock Net Delay (Destination): 1.293ns (routing 0.492ns, distribution 0.801ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.141     2.706    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/slowest_sync_clk
    SLICE_X87Y352        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y352        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.745 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/Q
                         net (fo=1, routed)           0.164     2.909    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Reset
    SLICE_X87Y352        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.293     2.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Clk
    SLICE_X87Y352        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.303ns  (logic 0.039ns (12.885%)  route 0.264ns (87.115%))
  Logic Levels:           0  
  Clock Path Skew:        -0.047ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.658ns
    Source Clock Delay      (SCD):    2.705ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.140ns (routing 0.439ns, distribution 0.701ns)
  Clock Net Delay (Destination): 1.355ns (routing 0.492ns, distribution 0.863ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.140     2.705    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X84Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y351        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.744 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/Q
                         net (fo=22, routed)          0.264     3.008    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_1[12]
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.355     2.658    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.303ns  (logic 0.039ns (12.885%)  route 0.264ns (87.115%))
  Logic Levels:           0  
  Clock Path Skew:        -0.043ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.662ns
    Source Clock Delay      (SCD):    2.705ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.140ns (routing 0.439ns, distribution 0.701ns)
  Clock Net Delay (Destination): 1.359ns (routing 0.492ns, distribution 0.867ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.140     2.705    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X84Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y351        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.744 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/Q
                         net (fo=22, routed)          0.264     3.008    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_3[12]
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.359     2.662    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.358ns  (logic 0.039ns (10.907%)  route 0.319ns (89.093%))
  Logic Levels:           0  
  Clock Path Skew:        -0.049ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.658ns
    Source Clock Delay      (SCD):    2.707ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.142ns (routing 0.439ns, distribution 0.703ns)
  Clock Net Delay (Destination): 1.355ns (routing 0.492ns, distribution 0.863ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.142     2.707    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y349        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y349        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     2.746 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[0]/Q
                         net (fo=22, routed)          0.319     3.065    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_1[0]
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[0]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.355     2.658    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.359ns  (logic 0.039ns (10.876%)  route 0.320ns (89.124%))
  Logic Levels:           0  
  Clock Path Skew:        -0.045ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.662ns
    Source Clock Delay      (SCD):    2.707ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.142ns (routing 0.439ns, distribution 0.703ns)
  Clock Net Delay (Destination): 1.359ns (routing 0.492ns, distribution 0.867ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.142     2.707    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y349        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y349        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     2.746 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[0]/Q
                         net (fo=22, routed)          0.320     3.066    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_3[0]
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[0]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.359     2.662    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_ADDR[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.385ns  (logic 0.038ns (9.863%)  route 0.347ns (90.137%))
  Logic Levels:           0  
  Clock Path Skew:        -0.044ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.658ns
    Source Clock Delay      (SCD):    2.702ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.137ns (routing 0.439ns, distribution 0.698ns)
  Clock Net Delay (Destination): 1.355ns (routing 0.492ns, distribution 0.863ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.137     2.702    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X83Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y343        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     2.740 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[0]/Q
                         net (fo=22, routed)          0.347     3.087    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_10[0]
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_ADDR[0]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.355     2.658    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_ADDR[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.385ns  (logic 0.038ns (9.863%)  route 0.347ns (90.137%))
  Logic Levels:           0  
  Clock Path Skew:        -0.040ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.662ns
    Source Clock Delay      (SCD):    2.702ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.137ns (routing 0.439ns, distribution 0.698ns)
  Clock Net Delay (Destination): 1.359ns (routing 0.492ns, distribution 0.867ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.137     2.702    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X83Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y343        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     2.740 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[0]/Q
                         net (fo=22, routed)          0.347     3.087    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_10[0]
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_ADDR[0]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.359     2.662    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.388ns  (logic 0.039ns (10.059%)  route 0.349ns (89.941%))
  Logic Levels:           0  
  Clock Path Skew:        -0.055ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.650ns
    Source Clock Delay      (SCD):    2.705ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.140ns (routing 0.439ns, distribution 0.701ns)
  Clock Net Delay (Destination): 1.347ns (routing 0.492ns, distribution 0.855ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.140     2.705    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X84Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y351        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.744 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/Q
                         net (fo=22, routed)          0.349     3.093    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_1[12]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.347     2.650    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.388ns  (logic 0.039ns (10.059%)  route 0.349ns (89.941%))
  Logic Levels:           0  
  Clock Path Skew:        -0.043ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.662ns
    Source Clock Delay      (SCD):    2.705ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.140ns (routing 0.439ns, distribution 0.701ns)
  Clock Net Delay (Destination): 1.359ns (routing 0.492ns, distribution 0.867ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.140     2.705    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X84Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y351        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.744 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/Q
                         net (fo=22, routed)          0.349     3.093    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_3[12]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.359     2.662    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.386ns  (logic 0.040ns (10.371%)  route 0.346ns (89.629%))
  Logic Levels:           0  
  Clock Path Skew:        -0.049ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.658ns
    Source Clock Delay      (SCD):    2.707ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.142ns (routing 0.439ns, distribution 0.703ns)
  Clock Net Delay (Destination): 1.355ns (routing 0.492ns, distribution 0.863ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.142     2.707    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y349        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y349        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.040     2.747 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[1]/Q
                         net (fo=22, routed)          0.346     3.093    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_1[1]
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[1]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.355     2.658    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  sys_clk_ddr4_clk_p
  To Clock:  mmcm_clkout6

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.068ns  (logic 0.081ns (7.584%)  route 0.987ns (92.416%))
  Logic Levels:           0  
  Clock Path Skew:        2.280ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.502ns
    Source Clock Delay      (SCD):    2.222ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.136ns (routing 0.171ns, distribution 0.965ns)
  Clock Net Delay (Destination): 1.843ns (routing 0.726ns, distribution 1.117ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.136     2.222    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y345        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y345        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/Q
                         net (fo=1, routed)           0.987     3.290    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb
    SLICE_X81Y346        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     2.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.843     4.502    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X81Y346        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.360ns  (logic 0.081ns (22.498%)  route 0.279ns (77.502%))
  Logic Levels:           0  
  Clock Path Skew:        2.274ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.495ns
    Source Clock Delay      (SCD):    2.221ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.135ns (routing 0.171ns, distribution 0.964ns)
  Clock Net Delay (Destination): 1.836ns (routing 0.726ns, distribution 1.110ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.135     2.221    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y343        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.302 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.279     2.581    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X85Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.863     1.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     2.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.836     4.495    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X85Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.165ns  (logic 0.040ns (24.289%)  route 0.125ns (75.711%))
  Logic Levels:           0  
  Clock Path Skew:        1.325ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.588ns
    Source Clock Delay      (SCD):    1.263ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.646ns (routing 0.096ns, distribution 0.550ns)
  Clock Net Delay (Destination): 1.285ns (routing 0.492ns, distribution 0.793ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.646     1.263    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y343        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.125     1.428    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X85Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.285     2.588    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X85Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.509ns  (logic 0.040ns (7.859%)  route 0.469ns (92.141%))
  Logic Levels:           0  
  Clock Path Skew:        1.325ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.589ns
    Source Clock Delay      (SCD):    1.264ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.647ns (routing 0.096ns, distribution 0.551ns)
  Clock Net Delay (Destination): 1.286ns (routing 0.492ns, distribution 0.794ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.647     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y345        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y345        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.304 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/Q
                         net (fo=1, routed)           0.469     1.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb
    SLICE_X81Y346        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.615     1.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.107 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.303 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.286     2.589    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X81Y346        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  sys_clk_ddr4_clk_p

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
                            (recovery check against rising-edge clock sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.789ns  (logic 0.079ns (10.013%)  route 0.710ns (89.987%))
  Logic Levels:           0  
  Clock Path Skew:        -0.542ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.899ns
    Source Clock Delay      (SCD):    2.441ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.215ns (routing 0.662ns, distribution 1.553ns)
  Clock Net Delay (Destination): 0.984ns (routing 0.155ns, distribution 0.829ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.215     2.441    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X77Y334        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y334        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.520 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.710     3.230    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X81Y336        FDPE                                         f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.984     1.899    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y336        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
                            (recovery check against rising-edge clock sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.789ns  (logic 0.079ns (10.013%)  route 0.710ns (89.987%))
  Logic Levels:           0  
  Clock Path Skew:        -0.542ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.899ns
    Source Clock Delay      (SCD):    2.441ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.215ns (routing 0.662ns, distribution 1.553ns)
  Clock Net Delay (Destination): 0.984ns (routing 0.155ns, distribution 0.829ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.215     2.441    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X77Y334        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y334        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.520 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.710     3.230    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X81Y336        FDPE                                         f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.984     1.899    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y336        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
                            (removal check against rising-edge clock sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.388ns  (logic 0.039ns (10.052%)  route 0.349ns (89.948%))
  Logic Levels:           0  
  Clock Path Skew:        0.187ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.521ns
    Source Clock Delay      (SCD):    1.334ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.214ns (routing 0.359ns, distribution 0.855ns)
  Clock Net Delay (Destination): 0.734ns (routing 0.108ns, distribution 0.626ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.214     1.334    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X77Y334        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y334        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.373 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.349     1.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X81Y336        FDPE                                         f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.734     1.521    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y336        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
                            (removal check against rising-edge clock sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.388ns  (logic 0.039ns (10.052%)  route 0.349ns (89.948%))
  Logic Levels:           0  
  Clock Path Skew:        0.187ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.521ns
    Source Clock Delay      (SCD):    1.334ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.214ns (routing 0.359ns, distribution 0.855ns)
  Clock Net Delay (Destination): 0.734ns (routing 0.108ns, distribution 0.626ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.214     1.334    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X77Y334        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y334        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.373 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.349     1.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X81Y336        FDPE                                         f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.734     1.521    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y336        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  

Max Delay             6 Endpoints
Min Delay             6 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.734ns  (logic 0.028ns (1.024%)  route 2.706ns (98.976%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.508     7.734    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y1           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.728ns  (logic 0.028ns (1.026%)  route 2.700ns (98.974%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.502     7.728    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSDAC_X0Y1           HSDAC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.722ns  (logic 0.028ns (1.029%)  route 2.694ns (98.971%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.496     7.722    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y0           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.707ns  (logic 0.028ns (1.034%)  route 2.679ns (98.966%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.481     7.707    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSDAC_X0Y0           HSDAC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.700ns  (logic 0.028ns (1.037%)  route 2.672ns (98.963%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.474     7.700    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y2           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.679ns  (logic 0.028ns (1.045%)  route 2.651ns (98.955%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       2.453     7.679    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y3           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.443ns  (logic 0.017ns (1.178%)  route 1.426ns (98.822%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.323     1.443    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y3           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.452ns  (logic 0.017ns (1.171%)  route 1.435ns (98.829%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.332     1.452    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y2           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.462ns  (logic 0.017ns (1.163%)  route 1.445ns (98.837%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.342     1.462    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSDAC_X0Y0           HSDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.468ns  (logic 0.017ns (1.158%)  route 1.451ns (98.842%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.348     1.468    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y1           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.475ns  (logic 0.017ns (1.153%)  route 1.458ns (98.847%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.355     1.475    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSDAC_X0Y1           HSDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.478ns  (logic 0.017ns (1.150%)  route 1.461ns (98.850%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.358     1.478    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y0           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            ddr4_pl_reset_n
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.377ns  (logic 0.927ns (38.987%)  route 1.450ns (61.013%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.156ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.062ns (routing 0.788ns, distribution 1.274ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.978     2.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       2.062     4.272    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X82Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y311        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     4.352 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/Q
                         net (fo=1, routed)           1.450     5.802    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/cal_RESET_n[0]
    A17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.847     6.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/OBUF_reset_n/O
                         net (fo=0)                   0.000     6.648    ddr4_pl_reset_n
    A17                                                               r  ddr4_pl_reset_n (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            ddr4_pl_reset_n
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.132ns  (logic 0.461ns (40.732%)  route 0.671ns (59.268%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.156ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.138ns (routing 0.435ns, distribution 0.703ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.545     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41406, routed)       1.138     2.693    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X82Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y311        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     2.734 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/Q
                         net (fo=1, routed)           0.671     3.405    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/cal_RESET_n[0]
    A17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.420     3.825 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/OBUF_reset_n/O
                         net (fo=0)                   0.000     3.825    ddr4_pl_reset_n
    A17                                                               r  ddr4_pl_reset_n (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.783ns  (logic 0.152ns (19.413%)  route 0.631ns (80.587%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 2.050ns (routing 0.798ns, distribution 1.252ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y1            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           0.573     0.573    d_1_i/rst_adc0_x2/U0/EXT_LPF/dcm_locked
    SLICE_X76Y114        LUT4 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152     0.725 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.058     0.783    d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0__0
    SLICE_X76Y114        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.695     2.081    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.711 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.926    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.950 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       2.050     5.000    d_1_i/rst_adc0_x2/U0/EXT_LPF/slowest_sync_clk
    SLICE_X76Y114        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.351ns  (logic 0.061ns (17.379%)  route 0.290ns (82.621%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 1.428ns (routing 0.537ns, distribution 0.891ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y1            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           0.269     0.269    d_1_i/rst_adc0_x2/U0/EXT_LPF/dcm_locked
    SLICE_X76Y114        LUT4 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.061     0.330 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.021     0.351    d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0__0
    SLICE_X76Y114        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.147     1.499    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.204 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.370    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.389 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86138, routed)       1.428     2.817    d_1_i/rst_adc0_x2/U0/EXT_LPF/slowest_sync_clk
    SLICE_X76Y114        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay             3 Endpoints
Min Delay             3 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 PMOD1_0_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/proc_start_cdc_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.855ns  (logic 0.643ns (22.514%)  route 2.212ns (77.486%))
  Logic Levels:           2  (IBUFCTRL=1 INBUF=1)
  Clock Path Skew:        5.072ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.072ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 2.090ns (routing 0.940ns, distribution 1.150ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L14                                               0.000     0.000 r  PMOD1_0_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_0_LS_IBUF_inst/I
    L14                  INBUF (Prop_INBUF_HPIOB_S_PAD_O)
                                                      0.643     0.643 r  PMOD1_0_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.643    PMOD1_0_LS_IBUF_inst/OUT
    L14                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_S_I_O)
                                                      0.000     0.643 r  PMOD1_0_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           2.212     2.855    d_1_i/qick_processor_0/inst/proc_start_i
    SLICE_X47Y233        FDRE                                         r  d_1_i/qick_processor_0/inst/proc_start_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.090     5.072    d_1_i/qick_processor_0/inst/c_clk_i
    SLICE_X47Y233        FDRE                                         r  d_1_i/qick_processor_0/inst/proc_start_cdc_reg/C

Slack:                    inf
  Source:                 PMOD1_1_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/proc_stop_cdc_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.829ns  (logic 0.642ns (22.705%)  route 2.187ns (77.295%))
  Logic Levels:           2  (IBUFCTRL=1 INBUF=1)
  Clock Path Skew:        5.072ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.072ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 2.090ns (routing 0.940ns, distribution 1.150ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L15                                               0.000     0.000 r  PMOD1_1_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_1_LS_IBUF_inst/I
    L15                  INBUF (Prop_INBUF_HPIOB_M_PAD_O)
                                                      0.642     0.642 r  PMOD1_1_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.642    PMOD1_1_LS_IBUF_inst/OUT
    L15                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.642 r  PMOD1_1_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           2.187     2.829    d_1_i/qick_processor_0/inst/proc_stop_i
    SLICE_X47Y233        FDRE                                         r  d_1_i/qick_processor_0/inst/proc_stop_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.090     5.072    d_1_i/qick_processor_0/inst/c_clk_i
    SLICE_X47Y233        FDRE                                         r  d_1_i/qick_processor_0/inst/proc_stop_cdc_reg/C

Slack:                    inf
  Source:                 d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.083ns  (logic 0.036ns (3.324%)  route 1.047ns (96.676%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 2.025ns (routing 0.940ns, distribution 1.085ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y5            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           0.998     0.998    d_1_i/rst_core/U0/EXT_LPF/dcm_locked
    SLICE_X73Y324        LUT4 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.036     1.034 r  d_1_i/rst_core/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.049     1.083    d_1_i/rst_core/U0/EXT_LPF/lpf_int0__0
    SLICE_X73Y324        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        2.025     5.007    d_1_i/rst_core/U0/EXT_LPF/slowest_sync_clk
    SLICE_X73Y324        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.530ns  (logic 0.015ns (2.830%)  route 0.515ns (97.170%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 1.410ns (routing 0.639ns, distribution 0.771ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y5            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           0.500     0.500    d_1_i/rst_core/U0/EXT_LPF/dcm_locked
    SLICE_X73Y324        LUT4 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.015     0.515 r  d_1_i/rst_core/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.015     0.530    d_1_i/rst_core/U0/EXT_LPF/lpf_int0__0
    SLICE_X73Y324        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.410     2.758    d_1_i/rst_core/U0/EXT_LPF/slowest_sync_clk
    SLICE_X73Y324        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/C

Slack:                    inf
  Source:                 PMOD1_1_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/proc_stop_cdc_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.199ns  (logic 0.194ns (16.189%)  route 1.005ns (83.811%))
  Logic Levels:           2  (IBUFCTRL=1 INBUF=1)
  Clock Path Skew:        2.798ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.798ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Destination): 1.450ns (routing 0.639ns, distribution 0.811ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L15                                               0.000     0.000 r  PMOD1_1_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_1_LS_IBUF_inst/I
    L15                  INBUF (Prop_INBUF_HPIOB_M_PAD_O)
                                                      0.194     0.194 r  PMOD1_1_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.194    PMOD1_1_LS_IBUF_inst/OUT
    L15                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.194 r  PMOD1_1_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           1.005     1.199    d_1_i/qick_processor_0/inst/proc_stop_i
    SLICE_X47Y233        FDRE                                         r  d_1_i/qick_processor_0/inst/proc_stop_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.450     2.798    d_1_i/qick_processor_0/inst/c_clk_i
    SLICE_X47Y233        FDRE                                         r  d_1_i/qick_processor_0/inst/proc_stop_cdc_reg/C

Slack:                    inf
  Source:                 PMOD1_0_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/proc_start_cdc_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.211ns  (logic 0.194ns (16.048%)  route 1.017ns (83.952%))
  Logic Levels:           2  (IBUFCTRL=1 INBUF=1)
  Clock Path Skew:        2.798ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.798ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Destination): 1.450ns (routing 0.639ns, distribution 0.811ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L14                                               0.000     0.000 r  PMOD1_0_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_0_LS_IBUF_inst/I
    L14                  INBUF (Prop_INBUF_HPIOB_S_PAD_O)
                                                      0.194     0.194 r  PMOD1_0_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.194    PMOD1_0_LS_IBUF_inst/OUT
    L14                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_S_I_O)
                                                      0.000     0.194 r  PMOD1_0_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           1.017     1.211    d_1_i/qick_processor_0/inst/proc_start_i
    SLICE_X47Y233        FDRE                                         r  d_1_i/qick_processor_0/inst/proc_start_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55462, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4524, routed)        1.450     2.798    d_1_i/qick_processor_0/inst/c_clk_i
    SLICE_X47Y233        FDRE                                         r  d_1_i/qick_processor_0/inst/proc_start_cdc_reg/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_pl_0

Max Delay             7 Endpoints
Min Delay             7 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.870ns  (logic 0.367ns (9.482%)  route 3.503ns (90.518%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[1]
                         net (fo=2, routed)           2.738     2.738    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[1]
    SLICE_X108Y136       LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.088     2.826 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_71/O
                         net (fo=1, routed)           0.151     2.977    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_71_n_0
    SLICE_X108Y134       LUT5 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.051     3.028 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_51/O
                         net (fo=1, routed)           0.268     3.296    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_51_n_0
    SLICE_X111Y134       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.089     3.385 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_21/O
                         net (fo=1, routed)           0.084     3.469    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_21_n_0
    SLICE_X111Y133       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.089     3.558 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_6/O
                         net (fo=1, routed)           0.213     3.771    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_6_n_0
    SLICE_X111Y124       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.050     3.821 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_1/O
                         net (fo=1, routed)           0.049     3.870    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_83
    SLICE_X111Y124       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y124       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[4]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.675ns  (logic 0.539ns (14.667%)  route 3.136ns (85.333%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.599ns, distribution 1.557ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[4]
                         net (fo=1, routed)           1.894     1.894    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[4]
    SLICE_X114Y135       LUT5 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.148     2.042 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_51/O
                         net (fo=1, routed)           0.549     2.591    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_51_n_0
    SLICE_X106Y135       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.146     2.737 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_30/O
                         net (fo=1, routed)           0.332     3.069    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_30_n_0
    SLICE_X108Y135       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.123     3.192 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_7/O
                         net (fo=1, routed)           0.312     3.504    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_7_n_0
    SLICE_X108Y126       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.122     3.626 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_1/O
                         net (fo=1, routed)           0.049     3.675    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_80
    SLICE_X108Y126       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y126       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[7]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.415ns  (logic 0.337ns (9.868%)  route 3.078ns (90.132%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.173ns (routing 0.599ns, distribution 1.574ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[7]
                         net (fo=1, routed)           2.171     2.171    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[7]
    SLICE_X106Y133       LUT5 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.124     2.295 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_24/O
                         net (fo=1, routed)           0.091     2.386    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_24_n_0
    SLICE_X106Y133       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.088     2.474 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_10/O
                         net (fo=1, routed)           0.499     2.973    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_10_n_0
    SLICE_X108Y135       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.036     3.009 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_3/O
                         net (fo=1, routed)           0.258     3.267    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_3_n_0
    SLICE_X110Y124       LUT6 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.089     3.356 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_1/O
                         net (fo=1, routed)           0.059     3.415    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_77
    SLICE_X110Y124       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.173     2.355    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y124       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[5]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.408ns  (logic 0.376ns (11.033%)  route 3.032ns (88.967%))
  Logic Levels:           5  (LUT6=5)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[5]
                         net (fo=1, routed)           2.121     2.121    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[5]
    SLICE_X107Y132       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.051     2.172 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_27/O
                         net (fo=1, routed)           0.147     2.319    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_27_n_0
    SLICE_X107Y132       LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.148     2.467 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_20/O
                         net (fo=1, routed)           0.043     2.510    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_20_n_0
    SLICE_X107Y132       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.090     2.600 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_10/O
                         net (fo=1, routed)           0.042     2.642    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_10_n_0
    SLICE_X107Y132       LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.037     2.679 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_2/O
                         net (fo=1, routed)           0.629     3.308    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_2_n_0
    SLICE_X111Y124       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.050     3.358 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.050     3.408    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X111Y124       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y124       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[0]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.367ns  (logic 0.540ns (16.038%)  route 2.827ns (83.962%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.155ns (routing 0.599ns, distribution 1.556ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[0]
                         net (fo=2, routed)           2.276     2.276    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[0]
    SLICE_X111Y133       LUT5 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.146     2.422 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_57/O
                         net (fo=1, routed)           0.043     2.465    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_57_n_0
    SLICE_X111Y133       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.099     2.564 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_27/O
                         net (fo=1, routed)           0.101     2.665    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_27_n_0
    SLICE_X111Y135       LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.123     2.788 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_8/O
                         net (fo=1, routed)           0.089     2.877    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_8_n_0
    SLICE_X111Y135       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.050     2.927 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_2/O
                         net (fo=1, routed)           0.269     3.196    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_2_n_0
    SLICE_X111Y126       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.122     3.318 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_1/O
                         net (fo=1, routed)           0.049     3.367    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_84
    SLICE_X111Y126       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.155     2.337    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y126       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.255ns  (logic 0.405ns (12.444%)  route 2.850ns (87.556%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.170ns (routing 0.599ns, distribution 1.571ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[2]
                         net (fo=2, routed)           2.097     2.097    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[2]
    SLICE_X111Y134       LUT4 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.148     2.245 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_58/O
                         net (fo=1, routed)           0.084     2.329    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_58_n_0
    SLICE_X111Y133       LUT5 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.050     2.379 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_26/O
                         net (fo=1, routed)           0.091     2.470    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_26_n_0
    SLICE_X111Y134       LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.035     2.505 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_8/O
                         net (fo=1, routed)           0.283     2.788    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_8_n_0
    SLICE_X110Y131       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.122     2.910 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_2/O
                         net (fo=1, routed)           0.245     3.155    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_2_n_0
    SLICE_X111Y123       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.050     3.205 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_1/O
                         net (fo=1, routed)           0.050     3.255    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_82
    SLICE_X111Y123       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.170     2.352    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y123       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.990ns  (logic 0.283ns (9.464%)  route 2.707ns (90.536%))
  Logic Levels:           5  (LUT4=1 LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.155ns (routing 0.599ns, distribution 1.556ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[3]
                         net (fo=2, routed)           1.655     1.655    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[3]
    SLICE_X107Y137       LUT4 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.052     1.707 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_73/O
                         net (fo=1, routed)           0.155     1.862    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_73_n_0
    SLICE_X106Y137       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.050     1.912 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_50/O
                         net (fo=1, routed)           0.488     2.400    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_50_n_0
    SLICE_X111Y136       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.050     2.450 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_20/O
                         net (fo=1, routed)           0.142     2.592    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_20_n_0
    SLICE_X111Y135       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     2.627 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_6/O
                         net (fo=1, routed)           0.217     2.844    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_6_n_0
    SLICE_X111Y126       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.096     2.940 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_1/O
                         net (fo=1, routed)           0.050     2.990    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_81
    SLICE_X111Y126       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       2.155     2.337    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y126       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[7]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.682ns  (logic 0.113ns (16.569%)  route 0.569ns (83.431%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.501ns (routing 0.405ns, distribution 1.096ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[7]
                         net (fo=1, routed)           0.278     0.278    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[7]
    SLICE_X115Y124       LUT5 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.022     0.300 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_36/O
                         net (fo=1, routed)           0.102     0.402    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_36_n_0
    SLICE_X114Y124       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.014     0.416 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_30/O
                         net (fo=1, routed)           0.021     0.437    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_30_n_0
    SLICE_X114Y124       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.014     0.451 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_17/O
                         net (fo=1, routed)           0.044     0.495    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_17_n_0
    SLICE_X114Y124       LUT6 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.041     0.536 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_6/O
                         net (fo=1, routed)           0.103     0.639    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_6_n_0
    SLICE_X110Y124       LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.022     0.661 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_1/O
                         net (fo=1, routed)           0.021     0.682    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_77
    SLICE_X110Y124       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.501     1.648    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y124       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.831ns  (logic 0.161ns (19.369%)  route 0.670ns (80.631%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.498ns (routing 0.405ns, distribution 1.093ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[2]
                         net (fo=2, routed)           0.288     0.288    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[2]
    SLICE_X116Y124       LUT6 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.014     0.302 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_67/O
                         net (fo=1, routed)           0.050     0.352    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_67_n_0
    SLICE_X116Y124       LUT5 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.060     0.412 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_41/O
                         net (fo=1, routed)           0.080     0.492    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_41_n_0
    SLICE_X116Y128       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.015     0.507 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_15/O
                         net (fo=1, routed)           0.045     0.552    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_15_n_0
    SLICE_X116Y129       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.022     0.574 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_3/O
                         net (fo=1, routed)           0.190     0.764    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_3_n_0
    SLICE_X111Y123       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.050     0.814 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_1/O
                         net (fo=1, routed)           0.017     0.831    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_82
    SLICE_X111Y123       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.498     1.645    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y123       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.835ns  (logic 0.193ns (23.111%)  route 0.642ns (76.889%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.493ns (routing 0.405ns, distribution 1.088ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[1]
                         net (fo=2, routed)           0.318     0.318    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[1]
    SLICE_X114Y125       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.014     0.332 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_27/O
                         net (fo=1, routed)           0.059     0.391    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_27_n_0
    SLICE_X116Y125       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.060     0.451 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_10/O
                         net (fo=1, routed)           0.093     0.544    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_10_n_0
    SLICE_X116Y120       LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.060     0.604 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_4/O
                         net (fo=1, routed)           0.156     0.760    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_4_n_0
    SLICE_X111Y124       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.059     0.819 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_1/O
                         net (fo=1, routed)           0.016     0.835    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_83
    SLICE_X111Y124       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.493     1.640    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y124       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[4]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.872ns  (logic 0.182ns (20.872%)  route 0.690ns (79.128%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.486ns (routing 0.405ns, distribution 1.081ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[4]
                         net (fo=1, routed)           0.336     0.336    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[4]
    SLICE_X114Y116       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.059     0.395 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_42/O
                         net (fo=1, routed)           0.056     0.451    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_42_n_0
    SLICE_X114Y117       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.060     0.511 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_24/O
                         net (fo=1, routed)           0.084     0.595    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_24_n_0
    SLICE_X114Y117       LUT4 (Prop_E6LUT_SLICEL_I3_O)
                                                      0.022     0.617 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_5/O
                         net (fo=1, routed)           0.198     0.815    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_5_n_0
    SLICE_X108Y126       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.041     0.856 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_1/O
                         net (fo=1, routed)           0.016     0.872    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_80
    SLICE_X108Y126       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.486     1.633    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y126       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[0]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.900ns  (logic 0.239ns (26.570%)  route 0.661ns (73.430%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.484ns (routing 0.405ns, distribution 1.079ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[0]
                         net (fo=2, routed)           0.230     0.230    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[0]
    SLICE_X116Y126       LUT5 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.035     0.265 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_68/O
                         net (fo=1, routed)           0.051     0.316    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_68_n_0
    SLICE_X115Y126       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.059     0.375 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_40/O
                         net (fo=1, routed)           0.048     0.423    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_40_n_0
    SLICE_X115Y126       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.051     0.474 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_14/O
                         net (fo=1, routed)           0.134     0.608    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_14_n_0
    SLICE_X116Y119       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.059     0.667 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_4/O
                         net (fo=1, routed)           0.182     0.849    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_4_n_0
    SLICE_X111Y126       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.035     0.884 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_1/O
                         net (fo=1, routed)           0.016     0.900    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_84
    SLICE_X111Y126       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.484     1.631    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y126       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.901ns  (logic 0.193ns (21.432%)  route 0.708ns (78.568%))
  Logic Levels:           5  (LUT6=5)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.484ns (routing 0.405ns, distribution 1.079ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[3]
                         net (fo=2, routed)           0.275     0.275    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[3]
    SLICE_X116Y127       LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.035     0.310 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_57/O
                         net (fo=1, routed)           0.075     0.385    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_57_n_0
    SLICE_X115Y127       LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.035     0.420 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_24/O
                         net (fo=1, routed)           0.025     0.445    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_24_n_0
    SLICE_X115Y127       LUT6 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.023     0.468 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_7/O
                         net (fo=1, routed)           0.111     0.579    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_7_n_0
    SLICE_X115Y120       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.041     0.620 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_2/O
                         net (fo=1, routed)           0.205     0.825    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_2_n_0
    SLICE_X111Y126       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.059     0.884 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_1/O
                         net (fo=1, routed)           0.017     0.901    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_81
    SLICE_X111Y126       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.484     1.631    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y126       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[5]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.572ns  (logic 0.117ns (7.443%)  route 1.455ns (92.557%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.493ns (routing 0.405ns, distribution 1.088ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[5]
                         net (fo=1, routed)           0.914     0.914    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[5]
    SLICE_X105Y137       LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.059     0.973 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_22/O
                         net (fo=1, routed)           0.077     1.050    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_22_n_0
    SLICE_X105Y133       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.014     1.064 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_11/O
                         net (fo=1, routed)           0.118     1.182    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_11_n_0
    SLICE_X107Y132       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.022     1.204 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_2/O
                         net (fo=1, routed)           0.329     1.533    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_2_n_0
    SLICE_X111Y124       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.022     1.555 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.017     1.572    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X111Y124       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55462, routed)       1.493     1.640    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y124       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Max Delay             4 Endpoints
Min Delay             4 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.581ns  (logic 4.300ns (77.054%)  route 1.281ns (22.946%))
  Logic Levels:           1  (BSCANE2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.557ns (routing 1.525ns, distribution 1.032ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           1.281     5.581    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/out
    SLICE_X106Y217       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.557     5.393    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/m_bscan_tck[0]
    SLICE_X106Y217       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.173ns  (logic 4.398ns (85.021%)  route 0.775ns (14.979%))
  Logic Levels:           2  (BSCANE2=1 LUT5=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.568ns (routing 1.525ns, distribution 1.043ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.727     5.027    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X108Y93        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.098     5.125 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2/O
                         net (fo=1, routed)           0.048     5.173    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2_n_0
    SLICE_X108Y93        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.568     5.404    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y93        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.128ns  (logic 4.351ns (84.850%)  route 0.777ns (15.150%))
  Logic Levels:           2  (BSCANE2=1 LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.571ns (routing 1.525ns, distribution 1.046ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.711     5.011    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X109Y94        LUT2 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.051     5.062 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2/O
                         net (fo=1, routed)           0.066     5.128    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2_n_0
    SLICE_X109Y94        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.571     5.407    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X109Y94        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.785ns  (logic 4.388ns (91.695%)  route 0.397ns (8.305%))
  Logic Levels:           2  (BSCANE2=1 LUT4=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.583ns (routing 1.525ns, distribution 1.058ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.347     4.647    dbg_hub/inst/BSCANID.u_xsdbm_id/TDI
    SLICE_X106Y97        LUT4 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.088     4.735 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid[31]_i_1/O
                         net (fo=1, routed)           0.050     4.785    dbg_hub/inst/BSCANID.u_xsdbm_id/p_2_in[31]
    SLICE_X106Y97        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.347     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.583     5.419    dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i
    SLICE_X106Y97        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.699ns  (logic 0.500ns (71.565%)  route 0.199ns (28.435%))
  Logic Levels:           2  (BSCANE2=1 LUT4=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.790ns (routing 1.028ns, distribution 0.762ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.182     0.647    dbg_hub/inst/BSCANID.u_xsdbm_id/TDI
    SLICE_X106Y97        LUT4 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     0.682 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid[31]_i_1/O
                         net (fo=1, routed)           0.017     0.699    dbg_hub/inst/BSCANID.u_xsdbm_id/p_2_in[31]
    SLICE_X106Y97        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.790     8.561    dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i
    SLICE_X106Y97        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.866ns  (logic 0.487ns (56.204%)  route 0.379ns (43.796%))
  Logic Levels:           2  (BSCANE2=1 LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.785ns (routing 1.028ns, distribution 0.757ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.355     0.820    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X109Y94        LUT2 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.022     0.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2/O
                         net (fo=1, routed)           0.024     0.866    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2_n_0
    SLICE_X109Y94        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.785     8.556    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X109Y94        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.880ns  (logic 0.506ns (57.468%)  route 0.374ns (42.532%))
  Logic Levels:           2  (BSCANE2=1 LUT5=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.782ns (routing 1.028ns, distribution 0.754ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.358     0.823    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X108Y93        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.041     0.864 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2/O
                         net (fo=1, routed)           0.016     0.880    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2_n_0
    SLICE_X108Y93        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.782     8.553    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y93        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.111ns  (logic 0.465ns (41.847%)  route 0.646ns (58.153%))
  Logic Levels:           1  (BSCANE2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.759ns (routing 1.028ns, distribution 0.731ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.646     1.111    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/out
    SLICE_X106Y217       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.452     6.752    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.771 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.759     8.530    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/m_bscan_tck[0]
    SLICE_X106Y217       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  sys_clk_ddr4_clk_p

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.009ns  (logic 0.298ns (14.833%)  route 1.711ns (85.167%))
  Logic Levels:           2  (LUT3=2)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 0.992ns (routing 0.155ns, distribution 0.837ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PLL_X0Y7             PLLE4_ADV                    0.000     0.000 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/LOCKED
                         net (fo=1, routed)           1.096     1.096    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/pll_lock_i[0]
    SLICE_X81Y311        LUT3 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.149     1.245 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/pll_lock__0/O
                         net (fo=1, routed)           0.409     1.654    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/pll_lock
    SLICE_X81Y342        LUT3 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.149     1.803 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_i_1/O
                         net (fo=1, routed)           0.206     2.009    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg0
    SLICE_X81Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.992     1.907    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.104ns  (logic 0.096ns (8.699%)  route 1.008ns (91.301%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 0.993ns (routing 0.155ns, distribution 0.838ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y4            MMCME4_ADV                   0.000     0.000 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                         net (fo=3, routed)           0.781     0.781    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_lock
    SLICE_X81Y342        LUT2 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.096     0.877 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_i_1/O
                         net (fo=1, routed)           0.227     1.104    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg0
    SLICE_X81Y345        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.993     1.908    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y345        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.495ns  (logic 0.035ns (7.077%)  route 0.460ns (92.923%))
  Logic Levels:           1  (LUT3=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 0.738ns (routing 0.108ns, distribution 0.630ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y4            MMCME4_ADV                   0.000     0.000 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                         net (fo=3, routed)           0.379     0.379    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_lock
    SLICE_X81Y342        LUT3 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.035     0.414 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_i_1/O
                         net (fo=1, routed)           0.081     0.495    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg0
    SLICE_X81Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.738     1.525    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y343        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.509ns  (logic 0.033ns (6.489%)  route 0.476ns (93.511%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 0.739ns (routing 0.108ns, distribution 0.631ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y4            MMCME4_ADV                   0.000     0.000 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                         net (fo=3, routed)           0.378     0.378    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_lock
    SLICE_X81Y342        LUT2 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.033     0.411 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_i_1/O
                         net (fo=1, routed)           0.098     0.509    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg0
    SLICE_X81Y345        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.739     1.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y345        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C





